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user?s manual all information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by renesas electronics corp. without notice. please review the latest information published by renesas electronics corp. through various m eans, including the renesas electronics corp. website (http://www.renesas.com). v850es/jg3-l user?s manual: hardware rev.7.00 sep, 2011 32 renesas mcu v850es/jx3-l microcontrollers www.renesas.com pd70f3737 pd70f3738 pd70f3792 pd70f3793 pd70f3841 pd70f3842
notice 1. all information included in this document is current as of th e date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas electronics products listed herein, please confirm the latest product information with a renesas electronics sales office. also, please pay regular and careful attention to additional and different information to be disclosed by renesas electronics such as that disclosed through our website. 2. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electronics products or technical information described in this document . no license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property right s of renesas electronics or others. 3. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part . 4. descriptions of circuits, software and other related information in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. when exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. you should not use renesas electronics products or the technology de scribed in this document for any purpose re lating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. renesas electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 6. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or om issions from the information included herein. 7. renesas electronics products are classified according to the following three quality grades: ?standard?, ?high quality?, an d ?specific?. the recommended applications for each renesas electronics product depends on the product?s quality grade, as indicated below. you must check the quality grade of each renesas electronics product before using it in a particular application. you may not use any renesas electronics product for any application categorized as ?specific? without the prior written consent of renesas electronics. further, you may not use any renesas electronics product for any application for which it is not intended without the prior written consent of renesas electronics. renesas electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any renesas electronics product for a n application categorized as ?specific? or for which the product is not intended where you have failed to obtain the prior writte n consent of renesas electronics. the quality grade of each renesas electronics product is ?standard? unless otherwise expressly specified in a renesas electronics data sheets or data books, etc. ?standard?: computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. ?high quality?: transportation equipment (automobiles, trains, ship s, etc.); traffic control systems; anti-disaster systems; an ti- crime systems; safety equipment; and medical equipment not specifically designed for life support. ?specific?: aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life. 8. you should use the renesas electronics products described in this document within the range specified by renesas electronics , especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas electronics shall have no liability for malfunctions o r damages arising out of the use of renesas electronics products beyond such specified ranges. 9. although renesas electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. fur ther, renesas electronics products are not subject to radiation resistance design. please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 10. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compatibility of each renesas electronics product. please use re nesas electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of c ontrolled substances, including without limitation, the eu rohs directive. renesas electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. this document may not be reproduced or duplicated, in any fo rm, in whole or in part, without prior written consent of renes as electronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this document or renesas electronics products, or if you have any other inquiries. (note 1) ?renesas electronics? as used in this document means renesas electronics corporation and also includes its majority- owned subsidiaries. (note 2) ?renesas electronics product(s)? means any product developed or manufactured by or for renesas electronics.
1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. power on/off sequence in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. input of signal during power off state do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. notes for cmos devices 5 6
how to use this manual readers this manual is intended for users who wish to understand the functions of the v850es/jg3-l and design applicati on systems using these products. purpose this manual is intended to give users an understanding of the hardwar e functions of the v850es/jg3-l shown in the organization below. organization this manual is divided into two parts: hardware (this manual) and architecture ( v850es architecture user?s manual ). hardware architecture ? pin functions ? data types ? cpu function ? register set ? on-chip peripheral functions ? instruction format and instruction set ? flash memory programming ? interrupts and exceptions ? electrical specifications ? pipeline operation how to read this manual it is assumed that the readers of this m anual have general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. to understand the overall func tions of the v850es/jg3-l read this manual according to the contents . to find the details of a regi ster where the name is known use appendix c register index . register format the name of the bit whose number is in angle brackets (<>) in the figure of the register format of each register is defined as a reserved word in the device file. to understand the details of an instruction function refer to the v850es architecture user?s manual available separately. to know the electrical specif ications of the v850es/jg3-l see chapter 32 electrical specifications ( pd70f3737, 70f3738). see chapter 33 electrical specifications ( pd70f3792, 70f3793). see chapter 34 electrical specifications ( pd70f3841, 70f3842). the ?yyy bit of the xxx register? is described as the ?xxx.yyy bit? in this manual. note with caution that if ?xxx.yyy? is described as is in a program, however, the compiler/assembler cannot recognize it correctly.
the mark shows major revised points. the revised points can be easily searched by copying an ?? in the pdf file and s pecifying it in the ?find what: ? field. conventions data significance: higher digits on the left and lower digits on the right active low representation: xxx (ove rscore over pin or signal name) memory map address: higher addresses on the top and lower addresses on the bottom note : footnote for item marked with note in the text caution : information requiring particular attention remark : supplementary information numeric representation: binary ... xxxx or xxxxb decimal ... xxxx hexadecimal ... xxxxh prefix indicating power of 2 ( address space, memory capacity): k (kilo): 2 10 = 1,024 m (mega): 2 20 = 1,024 2 g (giga): 2 30 = 1,024 3
related documents the related documents indicated in this pub lication may include preliminary versions. however, preliminary versions are not marked as such. documents related to v850es/jg3-l document name document no. v850es architecture user?s manual u15943e v850es/jg3-l (on-chip usb controlle r) hardware user?s manual u18953e documents related to development tools document name document no. qb-v850esjx3l in-circuit emulator to be prepared qb-v850mini, qb-v850minil on-c hip debug emulator u17638e qb-mini2 on-chip debug emulator with programming function u18371e operation u18512e c language u18513e assembly language u18514e ca850 ver. 3.20 c compiler package link directives u18415e pm+ ver. 6.30 project manager u18416e id850qb ver. 3.40 integrated debugger operation u18604e sm850 ver. 2.50 system simulator operation u16218e sm850 ver. 2.00 or later system si mulator external part user open interface specification u14873e operation u18601e sm+ system simulator user open interface u18212e basics u13430e installation u17419e technical u13431e rx850 ver. 3.20 real-time os task debugger u17420e basics u18165e installation u17421e rx850 pro ver. 3.21 real-time os task debugger u17422e az850 ver. 3.30 system performance analyzer u17423e pg-fp5 flash memory programmer u18865e
other documents document name document no. semiconductor selection guide ? products and packages ? x13769x semiconductor device mount manual note quality grades on renesas semiconductor devices c11531e renesas semiconductor device reliability/quality control system c10983e guide to prevent damage for semiconductor devices by electrostatic discharge (esd) c11892e note see the ?semiconductor device mount manual? website (http://www2.renesas.com/pkg/en/mount/index.html). caution the related doc uments listed above are subject to change without notice. be sure to use the latest versi on of each document when designing. caution: this product uses superflash ? technology licensed from s ilicon storage technology, inc. iecube is a registered trademark of renesas electronics corporation in japan and germany. minicube is a registered trademark of renesas electronics corporation in jap an and germany or a trademark in the united states of america. eeprom is a trademark of re nesas electronics corporation applilet is a registered trademark of renesas electronics in japan, germany , hong kong, china, the republic of korea, the united kingdom, and th e united states of america. windows and windows nt are either regist ered trademarks or trademarks of mi crosoft corporation in the united states and/or other countries. superflash is a registered trademark of silicon storag e technology, inc. in several countries including the united states and japan. pc/at is a trademark of internati onal business machines corporation. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademar ks of sun microsystems, inc. tron is an abbreviation of the r ealtime operating system nucleus. itron is an abbreviati on of industrial tron.
table of contents chapter 1 introduction ...................................................................................................... ........... 20 1.1 general ........................................................................................................................ .............. 20 1.2 features ....................................................................................................................... ............. 22 1.3 application fields ............................................................................................................. ....... 24 1.4 ordering information ........................................................................................................... .... 24 1.5 pin configuration (top view).................................................................................................. 2 5 1.6 function block configurat ion................................................................................................. 31 1.6.1 internal bl ock di agram ......................................................................................................... ............31 1.6.2 internal units ................................................................................................................. ..................32 chapter 2 pin functio ns .................................................................................................... ........... 35 2.1 list of pin functions.......................................................................................................... ...... 35 2.2 pin states ..................................................................................................................... ............. 45 2.3 pin i/o circuit types, i/o buffer power supp lies, and connection of unused pins......... 46 2.4 cautions ....................................................................................................................... ............. 50 chapter 3 cpu functio n ..................................................................................................... ........... 51 3.1 features ....................................................................................................................... ............. 51 3.2 cpu register set............................................................................................................... ....... 52 3.2.1 program regi ster set ........................................................................................................... ............53 3.2.2 system regi ster set ............................................................................................................ .............54 3.3 operation modes ................................................................................................................ ...... 60 3.4 address space .................................................................................................................. ....... 61 3.4.1 cpu address space .............................................................................................................. ..........61 3.4.2 memory map ..................................................................................................................... ..............62 3.4.3 areas .......................................................................................................................... ....................66 3.4.4 wraparound of dat a spac e....................................................................................................... .......74 3.4.5 recommended use of address s pace.............................................................................................74 3.4.6 peripheral i/o regist ers ....................................................................................................... ............78 3.4.7 special r egister s .............................................................................................................. ...............89 3.4.8 registers to be set fi rst ...................................................................................................... .............93 3.4.9 cauti ons....................................................................................................................... ...................94 chapter 4 port functio ns ................................................................................................... ........ 96 4.1 features ....................................................................................................................... ............. 96 4.2 basic port configuration....................................................................................................... .. 96 4.3 port configuration ............................................................. ................................................ ...... 97 4.3.1 port 0 ......................................................................................................................... ...................103 4.3.2 port 1 ......................................................................................................................... ...................107 4.3.3 port 3 ......................................................................................................................... ...................109 4.3.4 port 4 ......................................................................................................................... ...................115 4.3.5 port 5 ......................................................................................................................... ...................117 4.3.6 port 7 ......................................................................................................................... ...................122 4.3.7 port 9 ......................................................................................................................... ...................124 4.3.8 port cm........................................................................................................................ .................132 4.3.9 port ct ........................................................................................................................ .................134 4.3.10 port dh ........................................................................................................................ .................136 4.3.11 port dl........................................................................................................................ ..................138 4.4 block diagrams ................................................................................................................. ..... 141 4.5 port register settings when alternate function is used.................................................. 172
4.6 cautions ....................................................................................................................... ........... 180 4.6.1 cautions on se tting port pins.................................................................................................. .......180 4.6.2 cautions on bit manipulation instru ction for port n r egister (pn) ....................................................183 4.6.3 cautions on on- chip debug pins................................................................................................. ...184 4.6.4 cautions on p05/in tp2/drst pin................................................................................................1 84 4.6.5 cautions on p10, p11, and p53 pi ns when power is turned on .................................................... 184 4.6.6 hysteresis char acterist ics ..................................................................................................... ........184 chapter 5 bus control function ............................ .............................................................. 18 5 5.1 features ....................................................................................................................... ........... 185 5.2 bus control pins ............................................................................................................... ..... 186 5.2.1 pin status when internal rom, in ternal ram, on-chip peripheral i/o , or expanded internal ram is accesse d....................................................................................................................... ................187 5.2.2 pin status in eac h operati on m ode.............................................................................................. ..187 5.3 memory block function ........................................................................................................ 18 8 5.4 external bus interface mode control function ....... ........................................................... 190 5.5 bus access ..................................................................................................................... ........ 191 5.5.1 number of clock cycles required for access ..................................................................................191 5.5.2 bus size setti ng func tion ...................................................................................................... .........192 5.5.3 access according to bus size................................................................................................... .....193 5.6 wait function.................................................................................................................. ........ 200 5.6.1 programmable wa it func tion..................................................................................................... .....200 5.6.2 external wait func tion......................................................................................................... ...........201 5.6.3 relationship between programmabl e wait and exte rnal wa it.........................................................202 5.6.4 programmable address wait func tion ............................................................................................2 03 5.7 idle state insertion func tion................................................................................................. 2 04 5.8 bus hold function .............................................................................................................. ... 205 5.8.1 functional outlin e............................................................................................................. .............205 5.8.2 bus hold pr ocedur e............................................................................................................. ..........206 5.8.3 operation in pow er save mode ................................................................................................... ..206 5.9 bus priority ................................................................................................................... .......... 207 5.10 bus timing..................................................................................................................... ......... 208 5.11 sram connection examples ................................................................................................ 214 chapter 6 clock generator .................................................................................................. .. 216 6.1 overview ....................................................................................................................... .......... 216 6.2 configuration.................................................................................................................. ........ 217 6.3 registers ...................................................................................................................... ........... 219 6.4 operations ..................................................................................................................... ......... 225 6.4.1 operation of each cl ock ........................................................................................................ ........225 6.4.2 clock output functi on .......................................................................................................... ..........226 6.4.3 external clo ck signal input.................................................................................................... .........226 6.5 pll function ................................................................................................................... ....... 226 6.5.1 overvi ew ....................................................................................................................... ................226 6.5.2 regist ers...................................................................................................................... .................227 6.5.3 usage .......................................................................................................................... .................230 6.6 how to connect a resonator ................................................................................................ 231 6.6.1 main clock oscilla tor.......................................................................................................... ............231 6.6.2 subclock o scillato r ............................................................................................................ ............231 chapter 7 16-bit timer/event counter p (tmp) . ............................................................... 234 7.1 overview ....................................................................................................................... .......... 234 7.2 configuration.................................................................................................................. ........ 235
7.2.1 pins used by tmpn.............................................................................................................. .........237 7.2.2 interr upts..................................................................................................................... ..................238 7.3 registers ...................................................................................................................... ........... 239 7.4 operations ..................................................................................................................... ......... 251 7.4.1 interval timer mode (tpnmd2 to tpnmd0 bi ts = 000) .................................................................. 258 7.4.2 external event count mode (tpn md2 to tpnmd0 bits = 001) ...................................................... 269 7.4.3 external trigger pulse output mode (tpnmd2 to tpnmd0 bits = 010) ..........................................278 7.4.4 one-shot pulse output mode (tpn md2 to tpnmd0 bits = 011).................................................... 290 7.4.5 pwm output mode (tpnmd2 to tpnmd0 bi ts = 100) ...................................................................298 7.4.6 free-running timer mode (tpnmd2 to tpnmd0 bi ts = 101) ......................................................... 307 7.4.7 pulse width measurement mode (tpn md2 to tpnmd0 bits = 110).............................................. 323 7.4.8 timer output operati ons ........................................................................................................ ........327 7.5 selector ....................................................................................................................... ............ 328 7.6 cautions ....................................................................................................................... ........... 329 chapter 8 16-bit timer/event counter q (tmq). ............................................................... 330 8.1 functions ...................................................................................................................... .......... 330 8.2 configuration.................................................................................................................. ........ 331 8.2.1 pins used by tmq0 .............................................................................................................. ........333 8.2.2 interr upts..................................................................................................................... ..................333 8.3 registers ...................................................................................................................... ........... 334 8.4 operations ..................................................................................................................... ......... 349 8.4.1 interval timer mode (tq0md2 to tq0md0 bi ts = 000) ................................................................. 356 8.4.2 external event count mode (tq0 md2 to tq0md0 bits = 001) ..................................................... 368 8.4.3 external trigger pulse output mode (tq0md2 to tq0md0 bits = 010) .........................................378 8.4.4 one-shot pulse output mode (tq0 md2 to tq0md0 bits = 011) ................................................... 393 8.4.5 pwm output mode (tq0md2 to tq0md0 bi ts = 100) .................................................................. 403 8.4.6 free-running timer mode (tq0md2 to tq0md0 bi ts = 101)......................................................... 414 8.4.7 pulse width measurement mode (tq0 md2 to tq0md0 bits = 110) ............................................. 434 8.4.8 timer output operati ons ........................................................................................................ ........439 8.5 cautions ....................................................................................................................... ........... 440 chapter 9 16-bit interval timer m (tmm) .... ........................................................................ 441 9.1 features ....................................................................................................................... ........... 441 9.2 configuration.................................................................................................................. ........ 442 9.3 registers ...................................................................................................................... ........... 443 9.4 operation ...................................................................................................................... .......... 445 9.4.1 interval ti mer m ode ............................................................................................................ ...........445 9.4.2 cauti ons....................................................................................................................... .................449 chapter 10 watch time r..................................................................................................... ......... 450 10.1 functions ...................................................................................................................... .......... 450 10.2 configuration.................................................................................................................. ........ 451 10.3 control registers .............................................................................................................. ..... 453 10.4 operation ...................................................................................................................... .......... 457 10.4.1 watch timer operati ons ......................................................................................................... ........457 10.4.2 interval time r operat ions...................................................................................................... ..........458 10.5 cautions ....................................................................................................................... ........... 460 chapter 11 real-time counter ( pd70f3792, 70f3793, 70f3841, 70f3842) ....................... 461 11.1 functions ...................................................................................................................... .......... 461 11.2 configuration.................................................................................................................. ........ 462 11.2.1 pin confi guratio n .............................................................................................................. .............464 11.2.2 interrupt functi ons ............................................................................................................ .............464
11.3 registers ...................................................................................................................... ........... 465 11.4 operation ...................................................................................................................... .......... 480 11.4.1 initial setti ngs ............................................................................................................... .................480 11.4.2 rewriting each counter during r eal-time counter operatio n...........................................................481 11.4.3 reading each counter during real -time counter operatio n ............................................................482 11.4.4 changing intrtc0 interrupt setting duri ng real-time count er operat ion ......................................483 11.4.5 changing intrtc1 interrupt setting duri ng real-time count er operat ion ......................................484 11.4.6 initial intrtc2 in terrupt settings ............................................................................................. .....485 11.4.7 changing intrtc2 interrupt setting duri ng real-time count er operat ion ......................................486 11.4.8 initializing real -time c ounter ................................................................................................. .........487 11.4.9 watch error correction exampl e of real-tim e count er .................................................................... 488 chapter 12 watchdog timer 2 ............................................................................................... .. 492 12.1 functions ...................................................................................................................... .......... 492 12.2 configuration.................................................................................................................. ........ 493 12.3 registers ...................................................................................................................... ........... 494 12.4 operation ...................................................................................................................... .......... 496 chapter 13 real-time output function (rto).. ................................................................. 497 13.1 function ....................................................................................................................... ........... 497 13.2 configuration.................................................................................................................. ........ 498 13.3 registers ...................................................................................................................... ........... 500 13.4 operation ...................................................................................................................... .......... 502 13.5 usage.......................................................................................................................... ............. 503 13.6 cautions ....................................................................................................................... ........... 503 chapter 14 a/d converter ................................................................................................... ...... 504 14.1 overview ....................................................................................................................... .......... 504 14.2 functions ...................................................................................................................... .......... 504 14.3 configuration.................................................................................................................. ........ 505 14.4 registers ...................................................................................................................... ........... 508 14.5 operation ...................................................................................................................... .......... 519 14.5.1 basic oper ation ................................................................................................................ .............519 14.5.2 conversion timi ng .............................................................................................................. ...........520 14.5.3 trigger modes .................................................................................................................. .............521 14.5.4 operati on m ode ................................................................................................................. ...........523 14.5.5 power-fail co mpare mode ........................................................................................................ .....529 14.6 cautions ....................................................................................................................... ........... 536 14.7 how to read a/d converter characteristics table . ........................................................... 541 chapter 15 d/a converter ................................................................................................... ...... 545 15.1 functions ...................................................................................................................... .......... 545 15.2 configuration.................................................................................................................. ........ 546 15.3 registers ...................................................................................................................... ........... 547 15.4 operation ...................................................................................................................... .......... 549 15.4.1 operation in normal mode....................................................................................................... ......549 15.4.2 operation in real -time output mode............................................................................................. ..549 15.4.3 cauti ons....................................................................................................................... .................550 chapter 16 asynchronous serial interface a (uarta) ............................................. 551 16.1 features ....................................................................................................................... ........... 551 16.2 configuration.................................................................................................................. ........ 552 16.2.1 pin functions of each channel .................................................................................................. .....554 16.3 mode switching of uarta and other serial interf aces..................................................... 555 16.3.1 uarta0 and csib4 m ode switch ing ............................................................................................555
16.3.2 uarta1 and i 2 c02 mode swit ching ..............................................................................................556 16.3.3 uarta2 and i 2 c00 mode swit ching ..............................................................................................557 16.4 registers ...................................................................................................................... ........... 558 16.5 interrupt request signals .................................................... ................................................. 5 65 16.6 operation ...................................................................................................................... .......... 566 16.6.1 data fo rmat .................................................................................................................... ...............566 16.6.2 uart trans missi on .............................................................................................................. .........568 16.6.3 continuous transmi ssion proc edure.............................................................................................. 569 16.6.4 uart rec eptio n ................................................................................................................. ...........571 16.6.5 reception errors ............................................................................................................... ............573 16.6.6 parity types and operat ions.................................................................................................... .......575 16.6.7 lin transmission/re ception format .............................................................................................. ..576 16.6.8 sbf trans missi on............................................................................................................... ...........578 16.6.9 sbf rec eptio n .................................................................................................................. .............579 16.6.10 receive data noi se f ilter ...................................................................................................... .....580 16.7 dedicated baud rate generator................................ ........................................................... 581 16.8 cautions ....................................................................................................................... ........... 589 chapter 17 asynchronous serial interface c (uartc) ( pd70f3792, 70f3793, 70f3841, 70f3842) .......................................................................................................... 590 17.1 features ....................................................................................................................... ........... 590 17.2 configuration.................................................................................................................. ........ 591 17.2.1 pin functions of each channel .................................................................................................. .....593 17.3 mode switching of uartc and other serial interf aces..................................................... 594 17.3.1 uartc0 and csib1 m ode switch ing............................................................................................594 17.4 registers ...................................................................................................................... ........... 595 17.5 interrupt request signals .................................................... ................................................. 6 04 17.6 operation ...................................................................................................................... .......... 605 17.6.1 data fo rmat .................................................................................................................... ...............605 17.6.2 uart trans missi on .............................................................................................................. .........607 17.6.3 continuous transmi ssion proc edure.............................................................................................. 608 17.6.4 uart rec eptio n ................................................................................................................. ...........610 17.6.5 reception errors ............................................................................................................... ............612 17.6.6 parity types and operat ions.................................................................................................... .......614 17.6.7 lin transmission/re ception format .............................................................................................. ..615 17.6.8 sbf trans missi on............................................................................................................... ...........617 17.6.9 sbf rec eptio n .................................................................................................................. .............618 17.6.10 receive data noi se f ilter ...................................................................................................... .....619 17.7 dedicated baud rate generator................................ ........................................................... 620 17.8 cautions ....................................................................................................................... ........... 628 chapter 18 clocked serial interface b (csib) ............................................................... 629 18.1 features ....................................................................................................................... ........... 629 18.2 configuration.................................................................................................................. ........ 630 18.2.1 pin functions of each channel .................................................................................................. .....631 18.3 mode switching of csib and other serial interf aces......................................................... 632 18.3.1 csib0 and i 2 c01 mode swit ching .................................................................................................632 18.3.2 csib4 and uarta0 m ode switch ing ............................................................................................633 18.4 registers ...................................................................................................................... ........... 634 18.5 interrupt request signals .................................................... ................................................. 6 43 18.6 operation ...................................................................................................................... .......... 644 18.6.1 single transfer mode (master mode, transmi ssion m ode)............................................................. 644
18.6.2 single transfer mode (master mode, recept ion m ode) .................................................................. 646 18.6.3 single transfer mode (master mode, transmission/rec eption m ode) ............................................. 648 18.6.4 single transfer mode (slave mode, transmi ssion m ode) ............................................................... 650 18.6.5 single transfer mode (slave mode, recept ion m ode) .....................................................................652 18.6.6 single transfer mode (slave mode, transmission/rec eption m ode)................................................ 655 18.6.7 continuous transfer mode (master mode, transmi ssion m ode)..................................................... 657 18.6.8 continuous transfer mode (master mode, recept ion m ode) .......................................................... 659 18.6.9 continuous transfer mode (master m ode, transmission/re ception mode) .....................................662 18.6.10 continuous transfer mode (slave mode, transmi ssion m ode) .................................................. 666 18.6.11 continuous transfer mode (slave mode, recept ion m ode)........................................................ 668 18.6.12 continuous transfer mode (slave m ode, transmission/re ception mode) ...................................671 18.6.13 reception errors............................................................................................................... ........674 18.6.14 clock ti ming................................................................................................................... ...........675 18.7 output pins .................................................................................................................... ......... 677 18.8 baud rate generator ............................................................................................................ . 678 18.8.1 baud rate generatio n ........................................................................................................... .........679 18.9 cautions ....................................................................................................................... ........... 680 chapter 19 i 2 c bus ......................................................................................................................... . 681 19.1 mode switching of i 2 c bus and other serial interfaces...... ............................................... 681 19.1.1 uarta2 and i 2 c00 mode swit ching ..............................................................................................681 19.1.2 csib0 and i 2 c01 mode swit ching .................................................................................................682 19.1.3 uarta1 and i 2 c02 mode swit ching ..............................................................................................683 19.2 features ....................................................................................................................... ........... 684 19.3 configuration.................................................................................................................. ........ 685 19.4 registers ...................................................................................................................... ........... 689 19.5 i 2 c bus mode functions ........................................................................................................ 705 19.5.1 pin confi guratio n .............................................................................................................. .............705 19.6 i 2 c bus definitions and control methods .................. .......................................................... 706 19.6.1 start c onditi on ................................................................................................................ ...............706 19.6.2 addre sses ...................................................................................................................... ...............707 19.6.3 transfer direction specific ation ............................................................................................... ......708 19.6.4 ack ............................................................................................................................ ..................709 19.6.5 stop condi tion ................................................................................................................. ..............710 19.6.6 wait state..................................................................................................................... .................711 19.6.7 wait state canc ellation method ................................................................................................. ....713 19.7 i 2 c interrupt request signals (intiicn)..................... ........................................................... 714 19.7.1 master devic e operat ion........................................................................................................ ........714 19.7.2 slave device operation (when receiving sl ave address data (addr ess matc h)) .............................717 19.7.3 slave device operation (when re ceiving extens ion c ode).............................................................. 721 19.7.4 operation without communica tion................................................................................................ .725 19.7.5 operation when arbitration loss occurs (oper ation as slave after arbitrati on loss) ........................725 19.7.6 operation when arbitration loss occurs ( no communication after arbitrati on loss) ........................727 19.8 interrupt request signal (intiicn) generation ti ming and wait control ........................ 734 19.9 address match detection method ...... .................................................................................. 736 19.10 error detection ................................................................................................................ ....... 736 19.11 extension code ................................................................................................................. ..... 736 19.12 arbitration .................................................................................................................... ........... 737 19.13 wakeup function ................................................................................................................ ... 738 19.14 communication reservation ................................................................................................ 739 19.14.1 when communication reservation function is enabled (iicfn.iicr svn bit = 0)........................739
19.14.2 when communication reservation function is disabled (iicfn.ii crsvn bit = 1) .......................743 19.15 cautions ....................................................................................................................... ........... 744 19.16 communication operations .................................................................................................. 745 19.16.1 master operation in si ngle master system ................................................................................746 19.16.2 master operation in multimaste r system ...................................................................................747 19.16.3 slave oper ation ................................................................................................................ ........750 19.17 timing of data communication ............................................................................................ 753 chapter 20 dma function (dma controller) ..... .............................................................. 760 20.1 features ....................................................................................................................... ........... 760 20.2 configuration.................................................................................................................. ........ 761 20.3 registers ...................................................................................................................... ........... 763 20.4 transfer sources and destinations ..................................................................................... 771 20.5 transfer modes ................................................................................................................. ..... 771 20.6 transfer types ................................................................................................................. ...... 772 20.7 dma channel priorities ......................................................................................................... 773 20.8 time related to dma transfer.............................................................................................. 774 20.9 dma transfer start f actors .................................................................................................. 775 20.10 dma abort factors .............................................................................................................. .. 776 20.11 end of dma transfer ............................................................................................................ . 776 20.12 operation timing............................................................................................................... ..... 776 20.13 cautions ....................................................................................................................... ........... 781 chapter 21 interrupt servicing/exception processing function......................... 786 21.1 features ....................................................................................................................... ........... 786 21.2 non-maskable interrupt s ....................................................................................................... 7 90 21.2.1 operat ion ...................................................................................................................... ................792 21.2.2 restorat ion.................................................................................................................... ................793 21.2.3 np fl ag ........................................................................................................................ ..................794 21.3 maskable interrupts ............................................................................................................ ... 795 21.3.1 operat ion ...................................................................................................................... ................795 21.3.2 restorat ion.................................................................................................................... ................797 21.3.3 priorities of ma skable inte rrupts.............................................................................................. ......798 21.3.4 interrupt control r egister ( xxicn) ............................................................................................. ......802 21.3.5 interrupt mask registers 0 to 3 (imr0 to imr3 ) .............................................................................804 21.3.6 in-service priority register (ispr) ............................................................................................ ......807 21.3.7 id flag ........................................................................................................................ ...................808 21.3.8 watchdog timer mode regi ster 2 (w dtm2) ...................................................................................808 21.4 software exception............................................................................................................. ... 809 21.4.1 operat ion ...................................................................................................................... ................809 21.4.2 restorat ion.................................................................................................................... ................810 21.4.3 ep fl ag ........................................................................................................................ ..................811 21.5 exception trap ................................................................................................................. ...... 812 21.5.1 illegal opcode ................................................................................................................. ...............812 21.5.2 debug tr ap ..................................................................................................................... ...............814 21.6 multiple interrupt servicing cont rol..................................................................................... 816 21.7 external interrupt request input pins (nmi, intp 0 to intp7) ........................................... 817 21.7.1 noise elim inatio n.............................................................................................................. .............817 21.7.2 edge detec tion ................................................................................................................. .............817 21.8 interrupt response time of cpu............................... ........................................................... 823 21.9 periods in which interrupts are not acknowledge d by cpu ........................................... 824 21.10 cautions ....................................................................................................................... ........... 824
21.10.1 restor ed pc .................................................................................................................... .........824 chapter 22 key interrupt function ....................... .............................................................. 825 22.1 function ....................................................................................................................... ........... 825 22.2 pin functions.................................................................................................................. ........ 826 22.3 registers ...................................................................................................................... ........... 826 22.4 cautions ....................................................................................................................... ........... 827 chapter 23 standby functi on ................................................................................................ .. 828 23.1 overview ....................................................................................................................... .......... 828 23.2 registers ...................................................................................................................... ........... 830 23.3 halt mode ...................................................................................................................... ....... 835 23.3.1 setting and operat ion st atus ................................................................................................... ......835 23.3.2 releasing ha lt m ode ............................................................................................................ ......835 23.4 idle1 mode..................................................................................................................... ........ 837 23.4.1 setting and operat ion st atus ................................................................................................... ......837 23.4.2 releasing id le1 m ode ........................................................................................................... ......838 23.5 idle2 mode..................................................................................................................... ........ 840 23.5.1 setting and operat ion st atus ................................................................................................... ......840 23.5.2 releasing id le2 m ode ........................................................................................................... ......841 23.5.3 securing setup time when releasing id le2 m ode......................................................................... 843 23.6 stop mode/low-voltage stop mode ................................................................................. 844 23.6.1 setting and operat ion st atus ................................................................................................... ......844 23.6.2 releasing stop mode/lo w-voltage stop mode ..........................................................................848 23.6.3 re-setting after release of low-voltage st op m ode ..................................................................... 849 23.6.4 securing oscillation stabilization ti me when releasi ng stop mode ..............................................850 23.7 subclock operation mode/low-voltage subclock operation mode ................................ 851 23.7.1 setting and operat ion st atus ................................................................................................... ......851 23.7.2 releasing subclock operation mode .............................................................................................8 55 23.7.3 releasing low-voltage s ubclock operati on mode ..........................................................................855 23.8 sub-idle mode/low-voltage sub-idle mode ......... ........................................................... 856 23.8.1 setting and operat ion st atus ................................................................................................... ......856 23.8.2 releasing sub-idle mode/lo w-voltage sub-id le m ode ............................................................... 859 23.9 rtc backup mode ( pd70f3792, 70f3793, 70f3841, 70f3842 onl y) .............................. 860 23.9.1 r egister s .............................................................................................................. ........................860 23.9.2 rtc backup mode se tting condi tions............................................................................................8 62 23.9.3 rtc backup mode se tting proc edure ............................................................................................86 3 chapter 24 reset function.................................................................................................. ...... 870 24.1 overview ....................................................................................................................... .......... 870 24.2 configuration.................................................................................................................. ........ 871 24.3 register to check reset source ............................... ........................................................... 872 24.4 operation ...................................................................................................................... .......... 873 24.4.1 reset operation vi a reset pin .................................................................................................. ..873 24.4.2 reset operation by watchdog ti mer 2............................................................................................ 876 24.4.3 reset operation by lo w-voltage det ector .......................................................................................8 78 24.4.4 operation immediatel y after re set ends ........................................................................................8 79 24.4.5 reset functi on operat ion ....................................................................................................... ........881 24.5 cautions ....................................................................................................................... ........... 882 chapter 25 clock monito r ................................................................................................... ..... 883 25.1 functions ...................................................................................................................... .......... 883 25.2 configuration.................................................................................................................. ........ 883 25.3 registers ...................................................................................................................... ........... 884
25.4 operation ...................................................................................................................... .......... 885 chapter 26 low-voltage detector (lvi) ............ ................................................................. 888 26.1 functions ...................................................................................................................... .......... 888 26.2 configuration.................................................................................................................. ........ 888 26.3 registers ...................................................................................................................... ........... 889 26.4 operation ...................................................................................................................... .......... 891 26.4.1 to use for inter nal rese t signal............................................................................................... .......891 26.4.2 to use for interr upt........................................................................................................... .............892 chapter 27 crc function .................................................................................................... ........ 893 27.1 functions ...................................................................................................................... .......... 893 27.2 configuration.................................................................................................................. ........ 893 27.3 registers ...................................................................................................................... ........... 894 27.4 operation ...................................................................................................................... .......... 895 27.5 usage.......................................................................................................................... ............. 896 chapter 28 regulator ........................................................................................................ ......... 898 28.1 outline ........................................................................................................................ ............. 898 28.2 operation ...................................................................................................................... .......... 900 chapter 29 option byte..................................................................................................... .......... 901 29.1 program example................................................................................................................ ... 903 chapter 30 flash memory .................................................................................................... ...... 904 30.1 features ....................................................................................................................... ........... 904 30.2 memory configuratio n........................................................................................................... 905 30.3 functional outline............................................................................................................. ..... 907 30.4 rewriting by dedicated flash memory programmer . ........................................................ 910 30.4.1 programming environm ent........................................................................................................ ....910 30.4.2 communicati on m ode ............................................................................................................. ......911 30.4.3 interface...................................................................................................................... ..................913 30.4.4 flash memory cont rol ........................................................................................................... ........920 30.4.5 selection of co mmunicati on m ode ................................................................................................ 921 30.4.6 communicati on comm ands ......................................................................................................... ..922 30.4.7 pin connection in on- board progra mming .....................................................................................923 30.5 rewriting by self programming... ......................................................................................... 927 30.5.1 overvi ew ....................................................................................................................... ................927 30.5.2 featur es....................................................................................................................... .................928 30.5.3 standard self pr ogramming flow ................................................................................................. ..929 30.5.4 flash f uncti ons................................................................................................................ ..............930 30.5.5 pin proc essi ng ................................................................................................................. .............930 30.5.6 internal res ources used........................................................................................................ .........931 chapter 31 on-chip debug function ....................... .............................................................. 932 31.1 debugging with dcu ............................................................................................................. 934 31.1.1 connection circui t exam ple ..................................................................................................... ......934 31.1.2 interface signal s.............................................................................................................. ..............935 31.1.3 mask func tion.................................................................................................................. ..............936 31.1.4 regist ers...................................................................................................................... .................937 31.1.5 operat ion ...................................................................................................................... ................938 31.1.6 cauti ons....................................................................................................................... .................939 31.2 debugging without using dcu ..................................... ....................................................... 940 31.2.1 circuit connecti on exam ples .................................................................................................... .....940 31.2.2 mask func tion.................................................................................................................. ..............942 31.2.3 allocation of us er res ources................................................................................................... .......942
31.2.4 cauti ons....................................................................................................................... .................949 31.3 rom security function ......................................................................................................... 9 50 31.3.1 security id .................................................................................................................... ................950 31.3.2 setti ng........................................................................................................................ ...................951 chapter 32 electrical specifications ( pd70f3737, 70f3738)....................................... 952 32.1 absolute maximum ratings .................................................................................................. 952 32.2 capacitance .................................................................................................................... ........ 954 32.3 operating conditions ........................................................................................................... . 954 32.4 oscillator characteris tics..................................................................................................... . 955 32.4.1 main clock oscillato r characte ristics .......................................................................................... ....955 32.4.2 subclock oscillator characteri stics ............................................................................................ ....959 32.4.3 pll characte ristics............................................................................................................ ............961 32.4.4 internal oscillator characteri stics ............................................................................................ .......961 32.5 regulator characteristics ..................................................................................................... 9 61 32.6 dc characteristics ............................................................................................................. .... 962 32.6.1 pin characte ristics............................................................................................................ .............962 32.6.2 supply current c haracteri stics ................................................................................................. ......964 32.6.3 data retention characteri stics (in st op m ode)............................................................................. 965 32.7 ac characteristics ............................................................................................................. .... 966 32.7.1 measurement conditi ons ......................................................................................................... ......966 32.7.2 clkout output timi ng........................................................................................................... .......967 32.7.3 bus ti ming ..................................................................................................................... ................968 32.7.4 power on/power o ff/reset timing................................................................................................ ....981 32.8 peripheral function characteristics .......................... .......................................................... 982 32.8.1 interrupt timi ng ............................................................................................................... ...............982 32.8.2 key return timi ng.............................................................................................................. .............982 32.8.3 timer ti ming ................................................................................................................... ...............982 32.8.4 uart ti ming.................................................................................................................... ..............983 32.8.5 csib ti ming .................................................................................................................... ...............983 32.8.6 i 2 c bus mode..................................................................................................................... ............985 32.8.7 a/d conv erter .................................................................................................................. ..............986 32.8.8 d/a conv erter .................................................................................................................. ..............987 32.8.9 lvi circuit char acteristics .................................................................................................... ..........987 32.9 flash memory programming characteristics ........... .......................................................... 988 chapter 33 electrical specifications ( pd70f3792, 70f3793)..................................... 990 33.1 absolute maximum ratings .................................................................................................. 990 33.2 capacitance .................................................................................................................... ........ 992 33.3 operating conditions ........................................................................................................... . 992 33.4 oscillator characteris tics..................................................................................................... . 993 33.4.1 main clock oscillato r characte ristics .......................................................................................... ....993 33.4.2 subclock oscillator characteri stics ............................................................................................ ....996 33.4.3 pll characte ristics............................................................................................................ ............998 33.4.4 internal oscillator characteri stics ............................................................................................ .......998 33.5 regulator characteristics ..................................................................................................... 9 99 33.6 dc characteristics ............................................................................................................. .. 1000 33.6.1 pin characte ristics............................................................................................................ ...........1000 33.6.2 supply current c haracteri stics ................................................................................................. ....1002 33.6.3 data retention characteri stics (in st op m ode)........................................................................... 1003 33.7 ac characteristics ............................................................................................................. .. 1004 33.7.1 measurement conditi ons ......................................................................................................... ....1004
33.7.2 clkout output timi ng........................................................................................................... .....1005 33.7.3 bus ti ming ..................................................................................................................... ..............1006 33.7.4 power on/power o ff/reset timing................................................................................................ ..1019 33.8 peripheral function characteristics .......................... ........................................................ 1020 33.8.1 interrupt timi ng ............................................................................................................... .............1020 33.8.2 key return timi ng.............................................................................................................. ...........1020 33.8.3 timer ti ming ................................................................................................................... .............1020 33.8.4 uart ti ming.................................................................................................................... ............1021 33.8.5 csib ti ming .................................................................................................................... .............1021 33.8.6 i 2 c bus mode..................................................................................................................... ..........1023 33.8.7 a/d conv erter .................................................................................................................. ............1024 33.8.8 d/a conv erter .................................................................................................................. ............1025 33.8.9 lvi circuit char acteristics .................................................................................................... ........1025 33.8.10 rtc back-up mode char acterist ics ........................................................................................1026 33.9 flash memory programming characteristics ........... ........................................................ 1027 chapter 34 electrical specifications ( pd70f3841, 70f3842)...................................... 1029 34.1 absolute maximum ratings ................................................................................................ 1029 34.2 capacitance .................................................................................................................... ...... 1031 34.3 operating conditions .......................................................................................................... 1 031 34.4 oscillator characteris tics.................................................................................................... 1 032 34.4.1 main clock oscillato r characte ristics .......................................................................................... ..1032 34.4.2 subclock oscillator characteri stics ............................................................................................ ..1035 34.4.3 pll characte ristics............................................................................................................ ..........1037 34.4.4 internal oscillator characteri stics ............................................................................................ .....1037 34.5 regulator characteristics ................................................................................................... 103 8 34.6 dc characteristics ............................................................................................................. .. 1039 34.6.1 pin characte ristics............................................................................................................ ...........1039 34.6.2 supply current c haracteri stics ................................................................................................. ....1041 34.6.3 data retention characteri stics (in st op m ode)........................................................................... 1042 34.7 ac characteristics ............................................................................................................. .. 1043 34.7.1 measurement conditi ons ......................................................................................................... ....1043 34.7.2 clkout output timi ng........................................................................................................... .....1044 34.7.3 bus ti ming ..................................................................................................................... ..............1045 34.7.4 power on/power o ff/reset timing................................................................................................ ..1052 34.8 peripheral function characteristics .......................... ........................................................ 1053 34.8.1 interrupt timi ng ............................................................................................................... .............1053 34.8.2 key return timi ng.............................................................................................................. ...........1053 34.8.3 timer ti ming ................................................................................................................... .............1053 34.8.4 uart ti ming.................................................................................................................... ............1054 34.8.5 csib ti ming .................................................................................................................... .............1054 34.8.6 i 2 c bus mode..................................................................................................................... ..........1056 34.8.7 a/d conv erter .................................................................................................................. ............1057 34.8.8 d/a conv erter .................................................................................................................. ............1058 34.8.9 lvi circuit char acteristics .................................................................................................... ........1058 34.8.10 rtc back-up mode char acterist ics ........................................................................................1059 34.9 flash memory programming characteristics ........... ........................................................ 1060 chapter 35 package drawings .............................................................................................. 10 62 chapter 36 recommended soldering condition s......................................................... 1065 appendix a development tools............................................................................................. 10 67 a.1 software package ............................................................................................................... . 1069
a.2 language processing software ......................................................................................... 1069 a.3 control software ............................................................................................................... ... 1069 a.4 debugging tools (hardware) .............................................................................................. 1070 a.4.1 when using iecube ? qb-v850essx2, qb -v850esjx3 l ........................................................1070 a.4.2 when using minicu be qb-v850m ini .......................................................................................1073 a.4.3 when using minicu be2 qb-mi ni2............................................................................................1074 a.5 debugging tools (software) ............................................................................................... 1075 a.6 embedded software............................................................................................................. 1 076 a.7 flash memory writing tools ............................................................................................... 1077 appendix b major differences between prod ucts..................................................... 1078 appendix c register index .................................................................................................. ..... 1081 appendix d instruction set list ........................................................................................... 1092 d.1 conventions.................................................................................................................... ...... 1092 d.2 instruction set (in alphabetical order) .................. ............................................................ 1095
r01uh0165ej0700 rev.7.00 page 20 of 1113 sep 22, 2011 r01uh0165ej0700 rev.7.00 sep 22, 2011 v850es/jg3-l renesas mcu chapter 1 introduction the v850es/jg3-l is one of the products in the renesas electronics v850 single-chip microcontroller series designed for low-power operation for real-time control applications. 1.1 general the v850es/jg3-l is a 32-bit single-chip microcontro ller that includes the v850es cpu core and peripheral functions such as rom/ram, timer/counters, serial interfaces, an a/d converter, and a d/a converter. in addition to high real-time response characteristics and 1-clock-pitch basic instructions, the v850es/jg3-l features multiply instructions, satura ted operation instructions, bit manipulati on instructions, etc., realized by a hardware multiplier, as optimum instruct ions for digital servo control applicati ons. moreover, as a real-time control system, the v850es/jg3-l enables an extremely high cost -performance for applications that require super low power consumption, such as digital cameras, electrical power meters, and mobile terminals. table 1-1 lists the produc ts of the v850es/jg3-l.
v850es/jg3-l chapter 1 introduction r01uh0165ej0700 rev.7.00 page 21 of 1113 sep 22, 2011 table 1-1. v850es/jx3-l product list product name pd70f3841 pd70f3842 pd70f3792 pd70f3793 pd70f3737 pd70f3738 flash memory 768 kb 1 mb 384 kb 512 kb 128 kb 256 kb internal memory ram 80 kb note1 80 kb note1 32 kb 40 kb 8 kb 16 kb logical space 64 mb memory space external memory area 15 mb external bus interface address buses: 22 bits address data buses: 8/16 bits multiplexed bus mode (capable of separate output) address buses: 22 bits address data buses: 8/16 bits separate bus/multiplexed bus mode selectable general-purpose register 32 bits 32 registers main clock (oscillation frequency) ceramic/crystal (pll mode: f x = 2.5 to 5 mhz (multiplication by 4), clock through mode: f x = 2.5 to 10 mhz) external clock (pll mode: f x = 2.5 to 5 mhz (multiplication by 4), clock through mode: f x = 2.5 to 5 mhz) subclock (oscillation frequency) crystal (f xt = 32.768 khz) internal oscillator f r = 220 khz (typ.) clocks minimum instruction execution time 50 ns (main clock (f xx ) = 20 mhz) i/o ports i/o: 83 (5 v tolerant/n-ch open drain output selectable: 31) i/o: 84 (5 v tolerant/n-ch open drain output selectable: 31) 16-bit tmp 6 channels 16-bit tmq 1 channel 16-bit tmm 1 channel watch timer 1 channel real-time counter 1 channel ? timer wdt 1 channel real-time output function 4 bits 1 channel, 2 bits 1 channel or 6 bits 1 channel 10-bit a/d converter 12 channels 8-bit d/a converter 2 channels serial interface csib: 3 channels uarta/csib: 1 channel csib/i 2 c bus: 1 channel uarta/i 2 c bus: 2 channels uarta: 3 channels uartc; 1 channels csib: 3 channels uarta/csib: 1 channel csib/i 2 c bus: 1 channel uarta/i 2 c bus: 2 channels dma controller 4 channels (transfer target: on-chip peripheral i/o, internal ram, expanded internal ram external memory) 4 channels (transfer target: on-chip peripheral i/o, internal ram, external memory) external 9 (9) note2 9 (9) note2 interrupt source internal 55 48 halt/idle1/idle2/stop/subclock/sub-idle/l ow-voltage stop/low-voltage subclock/ low-voltage sub-idle modes power-save function rtc backup mode ? reset factor reset pin input, watchdog timer 2 (wdt2), clock monitor (clm), low-voltage detector (lvi) on-chip debugging minicube ? , minicube2 supported 2.2 to 3.6 v@5 mhz, 2.7 to 3.6 v@20 mhz operating power supply voltage 2.0 to 3.6 v@2.5 mhz ? operating ambient temperature ? 40 to +85 c package 100-pin lqfp (14 14 mm) 121-pin fbga (8 8 mm) 100-pin lqfp (14 14 mm) 100-pin lqfp (14 20 mm) 121-pin fbga (8 8 mm) notes1. including 24 kb of expanded internal ram area. 2. the figure in parentheses indicates the number of ex ternal interrupts that can release the stop mode.
v850es/jg3-l chapter 1 introduction r01uh0165ej0700 rev.7.00 page 22 of 1113 sep 22, 2011 1.2 features { minimum instruction execution time: 50 ns (operating on main clock (f xx ) of 20 mhz: v dd = 2.7 to 3.6 v) 200 ns (operating on main clock (f xx ) of 5 mhz: v dd = 2.2 to 3.6 v) 400 ns (operating on main clock (f xx ) of 2.5 mhz: v dd = 2.0 to 3.6 v) note 30.5 p s (operating on subclock (f xt ) of 32.768 khz) note p pd70f3792, 70f3793, 70f 3841, 70f3842 only { general-purpose registers: 32 bits u 32 registers { cpu features: signed multiplication (16 u 16 o 32): 1 to 2 clocks signed multiplication (32 u 32 o 64): 1 to 5 clocks saturated operations (overflow and underflow detection functions included) most instructions can be executed in 1 clock cycle by using 32-bit risc-based 5-stage pipeline architecture instruction fetching from internal rom and accessing internal ram for data can be executed separately, by using harvard architecture high code efficiency achieved by using variable length instructions 32-bit shift instruction: 1 clock cycle bit manipulation instructions load/store instructions with long/short format { memory space: 64 mb of linear address space (for programs and data) external expansion: up to 16 mb (including 1 mb used as internal rom/ram) x internal memory: ram: 8/16/32/40 /80 kb (see table 1-1 ) flash memory: 128 k/256 k/384 k/512 k/768 k/1 mb (see table 1-1 ) x external bus interface: x separate bus/multiplexed bus output selectable ( p pd70f3737, 70f3738, 70f3792, 70f3793) x multiplexed bus mode (capable of separate output) ( p pd70f3841, 70f3842) 8/16 bit data bus sizing function wait function x programmable wait function x external wait function idle state function bus hold function { interrupts and exceptions: internal external non-maskable maskable total non-maskable maskable total p pd70f3737 1 47 48 1 8 9 p pd70f3738 1 47 48 1 8 9 p pd70f3792 1 54 55 1 8 9 p pd70f3793 1 54 55 1 8 9 p pd70f3841 1 54 55 1 8 9 p pd70f3842 1 54 55 1 8 9 software exceptions: 32 sources exception trap: 2 sources
v850es/jg3-l chapter 1 introduction r01uh0165ej0700 rev.7.00 page 23 of 1113 sep 22, 2011 { ports: i/o ports: 84 ( p pd70f3737, 70f3738) 83 ( p pd70f3792, 70f3793, 70f3841, 70f3842) { timer function: 16-bit interv al timer m (tmm): 1 channel 16-bit timer/event counter p (tmp): 6 channels 16-bit timer/event counter q (tmq): 1 channel watch timer: 1 channel watchdog timer: 1 channel { real-time counter note : 1 channel { real-time output port: 6 bits u 1 channel { serial interface: asynchronous serial interface a (uarta) 3-wire variable-length serial interface b (csib) i 2 c bus interface (i 2 c) uarta/csib: 1 channel uarta/i 2 c: 2 channels csib/i 2 c: 1 channel csib: 3 channels uarta note : 3 channels uartc note : 1 channel { a/d converter: 10-bit resolution: 12 channels { d/a converter: 8-bit resolution: 2 channels { dma controller: 4 channels { dcu (debug control unit): jtag interface { clock generator: during main clock or subclock operation 7-level cpu clock (f xx , f xx /2, f xx /4, f xx /8, f xx /16, f xx /32, f xt ) clock-through mode/pll mode selectable { internal oscillator clock: 220 khz (typ.) { power-save functions: halt/idle1/idle2/stop/low-voltage stop/subclock/sub-idle/ low-voltage subclock/low-voltage sub-idle mode (/rtc backup mode) note { package: 100-pin plastic lqfp (14 u 20) 100-pin plastic lqfp (fine pitch) (14 u 14) 121-pin plastic fbga (8 u 8) { power supply voltage: v dd = 2.0 v to 3.6 v (2.5 mhz) note v dd = 2.2 v to 3.6 v (5 mhz) v dd = 2.7 v to 3.6 v (20 mhz) note p pd70f3792, 70f3793, 70f 3841, 70f3842 only
v850es/jg3-l chapter 1 introduction r01uh0165ej0700 rev.7.00 page 24 of 1113 sep 22, 2011 1.3 application fields digital cameras, electrical power me ters, mobile terminals, digital home electronics, other consumer devices 1.4 ordering information part number package internal flash memory pd70f3737gc-ueu-ax pd70f3738gc-ueu-ax pd70f3737gf-gas-ax note pd70f3738gf-gas-ax note pd70f3737f1-cah-a pd70f3738f1-cah-a pd70f3792gc-ueu-ax pd70f3793gc-ueu-ax pd70f3792f1-cah-a pd70f3793f1-cah-a pd70f3841gc-ueu-ax pd70f3842gc-ueu-ax pd70f3841f1-cah-a pd70f3842f1-cah-a 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic lqfp (14 20) 100-pin plastic lqfp (14 20) 121-pin plastic fbga (8 8 ) 121-pin plastic fbga (8 8 ) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic lqfp (fine pitch) (14 14) 121-pin plastic fbga (8 8 ) 121-pin plastic fbga (8 8 ) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic lqfp (fine pitch) (14 14) 121-pin plastic fbga (8 8 ) 121-pin plastic fbga (8 8 ) 128 kb 256 kb 128 kb 256 kb 128 kb 256 kb 384 kb 512 kb 384 kb 512 kb 768 kb 1 mb 768 kb 1 mb note under development remark the v850es/jg3-l is a lead-free product.
v850es/jg3-l chapter 1 introduction r01uh0165ej0700 rev.7.00 page 25 of 1113 sep 22, 2011 1.5 pin configuration (top view) 100-pin plastic lqfp (14 20) pd70f3737gf-gas-ax note pd70f3738gf-gas-ax note note under development p72/ani2 p73/ani3 p74/ani4 p75/ani5 p76/ani6 p77/ani7 p78/ani8 p79/ani9 p710/ani10 p711/ani11 pdh1/a17 pdh0/a16 pdl15/ad15 pdl14/ad14 pdl13/ad13 pdl12/ad12 pdl11/ad11 pdl10/ad10 pdl9/ad9 pdl8/ad8 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 p34/tip10/top10 p35/tip11/top11 p36 p37 ev ss ev dd p38/txda2/sda00 p39/rxda2/scl00 p50/tiq01/kr0/toq01/rtp00 p51/tiq02/kr1/toq02/rtp01 p52/tiq03/kr2/toq03/rtp02/ddi p53/sib2/kr3/tiq00/toq00/rtp03/ddo p54/sob2/kr4/rtp04/dck p55/sckb2/kr5/rtp05/dms p90/a0/kr6/txda1/sda02 p91/a1/kr7/rxda1/scl02 p92/a2/tip41/top41 p93/a3/tip40/top40 p94/a4/tip31/top31 p95/a5/tip30/top30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 pdl7/ad7 pdl6/ad6 pdl5/ad5/flmd1 pdl4/ad4 pdl3/ad3 pdl2/ad2 pdl1/ad1 pdl0/ad0 ev dd ev ss pct6/astb pct4/rd pct1/wr1 pct0/wr0 pcm3/hldrq pcm2/hldak pcm1/clkout pcm0/wait pdh3/a19 pdh2/a18 p915/a15/intp6/tip50/top50 p914/a14/intp5/tip51/top51 p913/a13/intp4 p912/a12/sckb3 p911/a11/sob3 p910/a10/sib3 p99/a9/sckb1 p98/a8/sob1 p97/a7/sib1/tip20/top20 p96/a6/tip21/top21 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 p71/ani1 p70/ani0 av ref0 av ss p10/ano0 p11/ano1 av ref1 pdh4/a20 pdh5/a21 flmd0 note 1 v dd regc note 2 v ss x1 x2 reset xt1 xt2 p02/nmi p03/intp0/adtrg p04/intp1 p05/intp2/drst p06/intp3 p40/sib0/sda01 p41/sob0/scl01 p42/sckb0 p30/txda0/sob4 p31/rxda0/intp7/sib4 p32/ascka0/sckb4/tip00/top00 p33/tip01/top01 notes 1. the flmd0 pin is used in flash programming. connect this pin to v ss in the normal operation mode. 2. connect the regc pin to v ss via a 4.7 f (recommended value) capacitor.
v850es/jg3-l chapter 1 introduction r01uh0165ej0700 rev.7.00 page 26 of 1113 sep 22, 2011 100-pin plastic lqfp (fine pitch) (14 14) (1/2) pd70f3737gc-ueu-ax pd70f3738gc-ueu-ax 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 p70/ani0 p71/ani1 p72/ani2 p73/ani3 p74/ani4 p75/ani5 p76/ani6 p77/ani7 p78/ani8 p79/ani9 p710/ani10 p711/ani11 pdh1/a17 pdh0/a16 pdl15/ad15 pdl14/ad14 pdl13/ad13 pdl12/ad12 pdl11/ad11 pdl10/ad10 pdl9/ad9 pdl8/ad8 pdl7/ad7 pdl6/ad6 pdl5/ad5/flmd1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 p31/rxda0/intp7/sib4 p32/ascka0/sckb4/tip00/top00 p33/tip01/top01 p34/tip10/top10 p35/tip11/top11 p36 p37 ev ss ev dd p38/txda2/sda00 p39/rxda2/scl00 p50/tiq01/kr0/toq01/rtp00 p51/tiq02/kr1/toq02/rtp01 p52/tiq03/kr2/toq03/rtp02/ddi p53/sib2/kr3/tiq00/toq00/rtp03/ddo p54/sob2/kr4/rtp04/dck p55/sckb2/kr5/rtp05/dms p90/a0/kr6/txda1/sda02 p91/a1/kr7/rxda1/scl02 p92/a2/tip41/top41 p93/a3/tip40/top40 p94/a4/tip31/top31 p95/a5/tip30/top30 p96/a6/tip21/top21 p97/a7/sib1/tip20/top20 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 pdl4/ad4 pdl3/ad3 pdl2/ad2 pdl1/ad1 pdl0/ad0 ev dd ev ss pct6/astb pct4/rd pct1/wr1 pct0/wr0 pcm3/hldrq pcm2/hldak pcm1/clkout pcm0/wait pdh3/a19 pdh2/a18 p915/a15/intp6/tip50/top50 p914/a14/intp5/tip51/top51 p913/a13/intp4 p912/a12/sckb3 p911/a11/sob3 p910/a10/sib3 p99/a9/sckb1 p98/a8/sob1 av ref0 av ss p10/ano0 p11/ano1 av ref1 pdh4/a20 pdh5/a21 flmd0 note 1 v dd regc note 2 v ss x1 x2 reset xt1 xt2 p02/nmi p03/intp0/adtrg p04/intp1 p05/intp2/drst p06/intp3 p40/sib0/sda01 p41/sob0/scl01 p42/sckb0 p30/txda0/sob4 notes 1. the flmd0 pin is used in flash programming. connect this pin to v ss in the normal operation mode. 2. connect the regc pin to v ss via a 4.7 f (recommended value) capacitor.
v850es/jg3-l chapter 1 introduction r01uh0165ej0700 rev.7.00 page 27 of 1113 sep 22, 2011 100-pin plastic lqfp (fine pitch) (14 14) (2/2) pd70f3792gc-ueu-ax pd70f3793gc-ueu-ax pd70f3841gc-ueu-ax pd70f3842gc-ueu-ax 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 p70/ani0 p71/ani1 p72/ani2 p73/ani3 p74/ani4 p75/ani5 p76/ani6 p77/ani7 p78/ani8 p79/ani9 p710/ani10 p711/ani11 pdh1/a17 pdh0/a16 pdl15/ad15 pdl14/ad14 pdl13/ad13 pdl12/ad12 pdl11/ad11 pdl10/ad10 pdl9/ad9 pdl8/ad8 pdl7/ad7 pdl6/ad6 pdl5/ad5/flmd1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 p31/rxda0/intp7/sib4 p32/ascka0/sckb4/tip00/top00 p33/tip01/top01 p34/tip10/top10 p35/tip11/top11 p36txda3 p37/rxda3 ev ss ev dd p38/txda2/sda00 p39/rxda2/scl00 p50/tiq01/kr0/toq01/rtp00 p51/tiq02/kr1/toq02/rtp01 p52/tiq03/kr2/toq03/rtp02/ddi p53/sib2/kr3/tiq00/toq00/rtp03/ddo p54/sob2/kr4/rtp04/dck p55/sckb2/kr5/rtp05/dms p90/a0/kr6/txda1/sda02 p91/a1/kr7/rxda1/scl02 p92/a2/tip41/top41/txda4 p93/a3/tip40/top40rxda4 p94/a4/tip31/top31/txda5 p95/a5/tip30/top30/rxda5 p96/a6/txdc0/tip21/top21 p97/a7/sib1/rxdc0/tip20/top20 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 pdl4/ad4 pdl3/ad3 pdl2/ad2 pdl1/ad1 pdl0/ad0 ev dd ev ss pct6/astb pct4/rd pct1/wr1 pct0/wr0 pcm3/hldrq pcm2/hldak pcm1/clkout pcm0/wait pdh3/a19 pdh2/a18 p915/a15/intp6/tip50/top50 p914/a14/intp5/tip51/top51 p913/a13/intp4 p912/a12/sckb3 p911/a11/sob3 p910/a10/sib3 p99/a9/sckb1 p98/a8/sob1 av ref0 av ss p10/ano0 p11/ano1 av ref1 pdh4/a20 p02/nmi/a21 flmd0 note 1 v dd regc note 2 v ss x1 x2 reset xt1 xt2 rv dd p03/intp0/adtrg/rtc1hz p04/intp1/rtcdiv/rtccl p05/intp2/drst p06/intp3 p40/sib0/sda01 p41/sob0/scl01 p42/sckb0 p30/txda0/sob4 notes 1. the flmd0 pin is used in flash programming. connect this pin to v ss in the normal operation mode. 2. connect the regc pin to v ss via a 4.7 f (recommended value) capacitor.
v850es/jg3-l chapter 1 introduction r01uh0165ej0700 rev.7.00 page 28 of 1113 sep 22, 2011 121-pin plastic fbga (8 8) pf70f3737f1-cah-a pf70f3738f1-cah-a pd70f3792f1-cah-a pd70f3793f1-cah-a pd70f3841f1-cah-a pd70f3842f1-cah-a 1 2 3 4 5 6 7 8 9 10 11 index mark a b c d e f g h j k l l k j h g f e d c b a index mark top view bottom view (1/2) pin no. pin name pin no. pin name pin no. pin name a1 av ref0 c1 av ss e1 regc note 1 a2 av ref0 c2 av ss e2 regc note 1 a3 p70/ani0 c3 p72/ani2 e3 p10/ano0 a4 p74/ani4 c4 p76/ani6 e4 p11/ano1 a5 p78/ani8 c5 p710/ani10 e5 ev ss a6 ev ss c6 pdh0/a16 e6 ev ss a7 pdl11/ad11 c7 pdl13/ad13 e7 ev ss a8 pdl8/ad8 c8 pdl10/ad10 e8 pct0/wr0 a9 pdl6/ad6 c9 pdl2/ad2 e9 pcm3/hldrq a10 pdl5/ad5/flmd1 c10 pdl1/ad1 e10 pcm2/hldak a11 ev dd c11 pdl0/ad0 e11 ev ss b1 av ref0 d1 v dd f1 x1 b2 av ref1 d2 v dd note 2 , rv dd note 3 f2 x2 b3 p71/ani1 d3 p73/ani3 f3 flmd0 note 4 b4 p75/ani5 d4 p77/ani7 f4 pdh4/a20 b5 p79/ani9 d5 p711/ani11 f5 ev ss b6 pdl15/ad15 d6 pdh1/a17 f6 ev ss b7 pdl12/ad12 d7 pdl14/ad14 f7 ev ss b8 pdl9/ad9 d8 pct6/astb f8 pdh3/a19 b9 pdl7/ad7 d9 pct4/rd f9 pdh2/a18 b10 pdl4/ad4 d10 pct1/wr1 f10 pcm1/clkout b11 pdl3/ad3 d11 ev dd f11 pcm0/wait notes 1. connect the e1 and e2 pins by using the sh ortest possible pattern and connect them to v ss via a 4.7 f (recommended value) capacitor. 2. pd70f3737, 70f3738 only 3. pd70f3792, 70f3793, 70f 3841, 70f3842 only 4. the flmd0 pin is used in flash programming. connect this pin to v ss in the normal operation mode.
v850es/jg3-l chapter 1 introduction r01uh0165ej0700 rev.7.00 page 29 of 1113 sep 22, 2011 (2/2) pin no. pin name pin no. pin name pin no. pin name g1 v ss h9 p911/a11/sob3 k6 ev dd g2 v ss h10 p910/a10/sib3 k7 p51/tiq02/kr1/ toq02 /rtp01 g3 p03/intp0/adtrg (/rtc1hz) note1 h11 p99/a9/sckb1 k8 p54/sob2/kr4/rtp04/dck pdh5/a21 note2 g4 p02/nmi/a21 note1, 3 j1 v ss k9 p92/a2/tip41/top41 (/txda4) note1 g5 ev ss j2 p02/nmi(/a21) note1, 3 k10 p95/a5/tip30/top30 (/rxda5) note1 g6 ev ss j3 p05/intp2/drst k11 p96/a6(/txdc0) note1 /tip21/top21 g7 ev ss j4 p06/intp3 l1 ev ss g8 p915/a15/intp6/tip50/top50 j5 p35/tip11/top11 l2 p42/sckb0 g9 p914/a14/intp5/tip51/top51 j6 p37(/rxda3) note1 l3 p30/txda0/sob4 g10 p913/a13/intp4 j7 p52/tiq03/kr2/toq03 /rtp02/ddi l4 p32/ascka0/sckb4/tip00 /top00 g11 p912/a12/sckb3 j8 p55/sckb2/kr5/rtp05/dms l5 ev ss h1 xt1 j9 p93/a3/tip40/top40 (/rxda4) note1 l6 ev dd h2 xt2 j10 p98/a8/sob1 l7 p50/tiq01/kr0/toq01/rtp00 h3 reset j11 p97/a7/sib1(/rxdc0) note1 /tip20/top20 l8 p53/sib2/kr3/tiq00/toq00 /rtp03/ddo h4 p04/intp1(/rtcdiv/rtccl) note1 k1 p40/sib0/sda01 l9 p91/a1/kr7/rxda1/scl02 h5 p36(/txda3) note1 k2 p41/sob0/scl01 l10 p94/a4/tip31/top31 (/txda5) note1 h6 p38/txda2/sda00 k3 p31/rxda0/intp7/sib4 l11 ev dd h7 p39/rxda2/scl00 k4 p33/tip01/top01 ? ? h8 p90/a0/kr6/txda1/sda02 k5 p34/tip10/top10 ? ? notes1. pd70f3792, 70f3793, 70f 3841, 70f3842 only 2. pd70f3737, 70f3738 only 3. the p02/nmi/a21 pin is assigned to the pin numbers j2 and g4. to use the functions of this pin, use only one of the pin numbers and open the other pin number. if not us ing the p02/nmi/a21 pin, perform processing for only one pin number in accordance with 2.3 pin i/o circuit types, i/o buffer power supplies, and connection of unused pins , and open the other pin number ( pd70f3792, 70f3793, 70f3841, 70f3842).
v850es/jg3-l chapter 1 introduction r01uh0165ej0700 rev.7.00 page 30 of 1113 sep 22, 2011 pin functions a0 to a21: ad0 to ad15: adtrg: ani0 to ani11: ano0, ano1: ascka0: astb: av ref0 , av ref1 : av ss : clkout: dck: ddi: ddo: dms: drst: ev dd : ev ss : flmd0, flmd1: hldak: hldrq: intp0 to intp7: kr0 to kr7: nmi: p02 to p06: p10, p11: p30 to p39: p40 to p42: p50 to p55: p70 to p711: p90 to p915: pcm0 to pcm3: pct0, pct1, pct4, pct6: pdh0 to pdh5: address bus address/data bus a/d trigger input analog input analog output asynchronous serial clock address strobe analog reference voltage analog v ss clock output debug clock debug data input debug data output debug mode select debug reset power supply for external pin ground for external pin flash programming mode hold acknowledge hold request external interrupt input key return non-maskable interrupt request port 0 port 1 port 3 port 4 port 5 port 7 port 9 port cm port ct port dh pdl0 to pdl15: rd: regc: reset: rtc1hz, rtccl, rtcdiv: rtp00 to rtp05: rv dd : rxda0 to rxda5, rxdc0: sckb0 to sckb4: scl00 to scl02: sda00 to sda02: sib0 to sib4: sob0 to sob4: tip00, tip01, tip10, tip11, tip20, tip21, tip30, tip31, tip40, tip41, tip50, tip51: tiq00 to tiq03, top00, top01, top10, top11, top20, top21, top30, top31, top40, top41, top50, top51, toq00 to toq03: txda0 to txda5, txdc0: v dd : v ss : wait: wr0: wr1: x1, x2: xt1, xt2: port dl read strobe regulator control reset real-time counter clock output real-time output port power supply for rtc receive data serial clock serial clock serial data serial input serial output timer input timer output transmit data power supply ground wait lower byte write strobe upper byte write strobe crystal for main clock crystal for subclock
v850es/jg3-l chapter 1 introduction r01uh0165ej0700 rev.7.00 page 31 of 1113 sep 22, 2011 1.6 function block configuration 1.6.1 internal block diagram nmi intp0 to intp7 toq00 to toq03 tiq00 to tiq03 top00 to top50, top01 to top51 tip00 to tip50, tip01 to tip51 kr0 to kr7 i 2 c: 3 ch sda00 to sda02 scl00 to scl02 txda0 to txda5 rxda0 to rxda5 ascka0 uarta: 6 ch note 5 dcu rtp00 to rtp05 rto : 1 ch crc rom ram pc alu cpu a0 to a21 ad0 to ad15 timer/counter function serial interface function hldrq wr0, wr1 drst dms ddi dck ddo sob0 to sob4 sib0 to sib4 sckb0 to sckb4 csib: 5 ch dma intc ano0, ano1 av ref1 adtrg av ref0 av ss ani0 to ani11 ev dd ev ss flash controller flmd0 flmd1 cg clkout x1 x2 xt1 xt2 reset pll debug function interrupt function bcu pcm0 to pcm3 pct0, pct1, pct4, pct6 pdh0 to pdh4, pdh5 note4 pdl0 to pdl15 p90 to p915 p70 to p711 p50 to p55 p40 to p42 p30 to p39 p10, p11 p02 to p06 clm expanded internal ram (24kb) note6 v dd v ss regc lvi hldak astb rd wait 16-bit timer/ event counter q: 1 ch 16-bit timer/ event counter p: 6 ch watchdog timer 2: 1ch watch timer: 1ch key interrupt function note 1 note 2 general-purpose registers 32 bits 32 multiplier 16 16 32 system registers 32-bit barrel shifter internal oscillator 16-bit interval timer m: 1 ch real-time counter: 1 ch note 3 a/d converter d/a converter regulator rv dd note 3 regulator note 3 ports rtc1hz rtccl rtcdiv txdc0 rxdc0 uartc: 1 ch note 3 notes 1. pd70f3737: 128 kb pd70f3738: 256 kb pd70f3792: 384 kb pd70f3793: 512 kb pd70f3841: 768 kb pd70f3842: 1 mb 2. pd70f3737: 8 kb pd70f3738: 16 kb pd70f3792: 32 kb pd70f3793: 40 kb pd70f3841, 70f3842: 56 kb 3. pd70f3792, 70f3793, 70f 3841, 70f3842 only 4. pd70f3737, 70f3738 only 5. pd70f3792, 70f3793, 70f 3841, 70f3842 only, pd70f3737, 70f3738 is 3 channels 6. pd70f3841, 70f842 only
v850es/jg3-l chapter 1 introduction r01uh0165ej0700 rev.7.00 page 32 of 1113 sep 22, 2011 1.6.2 internal units (1) cpu the cpu uses five-stage pipeline control to enable singl e-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. other dedicated on-chip hardware, such as a multiplier (16 bits 16 bits 32 bits) and a barrel shifter (32 bits) contribute to faster complex processing. (2) bus control unit (bcu) the bcu starts a required external bus cycle based on the physical address obtained by the cpu. when an instruction is fetched from external memory space and the cpu does not send a bus cycle start request, the bcu generates a prefetch address and prefetches the instruction code. the pref etched instruction code is stored in an instruction queue. (3) flash memory (rom) this is a 1 m/784 k/512 k/384 k/256 k/128 kb fl ash memory mapped to addresses 0000000h to 00fffffh/0000000h to 00bffffh/0000000h to 00 7ffffh/0000000h to 005ffffh/0000000h to 003ffffh/0000000h to 001ffffh. it can be accessed from the cpu in one cl ock during instruction fetch. (4) ram this is a 80 note /40/32/16/8 kb ram mapped to addresses 3ff1000h to 03ffefffh + 03fa000h to 03fffffh /3ff5000h to 3ffefffh/3 ff7000h to 3ffefffh /3ffb000h to 3ffefffh/3ffd000h to 3ffefffh. it can be accessed from the cpu in one clock dur ing data access. note including 24 kb of expanded internal ram area. (5) interrupt controller (intc) this controller handles hardware interrupt requests (n mi, intp0 to intp7) from on-chip peripheral hardware and external hardware. eight levels of interrupt prio rities can be specified for these interrupt requests, and multiplexed interrupt servicing control can be performed. (6) clock generator (cg) a main clock oscillator and subclock oscillator are pr ovided and generate the main clock oscillation frequency (f x ) and subclock frequency (f xt ), respectively. there are two modes: in the clock-through mode, f x is used as the main clock frequency (f xx ) as is. in the pll mode, f x is used multiplied by 4. the cpu clock frequency (f cpu ) can be selected from among f xx , f xx /2, f xx /4, f xx /8, f xx /16, f xx /32, and f xt . (7) internal oscillator an internal oscillator is provided on chip. the oscillati on frequency is 220 khz (typ). the internal oscillator supplies the clock for watchdog timer 2 and timer m. (8) timer/counter six-channel 16-bit timer/event counter p (tmp), one- channel 16-bit timer/event counter q (tmq), and one- channel 16-bit interval timer m (tmm), are provided on chip. (9) watch timer this timer counts the reference time period (0.5 s) for counting the clock (the 32.768 khz subclock or the 32.768 khz f brg clock from the prescaler). the watch timer can also be used as an interval timer based on the main clock.
v850es/jg3-l chapter 1 introduction r01uh0165ej0700 rev.7.00 page 33 of 1113 sep 22, 2011 (10) real-time counter (for watch) ( pd70f3792, 70f3793, 70f3841, 70f3842 only) the real-time counter count s the reference time (one second) for watch counting based on the subclock (32.768 khz) or main clock. this can simultaneously be used as the interval timer based on the main clock. hardware counters dedicated to year, month, day of week, day, hour, minute, and second are provided, and can count up to 99 years. (11) watchdog timer 2 a watchdog timer is provided on chip to detect inadv ertent program loops, system abnormalities, etc. the internal oscillator clock, the main clock, or t he subclock can be selected as the source clock. watchdog timer 2 generates a non-maskable interrupt re quest signal (intwdt2) or a system reset signal (wdt2res) after an overflow occurs. (12) serial interface the v850es/jg3-l includes three kinds of serial inte rfaces: asynchronous serial interface a (uarta), asynchronous serial interface c (uartc), 3-wire variable-length serial interface b (csib), and an i 2 c bus interface (i 2 c). (a) pd70f3737, 70f3738 in the case of uarta, data is transferred via the txda0 to txda2 pins and rxda0 to rxda2 pins. in the case of csib, data is transferred via the sob0 to sob4 pins, sib0 to sib4 pins, and sckb0 to sckb4 pins. in the case of i 2 c, data is transferred via the sda00 to sda02 and scl00 to scl02 pins. (b) pd70f3792, 70f3793, 70f3841, 70f3842 in the case of uarta, data is transferred via the txda0 to txda5 pins and rxda0 to rxda5 pins. in the case of uartc, data is transferred via the txdc0 pin and rxdc0 pin. in the case of csib, data is transferred via the sob0 to sob4 pins, sib0 to sib4 pins, and sckb0 to sckb4 pins. in the case of i2c, data is transferred via the sda00 to sda02 and scl00 to scl02 pins. (13) a/d converter this 10-bit a/d converter includes 12 analog input pins. conversion is performed using the successive approximation method. (14) d/a converter a two-channel, 8-bit-resolution d/a converter that uses the r-2r ladder method is provided on chip. (15) dma controller a 4-channel dma controller is provided on chip. this controller transfers data between the internal ram and on-chip peripheral i/o devices in response to inte rrupt requests sent by on-chip peripheral i/o. (16) key interrupt function a key interrupt request signal (intkr) can be generated by inputting a falling edge to the key input pins (8 channels). (17) real-time output function the real-time output function transfe rs preset 6-bit data to output la tches upon the occurrence of a timer compare register match signal.
v850es/jg3-l chapter 1 introduction r01uh0165ej0700 rev.7.00 page 34 of 1113 sep 22, 2011 (18) crc function a crc operation circuit that generates a 16-bit crc (c yclic redundancy check) code upon the setting of 8-bit data is provided on-chip. (19) dcu (debug control unit) an on-chip debug function that uses the jtag (joint test action group) communication specifications is provided. switching between the normal port func tion and on-chip debugging function is done with the control pin input level and the ocdm register. (20) ports the following general-purpose port functions and control pin functions are available. table 1-2. port functions port i/o alternate function p0 5-bit i/o nmi, external interrupt, a/d converter trigger, debug reset, real time counter output note 1 p1 2-bit i/o d/a converter analog output p3 10-bit i/o external interrupt, serial interface, timer i/o p4 3-bit i/o serial interface p5 6-bit i/o timer i/o, real-time output, key interrupt input, serial interface, debug i/o p7 12-bit i/o a/d converter analog input p9 16-bit i/o external address bus, serial interface, key interrupt input, timer i/o, external interrupt pcm 4-bit i/o external control signal pct 4-bit i/o external control signal pdh 6-bit i/o note 2 , 5-bit i/o note 1 external address bus pdl 16-bit i/o external address/data bus notes1. pd70f3792, 70f3793, 70f 3841, 70f3842 only 2 . pd70f3737, 70f3738 only
v850es/jg3-l chapter 2 pin functions r01uh0165ej0700 rev.7.00 page 35 of 1113 sep 22, 2011 chapter 2 pin functions 2.1 list of pin functions the functions of the pins in the v850es/jg3-l are described below. there are three types of pin i/o buffer power supplies: av ref0 , av ref1 , and ev dd . the relationship between these power supplies and the pins is described below. table 2-1. pin i/o buffer power supplies power supply corresponding pins av ref0 port 7 av ref1 port 1 ev dd reset, ports 0, 3 to 5, 9, cm, ct, dh, dl, flmd0
v850es/jg3-l chapter 2 pin functions r01uh0165ej0700 rev.7.00 page 36 of 1113 sep 22, 2011 (1) port functions (1/3) pin no. function gf gc f1 i/o description alternate function p02 19 17 note 1 , 7 note 2 j2, g4 note 2 nmi(/a21) note 2 p03 20 18 g3 intp0/adtrg(/rtc1hz) note 2 p04 21 19 h4 intp1(/rtcdiv/rtccl) note 2 p05 note 3 22 20 j3 intp2/drst p06 23 21 j4 i/o port 0 (refer to 4.3.1 ) 5-bit i/o port input/output can be specified in 1-bit units. n-ch open-drain output can be specified in 1-bit units. 5 v tolerant. intp3 p10 5 3 e3 ano0 p11 6 4 e4 i/o port 1 (refer to 4.3.2 ) 2-bit i/o port input/output can be specified in 1-bit units. ano1 p30 27 25 l3 txda0/sob4 p31 28 26 k3 rxda0/intp7/sib4 p32 29 27 l4 ascka0/sckb4/tip00/top00 p33 30 28 k4 tip01/top01 p34 31 29 k5 tip10/top10 p35 32 30 j5 tip11/top11 p36 33 31 h5 txda3 note 2 p37 34 32 j6 rxda3 note 2 p38 37 35 h6 txda2/sda00 p39 38 36 h7 i/o port 3 (refer to 4.3.3 ) 10-bit i/o port input/output can be specified in 1-bit units. n-ch open-drain output can be specified in 1-bit units. 5 v tolerant. rxda2/scl00 p40 24 22 k1 sib0/sda01 p41 25 23 k2 sob0/scl01 p42 26 24 l2 i/o port 4 (refer to 4.3.4 ) 3-bit i/o port input/output can be specified in 1-bit units. n-ch open-drain output can be specified in 1-bit units. 5 v tolerant. sckb0 p50 39 37 l7 tiq01/kr0/toq01/rtp00 p51 40 38 k7 tiq02/kr1/toq02/rtp01 p52 41 39 j7 tiq03/kr2/toq03/rtp02/ddi p53 42 40 l8 sib2/kr3/tiq00/toq00/rtp03/ddo p54 43 41 k8 sob2/kr4/rtp04/dck p55 44 42 j8 i/o port 5 (refer to 4.3.5 ) 6-bit i/o port input/output can be specified in 1-bit units. n-ch open-drain output can be specified in 1-bit units. 5 v tolerant. sckb2/kr5/rtp05/dms notes1. pd70f3737, 70f3738 only. 2. pd70f3792, 70f3793, 70f 3841, 70f3842 only. 3. incorporates a pull-down resistor. it can be di sconnected by clearing the ocdm.ocdm0 bit to 0. remark gf: 100-pin plastic lqfp (14 20) ( pd70f3737, 70f3738 only) gc: 100-pin plastic lqfp (fine pitch) (14 14) f1: 121-pin plastic fbga (8 8)
v850es/jg3-l chapter 2 pin functions r01uh0165ej0700 rev.7.00 page 37 of 1113 sep 22, 2011 (2/3) pin no. function gf gc f1 i/o description alternate function p70 2 100 a3 ani0 p71 1 99 b3 ani1 p72 100 98 c3 ani2 p73 99 97 d3 ani3 p74 98 96 a4 ani4 p75 97 95 b4 ani5 p76 96 94 c4 ani6 p77 95 93 d4 ani7 p78 94 92 a5 ani8 p79 93 91 b5 ani9 p710 92 90 c5 ani10 p711 91 89 d5 i/o port 7 (refer to 4.3.6 ) 12-bit i/o port input/output can be specified in 1-bit units. ani11 p90 45 43 h8 a0/kr6/txda1/sda02 p91 46 44 l9 a1/kr7/rxda1/scl02 p92 47 45 k9 a2/tip41/top41(/txda4) note p93 48 46 j9 a3/tip40/top40(/rxda4) note p94 49 47 l10 a4/tip31/top31(/txda5) note p95 50 48 k10 a5/tip30/top30(/rxda5 ) note p96 51 49 k11 a6(/txdc0) note /tip21/top21 p97 52 50 j11 a7/sib1(/rxdc0) note /tip20/top20 p98 53 51 j10 a8/sob1 p99 54 52 h11 a9/sckb1 p910 55 53 h10 a10/sib3 p911 56 54 h9 a11/sob3 p912 57 55 g11 a12/sckb3 p913 58 56 g10 a13/intp4 p914 59 57 g9 a14/intp5/tip51/top51 p915 60 58 g8 i/o port 9 (refer to 4.3.7 ) 16-bit i/o port input/output can be specified in 1-bit units. n-ch open-drain output can be specified in 1-bit units. 5 v tolerant.(p90 to p96) a15/intp6/tip50/top50 note pd70f3792, 70f3793, 70f 3841, 70f3842 only. remark gf: 100-pin plastic lqfp (14 20) ( pd70f3737, 70f3738 only) gc: 100-pin plastic lqfp (fine pitch) (14 14) f1: 121-pin plastic fbga (8 8)
v850es/jg3-l chapter 2 pin functions r01uh0165ej0700 rev.7.00 page 38 of 1113 sep 22, 2011 (3/3) pin no. function gf gc f1 i/o description alternate function pcm0 63 61 f11 wait pcm1 64 62 f10 clkout pcm2 65 63 e10 hldak pcm3 66 64 e9 i/o port cm (refer to 4.3.8 ) 4-bit i/o port input/output can be specified in 1-bit units. hldrq pct0 67 65 e8 wr0 pct1 68 66 d10 wr1 pct4 69 67 d9 rd pct6 70 68 d8 i/o port ct (refer to 4.3.9 ) 4-bit i/o port input/output can be specified in 1-bit units. astb pdh0 89 87 c6 a16 pdh1 90 88 d6 a17 pdh2 61 59 f9 a18 pdh3 62 60 f8 a19 pdh4 8 6 f4 a20 pdh5 note 9 7 g4 i/o port dh (refer to 4.3.10 ) 6-bit i/o port ( pd70f3737, 70f3738) input/output can be specified in 1-bit units. 5-bit i/o port ( pd70f3792, 70f3793) input/output can be specified in 1-bit units. a21 pdl0 73 71 c11 ad0 pdl1 74 72 c10 ad1 pdl2 75 73 c9 ad2 pdl3 76 74 b11 ad3 pdl4 77 75 b10 ad4 pdl5 78 76 a10 ad5/flmd1 pdl6 79 77 a9 ad6 pdl7 80 78 b9 ad7 pdl8 81 79 a8 ad8 pdl9 82 80 b8 ad9 pdl10 83 81 c8 ad10 pdl11 84 82 a7 ad11 pdl12 85 83 b7 ad12 pdl13 86 84 c7 ad13 pdl14 87 85 d7 ad14 pdl15 88 86 b6 i/o port dl (refer to 4.3.11 ) 16-bit i/o port input/output can be specified in 1-bit units. ad15 note pd70f3792, 70f3793, 70f 3841, 70f3842 only. remark gf: 100-pin plastic lqfp (14 20) ( pd70f3737, 70f3738 only) gc: 100-pin plastic lqfp (fine pitch) (14 14) f1: 121-pin plastic fbga (8 8)
v850es/jg3-l chapter 2 pin functions r01uh0165ej0700 rev.7.00 page 39 of 1113 sep 22, 2011 (2) non-port functions (1/6) pin no. function gf gc f1 i/o description alternate function a0 45 43 h8 p90/kr6/txda1/sda02 a1 46 44 l9 p91/kr7/rxda1/scl02 a2 47 45 k9 p92/tip41/top41 (/txda4) note1 a3 48 46 j9 p93/tip40/top40 (/rxda4) note1 a4 49 47 l10 p94/tip31/top31(/txda5 ) note1 a5 50 48 k10 p95/tip30/top30 (/rxda5 ) note1 a6 51 49 k11 p96 (/txdc0 ) note1 /tip21/top21 a7 52 50 j11 p97/sib1 (/rxdc0 ) note1 /tip20/top20 a8 53 51 j10 p98/sob1 a9 54 52 h11 p99/sckb1 a10 55 53 h10 p910/sib3 a11 56 54 h9 p911/sob3 a12 57 55 g11 p912/sckb3 a13 58 56 g10 p913/intp4 a14 59 57 g9 p914/intp5/tip51/top51 a15 60 58 g8 output address bus for external memory (when using separate bus) n-ch open-drain output selectable. 5 v tolerant (a0 to a6). p915/intp6/tip50/top50 a16 89 87 c6 pdh0 a17 90 88 d6 pdh1 a18 61 59 f9 pdh2 a19 62 60 f8 pdh3 a20 8 6 f4 pdh4 p02/nmi note1 a21 9 7 j2, g4 note1 output address bus for external memory pdh5 note2 ad0 73 71 c11 pdl0 ad1 74 72 c10 pdl1 ad2 75 73 c9 pdl2 ad3 76 74 b11 pdl3 ad4 77 75 b10 pdl4 ad5 78 76 a10 pdl5/flmd1 ad6 79 77 a9 pdl6 ad7 80 78 b9 pdl7 ad8 81 79 a8 pdl8 ad9 82 80 b8 pdl9 ad10 83 81 c8 pdl10 ad11 84 82 a7 pdl11 ad12 85 83 b7 pdl12 ad13 86 84 c7 pdl13 ad14 87 85 d7 pdl14 ad15 88 86 b6 i/o address bus/data bus for external memory pdl15 notes1. pd70f3792, 70f3793, 70f 3841, 70f3842 only. 2. pd70f3737, 70f3738 only. remark gf: 100-pin plastic lqfp (14 20) ( pd70f3737, 70f3738 only) gc: 100-pin plastic lqfp (fine pitch) (14 14) f1: 121-pin plastic fbga (8 8)
v850es/jg3-l chapter 2 pin functions r01uh0165ej0700 rev.7.00 page 40 of 1113 sep 22, 2011 (2/6) pin no. function gf gc f1 i/o description alternate function adtrg 20 18 g3 input a/d converter external trigger input. 5 v tolerant. p03/intp0 (/rtc1hz) note1 ani0 2 100 a3 p70 ani1 1 99 b3 p71 ani2 100 98 c3 p72 ani3 99 97 d3 p73 ani4 98 96 a4 p74 ani5 97 95 b4 p75 ani6 96 94 c4 p76 ani7 95 93 d4 p77 ani8 94 92 a5 p78 ani9 93 91 b5 p79 ani10 92 90 c5 p710 ani11 91 89 d5 input analog voltage input for a/d converter p711 ano0 5 3 e3 p10 ano1 6 4 e4 output analog voltage output for d/a converter p11 ascka0 29 27 l4 input uarta0 baud rate clock input. 5 v tolerant. p32/sckb4/tip00/top00 astb 70 68 d8 output address strobe signal output for external memory pct6 av ref0 3 1 a1, a2, b1 reference voltage input for a/ d converter/positive power supply for port 7 ? av ref1 7 5 b2 ? reference voltage input for d/ a converter/positive power supply for port 1 ? av ss 4 2 c1, c2 ? ground potential for a/d and d/a converters (same potential as v ss ) ? clkout 64 62 f10 output internal system clock output pcm1 dck 43 41 k8 input debug clock input. 5 v tolerant. p54/sob2/kr4/rtp04 ddi 41 39 j7 input debug data input. 5 v tolerant. p52/tiq03/kr2/toq03/rtp02 ddo note 2 42 40 l8 output debug data output. n-ch open-drain output selectable. 5 v tolerant. p53/sib2/kr3/tiq00/toq00/ rtp03 dms 44 42 j8 input debug mode select input. 5 v tolerant. p55/sckb2/kr5/rtp05 drst 22 20 j3 input debug reset input. 5 v tolerant. p05/intp2 ev dd 36, 72 34, 70 note 3 ? positive power supply for external (same potential as v dd ) ? ev ss 35, 71 33, 69 note 4 ? ground potential for external (same potential as v ss ) ? flmd0 10 8 f3 ? flmd1 78 76 a10 input flash memory programming mode setting pin pdl5/ad5 hldak 65 63 e10 output bus hold acknowledge output pcm2 hldrq 66 64 e9 input bus hold request input pcm3 notes 1. pd70f3792, 70f3793, 70f 3841, 70f3842 only. 2. in the on-chip debug mode, high-level output is forcibly set. 3. a11, d11, k6, l6, l11 4. a6, e5 to e7, e11, f5 to f7, g5 to g7, l1, l5 remark gf: 100-pin plastic lqfp (14 20) ( pd70f3737, 70f3738 only) gc: 100-pin plastic lqfp (fine pitch) (14 14) f1: 121-pin plastic fbga (8 8)
v850es/jg3-l chapter 2 pin functions r01uh0165ej0700 rev.7.00 page 41 of 1113 sep 22, 2011 (3/6) pin no. function gf gc f1 i/o description alternate function intp0 20 18 g3 p03/adtrg (/rtc1hz) note3 intp1 21 19 h4 p04 (/rtcdiv/rtccl) note3 intp2 22 20 j3 p05/drst intp3 23 21 j4 p06 intp4 58 56 g10 p913/a13 intp5 59 57 g9 p914/a14/tip51/top51 intp6 60 58 g8 p915/a15/tip50/top50 intp7 28 26 k3 input external interrupt request input (maskable, analog noise elimination). analog noise elimination or digital noise elimination selectable for intp3 pin. 5 v tolerant. p31/rxda0/sib4 kr0 note 1 39 37 l7 p50/tiq01/toq01/rtp00 kr1 note 1 40 38 k7 p51/tiq02/toq02/rtp01 kr2 note 1 41 39 j7 p52/tiq03/toq03/rtp02/ddi kr3 note 1 42 40 l8 p53/sib2/tiq00/toq00/ rtp03/ddo kr4 note 1 43 41 k8 p54/sob2/rtp04/dck kr5 note 1 44 42 j8 p55/sckb2/rtp05/dms kr6 note 1 45 43 h8 p90/a0/txda1/sda02 kr7 note 1 46 44 l9 input key interrupt input (on-chip analog noise eliminator). 5 v tolerant. p91/a1/rxda1/scl02 nmi note 2 19 17 note4 , 7 note3 j2, g4 note3 input external interrupt input (non-maskable, analog noise elimination). 5 v tolerant. p02 (/a21) note3 rd 69 67 d9 output read strobe signal output for external memory pct4 regc 12 10 e1,e2 ? connection of regulator output stabilization capacitance (4.7 f (recommended value)) ? reset 16 14 h3 input system reset input ? rtc1hz note 3 ? 18 g3 output real-time counter correction clock (1 hz) output p03/intp0/adtrg rtcll note 3 ? 19 h4 output real-time counter clock (32 khz primary oscillation) output p04/intp1/rtcdiv rtcdiv note 3 ? 19 h4 output real-time counter clock (32 khz division) output p04/intp1/rtccl rtp00 39 37 l7 p50/tiq01/kr0/toq01 rtp01 40 38 k7 p51/tiq02/kr1/toq02 rtp02 41 39 j7 p52/tiq03/kr2/toq03/ddi rtp03 42 40 l8 p53/sib2/kr3/tiq00/toq00/ddo rtp04 43 41 k8 p54/sob2/kr4/dck rtp05 44 42 j8 output real-time output port. n-ch open-drain output selectable. 5 v tolerant. p55/sckb2/kr5/dms notes1. connect a pull-up resistor externally. 2. the nmi pin alternately functions as the p02 pin. it functions as the p02 pin after reset. to enable the nmi function, set the pmc0.pmc02 bit to 1. the in itial setting of the nmi pin is ?no edge detected?. select the nmi pin valid edge using the intf0 and intr0 registers. 3. pd70f3792, 70f3793, 70f 3841, 70f3842 only 4. pd70f3737, 70f3738 only remark gf: 100-pin plastic lqfp (14 20) ( pd70f3737, 70f3738 only) gc: 100-pin plastic lqfp (fine pitch) (14 14) f1: 121-pin plastic fbga (8 8)
v850es/jg3-l chapter 2 pin functions r01uh0165ej0700 rev.7.00 page 42 of 1113 sep 22, 2011 (4/6) pin no. function gf gc f1 i/o description alternate function rxda0 28 26 k3 p31/intp7/sib4 rxda1 46 44 l9 p91/a1/kr7/scl02 rxda2 38 36 h7 p39/scl00 rxda3 note ? 32 j6 p37 rxda4 note ? 46 j9 p93/a3/tip40/top40 rxda5 note ? 48 k10 serial receive data input (uarta0 to uarta2) 5 v tolerant. p95/a5/tip30/top30 rxdc0 note ? 50 j11 input serial receive data input (uartc0) p97/a7/sib1/tip20/top20 rv dd note ? 17 d2 ? positive power supply for rtc (same potential as v dd ) ? sckb0 26 24 l2 p42 sckb1 54 52 h11 p99/a9 sckb2 44 42 j8 p55/kr5/rtp05/dms sckb3 57 55 g11 p912/a12 sckb4 29 27 l4 i/o serial clock i/o (csib0 to csib4) n-ch open-drain output selectable. 5 v tolerant. p32/ascka0/tip00/top00 scl00 38 36 h7 p39/rxda2 scl01 25 23 k2 p41/sob0 scl02 46 44 l9 i/o serial clock i/o (i 2 c00 to i 2 c02) n-ch open-drain output selectable. 5 v tolerant. p91/a1/kr7/rxda1 sda00 37 35 h6 p38/txda2 sda01 24 22 k1 p40/sib0 sda02 45 43 h8 i/o serial transmit/receive data i/o (i 2 c00 to i 2 c02) n-ch open-drain output selectable. 5 v tolerant. p90/a0/kr6/txda1 sib0 24 22 k1 p40/sda01 sib1 52 50 j11 p97/a7 (/rxdc0 ) note /tip20/top20 sib2 42 40 l8 p53/kr3/tiq00/toq00/rtp03/ ddo sib3 55 53 h10 p910/a10 sib4 28 26 k3 input serial receive data input (csib0 to csib4) 5 v tolerant. p31/rxda0/intp7 sob0 25 23 k2 p41/scl01 sob1 53 51 j10 p98/a8 sob2 43 41 k8 p54/kr4/rtp04/dck sob3 56 54 h9 p911/a11 sob4 27 25 l3 output serial transmit data output (csib0 to csib4) n-ch open-drain output selectable. 5 v tolerant. p30/txda0 note pd70f3792, 70f3793, 70f 3841, 70f3842 only. remark gf: 100-pin plastic lqfp (14 20) ( pd70f3737, 70f3738 only) gc: 100-pin plastic lqfp (fine pitch) (14 14) f1: 121-pin plastic fbga (8 8)
v850es/jg3-l chapter 2 pin functions r01uh0165ej0700 rev.7.00 page 43 of 1113 sep 22, 2011 (5/6) pin no. function gf gc f1 i/o description alternate function tip00 29 27 l4 external event count input/cap ture trigger input/external trigger input (tmp0). 5 v tolerant. p32/ascka0/sckb4/top00 tip01 30 28 k4 capture trigger input (tmp0). 5 v tolerant. p33/top01 tip10 31 29 k5 external event count input/cap ture trigger input/external trigger input (tmp1). 5 v tolerant. p34/top10 tip11 32 30 j5 capture trigger input (tmp1). 5 v tolerant. p35/top11 tip20 52 50 j11 external event count input/cap ture trigger input/external trigger input (tmp2). 5 v tolerant. p97/a7/sib1/top20 tip21 51 49 k11 capture trigger input (tmp2). 5 v tolerant. p96/a6/top21 tip30 50 48 k10 external event count input/cap ture trigger input/external trigger input (tmp3). 5 v tolerant. p95/a5/top30 tip31 49 47 l10 capture trigger input (tmp3). 5 v tolerant. p94/a4/top31 tip40 48 46 j9 external event count input/cap ture trigger input/external trigger input (tmp4). 5 v tolerant. p93/a3/top40 tip41 47 45 k9 capture trigger input (tmp4). 5 v tolerant. p92/a2/top41 tip50 60 58 g8 external event count input/cap ture trigger input/external trigger input (tmp5). 5 v tolerant. p915/a15/intp6/top50 tip51 59 57 g9 input capture trigger input (tmp5). 5 v tolerant. p914/a14/intp5/top51 tiq00 42 40 l8 external event count input/cap ture trigger input/external trigger input (tmq0). 5 v tolerant. p53/sib2/kr3/toq00/rtp03 /ddo tiq01 39 37 l7 p50/kr0/toq01/rtp00 tiq02 40 38 k7 p51/kr1/toq02/rtp01 tiq03 41 39 j7 input capture trigger input (tmq0). 5 v tolerant. p52/kr2/toq03/rtp02/ddi remark gf: 100-pin plastic lqfp (14 20) ( pd70f3737, 70f3738 only) gc: 100-pin plastic lqfp (fine pitch) (14 14) f1: 121-pin plastic fbga (8 8)
v850es/jg3-l chapter 2 pin functions r01uh0165ej0700 rev.7.00 page 44 of 1113 sep 22, 2011 (6/6) pin no. function gf gc f1 i/o description alternate function top00 29 27 l4 p32/ascka0/sckb4/tip00 top01 30 28 k4 timer output (tmp0) n-ch open-drain output selectable. 5 v tolerant. p33/tip01 top10 31 29 k5 p34/tip10 top11 32 30 j5 timer output (tmp1) n-ch open-drain output selectable. 5 v tolerant. p35/tip11 top20 52 50 j11 p97/a7/sib1/tip20 top21 51 49 k11 timer output (tmp2) n-ch open-drain output selectable. 5 v tolerant. p96/a6/tip21 top30 50 48 k10 p95/a5/tip30 top31 49 47 l10 timer output (tmp3) n-ch open-drain output selectable. 5 v tolerant. p94/a4/tip31 top40 48 46 j9 p93/a3/tip40 top41 47 45 k9 timer output (tmp4) n-ch open-drain output selectable. 5 v tolerant. p92/a2/tip41 top50 60 58 g8 p915/a15/intp6/tip50 top51 59 57 g9 output timer output (tmp5) n-ch open-drain output selectable. 5 v tolerant. p914/a14/intp5/tip51 toq00 42 40 l8 p53/sib2/kr3/tiq00/rtp03/ ddo toq01 39 37 l7 p50/tiq01/kr0/rtp00 toq02 40 38 k7 p51/tiq02/kr1/rtp01 toq03 41 39 j7 output timer output (tmq0) n-ch open-drain output selectable. 5 v tolerant. p52/tiq03/kr2/rtp02/ddi txda0 27 25 l3 p30/sob4 txda1 45 43 h8 p90/a0/kr6/sda02 txda2 37 35 h6 p38/sda00 txda3 note ? 31 h5 p36 txda4 note ? 45 k9 p92/a2/tip41/top41 txda5 note ? 47 l10 serial transmit data output (uarta0 to uarta5) n-ch open-drain output selectable. 5 v tolerant. p94/a4/tip31/top31 txdc0 note ? 49 k11 output serial transmit data output (uartac) n-ch open-drain output selectable. 5 v tolerant. p96/a6/tip21/top21 v dd 11 9 d1, d2 ? positive power supply pi n for internal circuits ? v ss 13 11 g1, g2, j1 ? ground potential for internal circuits ? wait 63 61 f11 input external wait input pcm0 wr0 67 65 e8 write strobe for external memory (lower 8 bits) pct0 wr1 68 66 d10 output write strove for external memory (higher 8 bits) pct1 x1 14 12 f1 input ? x2 15 13 f2 ? connection of resonator for main clock ? xt1 17 15 h1 input ? xt2 18 16 h2 ? connection of resonator for subclock ? note pd70f3792, 70f3793, 70f 3841, 70f3842 only. remark gf: 100-pin plastic lqfp (14 20) ( pd70f3737, 70f3738 only) gc: 100-pin plastic lqfp (fine pitch) (14 14) f1: 121-pin plastic fbga (8 8)
v850es/jg3-l chapter 2 pin functions r01uh0165ej0700 rev.7.00 page 45 of 1113 sep 22, 2011 2.2 pin states the operation states of pins in the various modes are described below. table 2-2. pin operation states in various modes pin name when power is turned on note 1 during reset (except when power is turned on) halt mode note 2 idle1, idle2, sub-idle mode note 2 stop mode note 2 idle state note 3 bus hold rtc back up mode note 4 p05/drst pulled down pulled down note 5 held held held held held p10/ano0, p11/ano1 hi-z held held hi-z held held p53/ddo undefined hi-z note 7 held held held held held ad0 to ad15 notes 9, 10 a0 to a15 undefined notes 9, 11 a16 to a21 undefined note 9 hi-z hi-z held hi-z wait ? ? ? ? ? clkout operating l l operating operating wr0, wr1 rd astb h note 7 hi-z hldak h h h l hldrq hi-z note 8 hi-z note 8 operating note 9 ? ? ? operating other port pins hi-z hi-z held held held held held undefined note 6 notes 1. duration until 1 ms elapses after the supply volt age reaches the operating s upply voltage range (lower limit) when the power is turned on. 2. operates while an alternate function is operating. 3. in separate bus mode, the state of t he pins in the idle state inserted after the t2 state is shown. in multiplexed bus mode, the stat e of the pins in the idle state inserted after the t3 state is shown (only after a read operation). 4. pd70f3792, 70f3793, 70f 3841, 70f3842 only. 5. pulled down during external reset. during internal re set by the watchdog timer, clock monitor, etc., the state of this pin differs accord ing to the ocdm.ocdm0 bit setting. 6. because the v dd and ev dd voltages are less than the minimum oper ating voltage, t he pin status is undefined. 7. ddo output is specified in the on-chip debug mode. 8. the bus control pins function alternately as port pins, so they are initialized to the input mode (port mode). 9. operates even in the halt mode, during dma operation. 10. in separate bus mode: hi-z in multiplexed bus mode: undefined 11. in separate bus mode remark hi-z: high impedance held: the state during the immediately preceding external bus cycle is held. l: low-level output h: high-level output ? : input without sampling (not acknowledged)
v850es/jg3-l chapter 2 pin functions r01uh0165ej0700 rev.7.00 page 46 of 1113 sep 22, 2011 2.3 pin i/o circuit types, i/o buffer power supplies, and connection of unused pins (1/3) pin no. pin alternate function gf gc f1 i/o circuit type recommended connection of unused pin p02 nmi (/a21) note1 19 17 note2 , 7 note1 j2, g4 note1 p03 intp0/adtrg (/rtc1hz) note1 20 18 g3 p04 intp1 (/rtcdiv/rtcll) note1 21 19 h4 10-d input: independently connect to ev dd or ev ss via a resistor. output: leave open. p05 intp2/drst 22 20 j3 10-n input: independently connect to ev ss via a resistor. fixing to v dd level is prohibited. output: leave open. internally pull-down after reset by reset pin. p06 intp3 23 21 j4 10-d input: independently connect to ev dd or ev ss via a resistor. output: leave open. p10, p11 ano0, ano1 5, 6 3, 4 e3, e4 12-d input: independently connect to av ref1 or av ss via a resistor. output: leave open. p30 txda0/sob4 27 25 l3 10-g p31 rxda0/intp7/sib4 28 26 k3 p32 ascka0/sckb4/tip00 29 27 l4 p33 tip01/top01 30 28 k4 p34 tip10/top10 31 29 k5 p35 tip11/top11 32 30 j5 10-d p36 txda3 note1 33 31 h5 p37 rxda3 note1 34 32 j6 10-g, 10-d note1 p38 txda2/sda00 37 35 h6 p39 rxda2/scl00 38 36 h7 p40 sib0/sda01 24 22 k1 p41 sob0/scl01 25 23 k2 p42 sckb0 26 24 l2 p50 tiq01/kr0/toq01/rtp00 39 37 l7 p51 tiq02/kr1/toq02/rtp01 40 38 k7 p52 tiq03/kr2/toq03 /rtp02/ddi 41 39 j7 p53 sib2/kr3/tiq00/toq00 /rtp03/ddo 42 40 l8 p54 sob2/kr4/rtp04/dck 43 41 k8 p55 sckb2/kr5/rtp05/ dms 44 42 j8 10-d input: independently connect to ev dd or ev ss via a resistor. output: leave open. notes1. pd70f3792, 70f3793, 70f 3841, 70f3842 only. 2. pd70f3737, 70f3738 only. remark gf: 100-pin plastic lqfp (14 20) ( pd70f3737, 70f3738 only) gc: 100-pin plastic lqfp (fine pitch) (14 14) f1: 121-pin plastic fbga (8 8)
v850es/jg3-l chapter 2 pin functions r01uh0165ej0700 rev.7.00 page 47 of 1113 sep 22, 2011 (2/3) pin no. pin alternate function gf gc f1 i/o circuit type recommended connection of unused pin p70 to p711 ani0 to ani11 2, 1, 100 to 91 100 to 89 a3 to a5, b3 to b5, c3 to c5, d3 to d5 11-g input: independently connect to av ref0 or av ss via a resistor. output: leave open. p90 a0/kr6/tdxa1/sda02 45 43 h8 p91 a1/kr7/rxda1/scl02 46 44 l9 p92 a2/tip41/top41 (/txda4) note1 47 45 k9 p93 a3/tip40/top40 (/rxda4) note1 48 46 j9 p94 a4/tip31/top31 (/txda5) note1 49 47 l10 p95 a5/tip30/top30 (/rxda5) note1 50 48 k10 p96 a6 (/txdc0) note1 /tip21/top21 51 49 k11 p97 a7/sib1 (/rxdc0) note1 /tip20/ top20 52 50 j11 10-d p98 a8/sob1 53 51 j10 10-g p99 a9/sckb1 54 52 h11 p910 a10/sib3 55 53 h10 10-d p911 a11/sob3 56 54 h9 10-g p912 a12/sckb3 57 55 g11 p913 a13/intp4 58 56 g10 p914 a14/intp5/tip51/top51 59 57 g9 p915 a15/intp6/tip50/top50 60 58 g8 10-d pcm0 wait 63 61 f11 pcm1 clkout 64 62 f10 pcm2 hldak 65 63 e10 pcm3 hldrq 66 64 e9 pct0, pct1 wr0, wr1 67, 68 65, 66 e8, d10 pct4 rd 69 67 d9 pct6 astb 70 68 d8 pdh0 to pdh4 a16 to a20 89,90, 61,62, 8 87, 88, 59, 60, 6 c6, d6, f9, f8, f4 pdh5 note2 a21 9 7 g4 pdl0 to pdl4 ad0 to ad4 73 to 77 71 to 75 b10, b11, c9 to c11 pdl5 ad5/flmd1 78 76 a10 5 input: independently connect to ev dd or ev ss via a resistor. output: leave open. notes1. pd70f3792, 70f3793, 70f 3841, 70f3842 only. 2. pd70f3737, 70f3738 only. remark gf: 100-pin plastic lqfp (14 20) ( pd70f3737, 70f3738 only) gc: 100-pin plastic lqfp (fine pitch) (14 14) f1: 121-pin plastic fbga (8 8)
v850es/jg3-l chapter 2 pin functions r01uh0165ej0700 rev.7.00 page 48 of 1113 sep 22, 2011 (3/3) pin no. pin alternate function gf gc f1 i/o circuit type recommended connection of unused pin pdl6 to pdl15 ad6 to ad15 79 to 88 77 to 86 a7 to a9, b6 to b9, c7, c8, d7 5 input: independently connect to ev dd or ev ss via a resistor. output: leave open. rv dd note1 ? ? 17 d2 ? directly connect to v dd and always supply power. av ref0 ? 3 1 a1, a2, b1 ? directly connect to v dd and always supply power. av ref1 ? 7 5 b2 ? directly connect to v dd and always supply power. av ss ? 4 2 c1, c2 ? directly connect to v ss and always supply power. ev dd ? 36, 72 34, 70 a11, d11, k6, l11, l6 ? directly connect to v dd and always supply power. ev ss ? 35, 71 33, 69 note2 ? directly connect to v ss and always supply power. flmd0 ? 10 8 f3 ? directly connect to v ss in a mode other than the flash memory programming mode. regc ? 12 10 e1, e2 ? connection of regulator output stabilization capacitance (4.7 f (recommended value)) reset ? 16 14 h3 2 ? v dd ? 11 9 d1, d2 ? ? v ss ? 13 11 g1, g2, j1 ? ? x1 ? 14 12 f1 ? ? x2 ? 15 13 f2 ? ? xt1 ? 17 15 h1 16-c connect to v ss . xt2 ? 18 16 h2 16-c leave open. notes1. pd70f3792, 70f3793, 70f 3841, 70f3842 only. 2. a6, e5 to e7, e11, f5 to f7, g5 to g7, l1, l5 remark gf: 100-pin plastic lqfp (14 20) ( pd70f3737, 70f3738 only) gc: 100-pin plastic lqfp (fine pitch) (14 14) f1: 121-pin plastic fbga (8 8)
v850es/jg3-l chapter 2 pin functions r01uh0165ej0700 rev.7.00 page 49 of 1113 sep 22, 2011 figure 2-1. pin i/o circuits type 2 schmitt-triggered input with hysteresis characteristics type 5 in data output disable p-ch in/out ev dd ev ss n-ch input enable type 11-g type 12-d type 10-d data output disable ev dd ev ss note p-ch in/out in/out n-ch open drain input enable data output disable av ref0 p-ch in/out n-ch p-ch n-ch v ref0 (threshold voltage) comparator input enable + _ av ss av ss data output disable input enable av ref1 p-ch in/out n-ch p-ch n-ch analog output voltage av ss type 10-n data output disable ev dd ev ss p-ch in/out n-ch open drain input enable ocdm0 bit note n-ch type 16-c p-ch feedback cut-off xt1 xt2 type 10-g data output disable ev dd ev ss p-ch in/out n-ch open drain input enable note hysteresis characteristics are not available in port mode.
v850es/jg3-l chapter 2 pin functions r01uh0165ej0700 rev.7.00 page 50 of 1113 sep 22, 2011 2.4 cautions when the power is turned on, the following pins may ou tput an undefined level temporarily even during reset. ? p10/ano0 pin ? p11/ano1 pin ? p53/sib2/kr3/tiq00/toq00/rtp03/ddo pin
v850es/jg3-l chapter 3 cpu function r01uh0165ej0700 rev.7.00 page 51 of 1113 sep 22, 2011 chapter 3 cpu function the cpu of the v850es/jg3-l is based on risc architecture and executes almo st all instructions in one clock cycle by using a 5-stage pipeline. 3.1 features variable length instructions (16 bits/32 bits) minimum instruction execution time: 50 ns (operating on main clock (f xx ) of 20 mhz: v dd = 2.7 to 3.6 v) 200 ns (operating on main clock (f xx ) of 5 mhz: v dd = 2.2 to 3.6 v) 400 ns (operating on main clock (f xx ) of 2.5 mhz: v dd = 2.0 to 3.6 v) note 30.5 s (operating on subclock (f xt ) of 32.768 khz) memory space program space: 64 mb linear data space: 4 gb linear general-purpose registers: 32 bits 32 registers internal 32-bit architecture 5-stage pipeline control multiplication/division instruction saturation operation instruction 32-bit shift instruction: 1 clock load/store instruction with long/short format four types of bit manipulation instructions ? set1 ? clr1 ? not1 ? tst1 note pd70f3792, 70f3793, 70f 3841, 70f3842 only
v850es/jg3-l chapter 3 cpu function r01uh0165ej0700 rev.7.00 page 52 of 1113 sep 22, 2011 3.2 cpu register set the registers of the v850es/jg3-l can be classified into two types: general-purpose program registers and dedicated system registers. all the registers are 32 bits wide. for details, refer to the v850es architecture user?s manual . (1) program register set (2) system register set r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 (zero register) (assembler-reserved register) (stack pointer (sp)) (global pointer (gp)) (text pointer (tp)) (element pointer (ep)) (link pointer (lp)) pc (program counter) psw (program status word) ecr (interrupt source register) fepc fepsw (nmi status saving register) (nmi status saving register) eipc eipsw (interrupt status saving register) (interrupt status saving register) 31 0 31 0 31 0 ctbp (callt base pointer) dbpc dbpsw (exception/debug trap status saving register) (exception/debug trap status saving register) ctpc ctpsw (callt execution status saving register) (callt execution status saving register) general-purpose registers
v850es/jg3-l chapter 3 cpu function r01uh0165ej0700 rev.7.00 page 53 of 1113 sep 22, 2011 3.2.1 program register set the program registers include general-p urpose registers and a program counter. (1) general-purpose registers (r0 to r31) thirty-two general-purpose registers, r0 to r31, are av ailable. any of these regi sters can be used to store a data variable or an address variable. however, r0 and r30 are implicitly used by instructi ons and care must be exerci sed when these registers are used. r0 always holds 0 and is used for an operation that uses 0 or addressing of offset 0. r30 is used by the sld and sst instructions as a bas e pointer when these instructions access the memory. r1, r3 to r5, and r31 are implicitly used by the assembler and c co mpiler. when using these registers, save their contents for protection, and then restor e the contents after using the registers. r2 is sometimes used by the real-time os. if the real-time os does not use r2 , it can be used as a register for variables. table 3-1. program registers name usage operation r0 zero register always holds 0. r1 assembler-reserved register used as work ing register to create 32-bit immediate data r2 register for address/data variable (if real-time os does not use r2) r3 stack pointer used to create a stack frame when a function is called r4 global pointer used to access a global variable in the data area r5 text pointer used as register that indicates th e beginning of a text area (area where program codes are located) r6 to r29 register for address/data variable r30 element pointer used as base pointer to access memory r31 link pointer used when t he compiler calls a function pc program counter holds the instruction address during program execution remark for further details on the r1, r3 to r5, and r31 that are used in the assembler and c compiler, refer to the ca850 (c compiler package) as sembly language user?s manual . (2) program counter (pc) the program counter holds the instru ction address during program execution. the lower 32 bits of this register are valid. bits 31 to 26 are fixed to 0. a carry from bit 25 to 26 is ignored even if it occurs. bit 0 is fixed to 0. this means that ex ecution cannot branch to an odd address. 31 26 25 1 0 pc fixed to 0 instruction address during program execution 0 default value 00000000h
v850es/jg3-l chapter 3 cpu function r01uh0165ej0700 rev.7.00 page 54 of 1113 sep 22, 2011 3.2.2 system register set the system registers control the status of the cpu and hold interrupt information. these registers can be read or written by using system register load/store instru ctions (ldsr and stsr), using the system register numbers listed below. table 3-2. system register numbers operand specification system register number system register name ldsr instruction stsr instruction 0 interrupt status saving register (eipc) note 1 1 interrupt status saving register (eipsw) note 1 2 nmi status saving register (fepc) note 1 3 nmi status saving register (fepsw) note 1 4 interrupt source register (ecr) 5 program status word (psw) 6 to 15 reserved for future function expansion (operation is not guaranteed if these registers are accessed) 16 callt execution status saving register (ctpc) 17 callt execution status saving register (ctpsw) 18 exception/debug trap status saving register (dbpc) note 2 note 2 19 exception/debug trap status saving register (dbpsw) note 2 note 2 20 callt base pointer (ctbp) 21 to 31 reserved for future function expansion (operation is not guaranteed if these registers are accessed) notes 1. because only one set of these registers is availabl e, the contents of these r egisters must be saved by program if multiple interrupts are enabled. 2. these registers can be accessed only during t he interval between the execution of the dbtrap instruction or illegal opcode and dbret instruction execution. caution even if eipc or fepc, or bi t 0 of ctpc is set to 1 by the ldsr instruction, bit 0 is ignored when execution is returned to the main routine by the reti instruction after interrupt servicing (this is because bit 0 of the pc is fixed to 0). set an even value to eipc, fepc, and ctpc (bit 0 = 0). remark : can be accessed : access prohibited
v850es/jg3-l chapter 3 cpu function r01uh0165ej0700 rev.7.00 page 55 of 1113 sep 22, 2011 (1) interrupt status saving registers (eipc and eipsw) eipc and eipsw are used to save the status when an interrupt occurs. if a software exception or a maskable interrupt occurs, t he contents of the program counter (pc) are saved to eipc, and the contents of t he program status word (psw) are saved to eipsw (these contents are saved to the nmi status saving registers (fepc and f epsw) if a non-maskable interrupt occurs). the address of the instruction next to the instruction under execution, except some instructions (see 19.8 periods in which interrupts are not acknowledged by cpu ), is saved to eipc when a software exception or a maskable interrupt occurs. the current contents of the psw are saved to eipsw. because only one set of interrupt status saving registers is available, the contents of these r egisters must be saved by program when multiple interrupts are enabled. bits 31 to 26 of eipc and bits 31 to 8 of eipsw are reserved for future function expansion (these bits are always fixed to 0). the value of eipc is restored to the pc and the val ue of eipsw to the psw by the reti instruction. 31 0 eipc (contents of saved pc) 0 0 default value 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 eipsw (contents of saved psw) 0 0 default value 000000xxh (x: undefined) 87 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
v850es/jg3-l chapter 3 cpu function r01uh0165ej0700 rev.7.00 page 56 of 1113 sep 22, 2011 (2) nmi status saving re gisters (fepc and fepsw) fepc and fepsw are used to save the status when a non-maskable interrupt (nmi) occurs. if an nmi occurs, the contents of t he program counter (pc) are saved to fepc, and those of the program status word (psw) are saved to fepsw. the address of the instruction next to the one of the instruction under execution, except some instructions, is saved to fepc when an nmi occurs. the current contents of t he psw are saved to fepsw. because only one set of nmi status saving registers is available, the contents of these registers must be saved by program when multiple interrupts are enabled (f or multiple interrupt servicing using the nmi pin and the intwdt2 interrupt request signal). bits 31 to 26 of fepc and bits 31 to 8 of fepsw are re served for future function expansion (these bits are always fixed to 0). the value of fepc is restored to the pc and the value of fepsw to the psw by the reti instruction. 31 0 fepc (contents of saved pc) 0 0 default value 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 fepsw (contents of saved psw) 0 0 default value 000000xxh (x: undefined) 87 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (3) interrupt source register (ecr) the interrupt source register (ecr) hol ds the source of an exception or in terrupt if an exception or interrupt occurs. this register holds the exception code of each interrupt source. because this register is a read-only register, data cannot be written to this register using the ldsr instruction. 31 0 ecr fecc eicc default value 00000000h 16 15 bit position bit name meaning 31 to 16 fecc exception code of non-maskable interrupt (nmi) 15 to 0 eicc exception code of exception or maskable interrupt
v850es/jg3-l chapter 3 cpu function r01uh0165ej0700 rev.7.00 page 57 of 1113 sep 22, 2011 (4) program status word (psw) the program status word (psw) is a collection of flags that indicate t he status of the program (result of instruction execution) and the status of the cpu. if the contents of a bit of this regi ster are changed by using the ldsr instruction, the new contents are validated immediately after completion of ldsr instructio n execution. however if the id flag is set to 1, interrupt requests will not be acknowledged while the ldsr instruction is being executed. bits 31 to 8 of this register are reserved for future function expansion (these bits are fixed to 0). (1/2) psw default value 00000020h 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 87 np 6 ep 5 id 4 sat 3 cy 2 ov 1 sz bit position flag name meaning 7 np indicates that a non-maskable interrupt (nmi) is being serviced. this bit is set to 1 when an nmi request is acknowledged, disabling multiple interrupts. 0: nmi is not being serviced. 1: nmi is being serviced. 6 ep indicates that an exception is bei ng processed. this bit is set to 1 when an exception occurs. even if this bit is set, interrupt requests are acknowledged. 0: exception is not being processed. 1: exception is being processed. 5 id indicates whether a maskable interrupt can be acknowledged. 0: interrupt enabled 1: interrupt disabled 4 sat note indicates that the result of a saturation operation has overflowed and is saturated. because this is a cumulative flag, it is set to 1 when the result of a saturation operation instruction is saturated, and is not cleared to 0 even if the subsequent operation result is not saturated. use the ldsr instruction to clear this bit. th is flag is neither set to 1 nor cleared to 0 by execution of an arithmetic operation instruction. 0: not saturated 1: saturated 3 cy indicates whether a carry or a borrow o ccurs as a result of an operation. 0: carry or borrow does not occur. 1: carry or borrow occurs. 2 ov note indicates whether an overflow occurs during operation. 0: overflow does not occur. 1: overflow occurs. 1 s note indicates whether the result of an operation is negative. 0: the result is positive or 0. 1: the result is negative. 0 z indicates whether the result of an operation is 0. 0: the result is not 0. 1: the result is 0. remark also read note on the next page.
v850es/jg3-l chapter 3 cpu function r01uh0165ej0700 rev.7.00 page 58 of 1113 sep 22, 2011 (2/2) note the result of the operation that has performed satura tion processing is determine d by the contents of the ov and s flags. the sat flag is set to 1 only when the ov flag is set to 1 when a saturation operation is performed. flag status status of operation result sat ov s result of operation of saturation processing maximum positive value is exceeded 1 1 0 7fffffffh maximum negative value is exceeded 1 1 1 80000000h positive (maximum value is not exceeded) 0 negative (maximum value is not exceeded) holds value before operation 0 1 operation result itself (5) callt execution status saving registers (ctpc and ctpsw) ctpc and ctpsw are callt execut ion status saving registers. when the callt instruction is executed, the contents of the program counter (pc) are saved to ctpc, and those of the program status wo rd (psw) are saved to ctpsw. the contents saved to ctpc are the address of the inst ruction next to callt. the current contents of t he psw are saved to ctpsw. bits 31 to 26 of ctpc and bits 31 to 8 of ctpsw are reserved for future function expansion (fixed to 0). 31 0 ctpc (saved pc contents) 0 0 default value 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 ctpsw (saved psw contents) 0 0 default value 000000xxh (x: undefined) 87 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
v850es/jg3-l chapter 3 cpu function r01uh0165ej0700 rev.7.00 page 59 of 1113 sep 22, 2011 (6) exception/debug trap status saving registers (dbpc and dbpsw) dbpc and dbpsw are exception/debug trap status registers. if an exception trap or debug trap occurs, the contents of the program counter (pc) are saved to dbpc, and those of the program status word (psw) are saved to dbpsw. the contents to be saved to dbpc are the address of t he instruction next to the one that is being executed when an exception trap or debug trap occurs. the current contents of t he psw are saved to dbpsw. this register can be read or written only during the in terval between the execution of the dbtrap instruction or illegal opcode and the dbret instruction. bits 31 to 26 of dbpc and bits 31 to 8 of dbpsw are reserved for future function expansion (fixed to 0). the value of dbpc is restored to the pc and the value of dbpsw to the psw by the dbret instruction. 31 0 dbpc (saved pc contents) 0 0 default value 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 dbpsw (saved psw contents) 0 0 default value 000000xxh (x: undefined) 87 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (7) callt base pointer (ctbp) the callt base pointer (ctbp) is used to specify a tabl e address or generate a target address (bit 0 is fixed to 0). bits 31 to 26 of this register are reserved for future function expansion (fixed to 0). 31 0 ctbp (base address) 0 0 default value 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 0
v850es/jg3-l chapter 3 cpu function r01uh0165ej0700 rev.7.00 page 60 of 1113 sep 22, 2011 3.3 operation modes the v850es/jg3-l has the following operation modes. ? normal operation mode ? flash memory programming mode ? self programming mode ? on-chip debug mode the operation mode is specified acco rding to the status (input leve l) of the flmd0 and flmd1 pins. to specify the normal operation mode, input a low level to the flmd0 pin during the reset period. a high level is input to the flmd0 pin by the flash memo ry programmer in the flash memory programming mode if a flash programmer is connected. in the self-programming mode, input a high level to this pin from an external circuit. fix the specification of t hese pins in the application system and do not change the setting of these pins during operation. flmd0 flmd1 operation mode l normal operation mode h l flash memory programming mode h h setting prohibited remark h: high level l: low level : don?t care (1) normal operation mode after the system has been released from the reset state, the pins related to the bus interface are set to the port mode, execution branches to the reset entry address of the internal rom, and instruction processing is started. (2) flash memory programming mode when this mode is specified, the internal flash me mory can be programmed by using a flash programmer. (3) self programming mode data can be erased and written from/to the flash memory by using a user application program. for details, see chapter 30 flash memory . (4) on-chip debug mode the v850es/jg3-l is provided with an on-chip debug func tion that employs the jtag (joint test action group) communication specifications. for details, see chapter 31 on-chip debug function .
v850es/jg3-l chapter 3 cpu function r01uh0165ej0700 rev.7.00 page 61 of 1113 sep 22, 2011 3.4 address space 3.4.1 cpu address space for instruction addressing, up to a combined total of 16 mb of external memory area and internal rom area, plus an internal ram area, are supported in a linear address space (program space) of up to 64 mb. for operand addressing (data access), up to 4 gb of a linear address spac e (data space) is supported. the 4 gb address space, however, is viewed as 64 images of a 64 mb physical addr ess space. this means that the same 64 mb physical address space is accessed regardless of the value of bits 31 to 26. figure 3-1. address space image program space internal ram area access-prohibited area external memory area, etc internal rom area (external memory) data space image 63 note image 0 on-chip peripheral i/o area internal ram area access-prohibited area external memory area, etc internal rom area (external memory) 16 mb 4 gb 16 mb ? ? ? 64 mb access-prohibited area image 62 note image 2 note image 1 note note image 0 appears repeatedly for images 1 to 63.
v850es/jg3-l chapter 3 cpu function r01uh0165ej0700 rev.7.00 page 62 of 1113 sep 22, 2011 3.4.2 memory map the areas shown below are re served in the v850es/jg3-l. figure 3-2. data memory map (physical addresses) ( pd70f3737, 70f3738, 70f3793, 70f3793) image 0 (physical memory address) image 1 image 2 image 3 image 60 image 61 image 62 image 63 (64 kb) use prohibited external memory area note 1 (14 mb) internal rom area note 2 (1 mb) external memory area note 1 (1 mb) internal ram area (60 kb) on-chip peripheral i/o area (4 kb) 10000000h 0fffffffh 04000000h 03ffffffh 00000000h 03ffffffh 03fff000h 03ffefffh 03ff0000h 001fffffh 00100000h 000fffffh 00000000h 03ffffffh 03ff0000h 01000000h 00ffffffh 00200000h 001fffffh 03feffffh (2 mb) 00000000h 08000000h 07ffffffh 0c000000h 0bffffffh f0000000h efffffffh f4000000h f3ffffffh f8000000h f7ffffffh fc000000h fbffffffh ffffffffh notes 1. the v850es/jg3-l has 22 address pins, so the exte rnal memory area appears as a repeated 4 mb image. 2. fetch and read accesses to addresse s 00000000h to 000fffffh are m ade to the internal rom area. however, data write accesses to these addresses are made to the external memory area.
v850es/jg3-l chapter 3 cpu function r01uh0165ej0700 rev.7.00 page 63 of 1113 sep 22, 2011 figure 3-3. data memory map (physical addresses) ( pd70f3841, 70f3842) image 0 (physical memory address) image 1 image 2 image 3 image 60 image 61 image 62 image 63 (64 kb) use prohibited external memory area note 1 (12 mb) internal rom area note 2 (1 mb) external memory area note 1 (1 mb) internal ram area (60 kb) on-chip peripheral i/o area (4 kb) 10000000h 0fffffffh 04000000h 03ffffffh 00000000h 03ffffffh 03fff000h 03ffefffh 03ff0000h 001fffffh 00100000h 000fffffh 00000000h use prohibited expanded internal ram area(24 kb) 003fffffh 003fa000h 003f9fffh 00200000h 03ffffffh 03ff0000h 01000000h 00ffffffh 00200000h 001fffffh 00400000h 003fffffh 03feffffh (2 mb) (2 mb) 00000000h 08000000h 07ffffffh 0c000000h 0bffffffh f0000000h efffffffh f4000000h f3ffffffh f8000000h f7ffffffh fc000000h fbffffffh ffffffffh notes 1. the v850es/jg3-l has 22 address pins, so the exte rnal memory area appears as a repeated 4 mb image. 2. fetch and read accesses to addresses 00000000h to 000fffffh are made to the internal rom area. however, data write accesses to these addresses are made to the external memory area.
v850es/jg3-l chapter 3 cpu function r01uh0165ej0700 rev.7.00 page 64 of 1113 sep 22, 2011 figure 3-4. program memory map ( pd70f3737, 70f3738, 70f3793, 70f3793) internal ram area (60 kb) use prohibited (program fetch prohibited area) use prohibited (program fetch prohibited area) external memory area note (14 mb) external memory area note (1 mb) internal rom area (1 mb) 03ffffffh 03fff000h 03ffefffh 01000000h 00ffffffh 03ff0000h 03feffffh 00200000h 001fffffh 00100000h 000fffffh 00000000h note the v850es/jg3-l has 22 address pins, so the ex ternal memory area appears as a repeated 4 mb image.
v850es/jg3-l chapter 3 cpu function r01uh0165ej0700 rev.7.00 page 65 of 1113 sep 22, 2011 figure 3-5. program memory map ( pd70f3841, 70f3842) internal ram area (60 kb) use prohibited (program fetch prohibited area) use prohibited (program fetch prohibited area) use prohibited (program fetch prohibited area) external memory area note (12 mb) external memory area note (1 mb) internal rom area (1 mb) 03ffffffh 03fff000h 03ffefffh 01000000h 00ffffffh 03ff0000h 03feffffh 00200000h 001fffffh 00400000h 003fffffh 00100000h 000fffffh 00000000h note the v850es/jg3-l has 22 address pins, so the ex ternal memory area appears as a repeated 4 mb image.
v850es/jg3-l chapter 3 cpu function r01uh0165ej0700 rev.7.00 page 66 of 1113 sep 22, 2011 3.4.3 areas (1) internal rom area up to 1 mb is reserved as an internal rom area. (a) internal rom (128 kb) 128 kb are allocated to addresses 00000000h to 0001ffffh in the pd70f3737. accessing addresses 00020000h to 000fffffh is prohibited. figure 3-6. internal rom area (128 kb) access-prohibited area internal rom (128 kb) 000fffffh 00020000h 0001ffffh 00000000h (b) internal rom (256 kb) 256 kb are allocated to addresses 00000000h to 0003ffffh in the pd70f3738. accessing addresses 00040000h to 000fffffh is prohibited. figure 3-7. internal rom area (256 kb) access-prohibited area internal rom (256 kb) 00040000h 0003ffffh 00000000h 000fffffh
v850es/jg3-l chapter 3 cpu function r01uh0165ej0700 rev.7.00 page 67 of 1113 sep 22, 2011 (c) internal rom (384 kb) 384 kb are allocated to addresses 00000000h to 0005ffffh in the pd70f3792. accessing addresses 00060000h to 000fffffh is prohibited. figure 3-8. internal rom area (384 kb) access-prohibited area internal rom (384 kb) 00060000h 0005ffffh 00000000h 000fffffh (d) internal rom (512 kb) 512 kb are allocated to addresses 00000000h to 0007ffffh in the pd70f3793. accessing addresses 00080000h to 000fffffh is prohibited. figure 3-9. internal rom area (512 kb) access-prohibited area internal rom (512 kb) 00080000h 0007ffffh 00000000h 000fffffh
v850es/jg3-l chapter 3 cpu function r01uh0165ej0700 rev.7.00 page 68 of 1113 sep 22, 2011 (e) internal rom (768 kb) 768 kb are allocated to addresses 00000000h to 000bffffh in the pd70f3841. accessing addresses 000c0000h to 000fffffh is prohibited. figure 3-10. internal rom area (768 kb) access-prohibited area internal rom (768 kb) 000c0000h 000bffffh 00000000h 000fffffh (f) internal rom (1 mb) 1 mb are allocated to addres ses 00000000h to 000fffffh in the pd70f3842. figure 3-11. internal rom area (1 mb) internal rom (1 mb) 00000000h 000fffffh
v850es/jg3-l chapter 3 cpu function r01uh0165ej0700 rev.7.00 page 69 of 1113 sep 22, 2011 (2) internal ram area up to 60 kb allocated to physical addresses 03ff000 0h to 03ffefffh are reserved as the internal ram area. pd70f3841, 70f3842 include a expanded internal ram in addition to the internal ram. the ram capacity of v850es/jg3-l is as follows. table 3-3 ram area product name internal ram expanded internal ram total ram pd70f3737 8 kb - 8 kb pd70f3738 16 kb - 16 kb pd70f3792 32 kb - 32 kb pd70f3793 40 kb - 40 kb pd70f3841 56 kb 24 kb 80 kb pd70f3842 56 kb 24 kb 80 kb (a) internal ram (8 kb) 8 kb are allocated to addresses 03ffd000h to 03ffefffh of the pd70f3737. accessing addresses 03ff0000h to 03ffcfffh is prohibited. figure 3-12. internal ram area (8 kb) access-prohibited area internal ram (8 kb) 03ffd000h 03ffcfffh 03ff0000h 03ffefffh ffffd000h ffffcfffh ffff0000h ffffefffh physical address space logical address space
v850es/jg3-l chapter 3 cpu function r01uh0165ej0700 rev.7.00 page 70 of 1113 sep 22, 2011 (b) internal ram (16 kb) 16 kb are allocated to addresses 03ffb000h to 03ffefffh of the pd70f3738. accessing addresses 03ff0000h to 03ffafffh is prohibited. figure 3-13. internal ram area (16 kb) access-prohibited area internal ram (16 kb) 03ffb000h 03ffafffh 03ff0000h 03ffefffh ffffb000h ffffafffh ffff0000h ffffefffh physical address space logical address space (c) internal ram (32 kb) 32 kb are allocated to addresses 03ff7000h to 03ffefffh of the pd70f3792. accessing addresses 03ff0000h to 03ff6fffh is prohibited. figure 3-14. internal ram area (32 kb) access-prohibited area internal ram (32 kb) physical address space logical address space 03ff7000h 03ff6fffh 03ff0000h 03ffefffh ffff7000h ffff6fffh ffff0000h ffffefffh
v850es/jg3-l chapter 3 cpu function r01uh0165ej0700 rev.7.00 page 71 of 1113 sep 22, 2011 (d) internal ram (40 kb) 40 kb are allocated to addresses 03ff5000h to 03ffefffh of the pd70f3793. accessing addresses 03ff0000h to 03ff4fffh is prohibited. figure 3-15. internal ram area (40 kb) access-prohibited area internal ram (40 kb) physical address space logical address space ffff5000h ffff4fffh ffff0000h ffffefffh 03ff5000h 03ff4fffh 03ff0000h 03ffefffh (e) internal ram (56 kb) 56 kb are allocated to addresses 03ff1000h to 03ffefffh of the pd70f3841, 70f3842. accessing addresses 03ff0000h to 03ff0fffh is prohibited. figure 3-16. internal ram area (56 kb) access-prohibited area internal ram (56 kb) physical address space logical address space ffff1000h ffff0fffh ffff0000h ffffefffh 03ff1000h 03ff0fffh 03ff0000h 03ffefffh
v850es/jg3-l chapter 3 cpu function r01uh0165ej0700 rev.7.00 page 72 of 1113 sep 22, 2011 (3) expanded internal ram (24 kb) the expanded internal ram of 24 kb is alloca ted to addresses 003fa000h to 003fffffh of the pd70f3841, 70f3842. the expanded internal ram area is accessed via the external bus interface. before accessing the expanded internal ram area, be sure to set the registers related to the external bus interface (initialization of the expanded internal ram). figure 3-17. expanded internal ram (24 kb) access-prohibited area access-prohibited area expaned internal ram (24 kb) physical address space 003fa000h 003f9fffh 003fffffh the initial settings for the expanded internal ram are shown below. cautions 1. if the expanded internal ram is u sed with any but the foll owing initial settings, operation is not guaranteed. 2. when using the external memory and expanded internal ram simultaneously, set the external bus interface and expande d internal ram at the same time. ? bsc register setting bits 2 must be set to 1. ? dwc0 register setting bits 6 to 4 must be set to 001. ? awc register setting bits 3 to 2 must be set to 00. ? bcc register setting bits 3 must be set to 0.
v850es/jg3-l chapter 3 cpu function r01uh0165ej0700 rev.7.00 page 73 of 1113 sep 22, 2011 (4) on-chip peripheral i/o area 4 kb allocated to physical addresse s 03fff000h to 03ffffffh are reserved as the on-chip peripheral i/o area. figure 3-18. on-chip peripheral i/o area on-chip peripheral i/o area (4 kb) 03ffffffh 03fff000h ffffffffh fffff000h physical address space logical address space peripheral i/o registers that have fu nctions to specify the operation mode for and monitor the status of the on-chip peripheral i/o are mapped to t he on-chip peripheral i/o area. pr ogram cannot be fetched from this area. cautions 1. when a peripheral i/o register is accessed in word unit s, a word area is accessed twice in halfword units in the order of lower area then higher area, with th e lower 2 bits of the address ignored. 2. if a peripheral i/o register that can be accessed in byte units is accessed in halfword units, the lower 8 bits are valid. the higher 8 bits are undefined when the register is read and are invalid when the register is written. 3. addresses not defined as registers are re served for future expansion. the operation is undefined and not guaranteed when these addresses are accessed. 4. the internal rom/ram ar ea and on-chip peripheral i/o ar ea are assigned to successive addresses. when accessing the intern al rom/ram area by incr ementing or decrementing addresses using a pointer operation for examp le, be careful not to access the on-chip peripheral i/o area by mista kenly extending over the internal rom/ram area boundary. (5) external memory area 15 mb (00100000h to 00ffffffh)( pd70f3737, 70f3738, 70f3792, 70f3793) or 13 mb (00100000h to 001fffffh, 00400000h to 00ffffffh)( pd70f3841, 70f3842) are allocated as the external memory area. for details, see chapter 5 bus control function . caution the v850es/jg3-l has 22 address pins (a0 to a21), so the external memory area appears as a repeated 4 mb image.
v850es/jg3-l chapter 3 cpu function r01uh0165ej0700 rev.7.00 page 74 of 1113 sep 22, 2011 3.4.4 wraparound of data space the result of an operand address calculation oper ation that exceeds 32 bits is ignored. therefore, the highest address of the data space, ffffffffh, and the lowest address, 00000000h, are contiguous, and wraparound occurs at the boundary of these addresses. figure 3-19. wraparound of data space data space data space (+) direction ( ? ) direction 00000001h 00000000h ffffffffh fffffffeh 3.4.5 recommended use of address space the architecture of the v 850es/jg3-l requires that a r egister that serves as a pointer be secured for address generation when operand data in the data space is accessed. the address stored in this pointer 32 kb can be directly accessed by an instruction for operand data. be cause the number of general-p urpose registers that can be used as a pointer is limited, however, by keeping the performance from dropping during address calculation when a pointer value is changed, as many general-purpose regi sters as possible can be secured for variables, and the program size can be reduced. (1) program space of the 32 bits of the pc (program count er), the higher 6 bits are fixed to 0, and only the lower 26 bits are valid. regarding the program space, therefore, a 64 mb s pace of contiguous addresses starting from 00000000h unconditionally corresponds to the memory map. to use the internal ram area as the prog ram space, access the following addresses. caution if a branch instruction is at the upper limit of the internal ram area, a prefetch operation (invalid fetch) straddling the on-chip peripheral i/o area does not occur. product name ram size access address pd70f3737 8 kb 03ffd000h to 03ffefffh pd70f3738 16 kb 03ffb000h to 03ffefffh pd70f3792 32 kb 03ff7000h to 03ffefffh pd70f3793 40 kb 03ff5000h to 03ffefffh pd70f3841 56 kb 03ff1000h to 03ffefffh pd70f3842 56 kb 03ff1000h to 03ffefffh
v850es/jg3-l chapter 3 cpu function r01uh0165ej0700 rev.7.00 page 75 of 1113 sep 22, 2011 (2) data space with the v850es/jg3-l, it seems that there are sixty-four 64 mb (26-bi t address) physical address spaces on the 4 gb (32-bit address) cpu address s pace. therefore, the most signific ant bit (bit 25) of a 26-bit address of these 64 mb spaces is sign-extended to 32 bits and allocated as an address. figure 3-20. sign exte nsion in data space image 0 image 1 image 2 image 3 image 60 image 61 image 62 image 63 image 0 31 0 0 0 26 25 0 0 0 0 31 0 26 25 64 mb 64 mb 4 gb 64 mb 64 mb 64 mb 64 mb 64 mb 64 mb 64 mb a 26-bit address (64 mb) can be specified. a 32-bit address (4 gb) can be specified. an image of 64 mb appears repeatedly in the 4 gb space. 0000000h 3ffffffh f0000000h efffffffh f4000000h f3ffffffh f8000000h f7ffffffh fc000000h fbffffffh ffffffffh 10000000h 0fffffffh 04000000h 03ffffffh 08000000h 07ffffffh 0c000000h 0bffffffh 00000000h
v850es/jg3-l chapter 3 cpu function r01uh0165ej0700 rev.7.00 page 76 of 1113 sep 22, 2011 (a) application example of wraparound if r = r0 (zero register) is specified for the ld/st disp16 [r] instruction, a range of addresses 00000000h 32 kb can be addressed by sign-extended disp16. all the resources, including the internal hardware, can be addressed by one pointer. the zero register (r0) is a register fixed to 0 by har dware, and practically eliminates the need for registers dedicated to pointers. figure 3-21. example of data space usage in pd70f3738 internal rom area on-chip peripheral i/o area internal ram area 32 kb 4 kb 16 kb access-prohibited area 12 kb (r = ) 0003ffffh 00007fffh 00000000h fffff000h ffffefffh ffffb000h ffffafffh ffff8000h
v850es/jg3-l chapter 3 cpu function r01uh0165ej0700 rev.7.00 page 77 of 1113 sep 22, 2011 figure 3-22. recommended memory map ( pd70f3738) data space program space on-chip peripheral i/o on-chip peripheral i/o internal ram internal ram internal rom external memory note access-prohibited external memory note access-prohibited internal ram program space 64 mb internal rom internal rom ffffffffh fffff000h ffffefffh ffff0000h fffeffffh 04000000h 03ffffffh 03fff000h 03ffefffh 03ffb000h 03ffafffh 03ff0000h 03feffffh 01000000h 00ffffffh 00040000h 0003ffffh 00100000h 000fffffh 00000000h ffffffffh fffff000h ffffefffh ffffb000h ffffafffh ffff0000h fffeffffh 00100000h 000fffffh 00000000h access-prohibited note the v850es/jg3-l has 22 address pins, so the ex ternal memory area appears as a repeated 4 mb image. remark indicates the recommended area.
v850es/jg3-l chapter 3 cpu function r01uh0165ej0700 rev.7.00 page 78 of 1113 sep 22, 2011 3.4.6 peripheral i/o registers (1/11) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff004h port dl register pdl 0000h note fffff004h port dl register l pdll 00h note fffff005h port dl register h pdlh 00h note fffff006h port dh register pdh 00h note fffff00ah port ct register pct 00h note fffff00ch port cm register pcm 00h note fffff024h port dl mode register pmdl ffffh fffff024h port dl mode register l pmdll ffh fffff025h port dl mode register h pmdlh ffh fffff026h port dh mode register pmdh ffh fffff02ah port ct mode register pmct ffh fffff02ch port cm mode register pmcm ffh fffff044h port dl mode control register pmcdl 0000h fffff044h port dl mode control register l pmcdll 00h fffff045h port dl mode control register h pmcdlh 00h fffff046h port dh mode control register pmcdh 00h fffff04ah port ct mode control register pmcct 00h fffff04ch port cm mode control register pmccm 00h fffff066h bus size configuration register bsc 5555h fffff06eh system wait control register vswc 77h fffff080h dma source address register 0l dsa0l undefined fffff082h dma source address register 0h dsa0h undefined fffff084h dma destination address register 0l dda0l undefined fffff086h dma destination address register 0h dda0h undefined fffff088h dma source address register 1l dsa1l undefined fffff08ah dma source address register 1h dsa1h undefined fffff08ch dma destination address register 1l dda1l undefined fffff08eh dma destination address register 1h dda1h undefined fffff090h dma source address register 2l dsa2l undefined fffff092h dma source address register 2h dsa2h undefined fffff094h dma destination address register 2l dda2l undefined fffff096h dma destination address register 2h dda2h undefined fffff098h dma source address register 3l dsa3l undefined fffff09ah dma source address register 3h dsa3h undefined fffff09ch dma destination address register 3l dda3l undefined fffff09eh dma destination address register 3h dda3h undefined fffff0c0h dma transfer count register 0 dbc0 undefined fffff0c2h dma transfer count register 1 dbc1 undefined fffff0c4h dma transfer count register 2 dbc2 undefined fffff0c6h dma transfer count register 3 dbc3 undefined fffff0d0h dma addressing control register 0 dadc0 r/w 0000h note the output latch is 00h or 0000h. when these regist ers are in the input mode, the pin statuses are read.
v850es/jg3-l chapter 3 cpu function r01uh0165ej0700 rev.7.00 page 79 of 1113 sep 22, 2011 (2/11) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff0d2h dma addressing control register 1 dadc1 0000h fffff0d4h dma addressing control register 2 dadc2 0000h fffff0d6h dma addressing control register 3 dadc3 0000h fffff0e0h dma channel control register 0 dchc0 00h fffff0e2h dma channel control register 1 dchc1 00h fffff0e4h dma channel control register 2 dchc2 00h fffff0e6h dma channel control register 3 dchc3 00h fffff100h interrupt mask register 0 imr0 ffffh fffff100h interrupt mask register 0l imr0l ffh fffff101h interrupt mask register 0h imr0h ffh fffff102h interrupt mask register 1 imr1 ffffh fffff102h interrupt mask register 1l imr1l ffh fffff103h interrupt mask register 1h imr1h ffh fffff104h interrupt mask register 2 imr2 ffffh fffff104h interrupt mask register 2l imr2l ffh fffff105h interrupt mask register 2h imr2h ffh fffff106h interrupt mask register 3 imr3 ffffh fffff106h interrupt mask register 3l imr3l ffh fffff107h interrupt mask register 3h imr3h ffh fffff110h interrupt control register (intlvi) lviic 47h fffff112h interrupt control register (intp0) pic0 47h fffff114h interrupt control register (intp1) pic1 47h fffff116h interrupt control register (intp2) pic2 47h fffff118h interrupt control register (intp3) pic3 47h fffff11ah interrupt control register (intp4) pic4 47h fffff11ch interrupt control register (intp5) pic5 47h fffff11eh interrupt control register (intp6) pic6 47h fffff120h interrupt control register (intp7) pic7 47h fffff122h interrupt control register (inttq0ov) tq0ovic 47h fffff124h interrupt control register (inttq0cc0) tq0ccic0 47h fffff126h interrupt control register (inttq0cc1) tq0ccic1 47h fffff128h interrupt control register (inttq0cc2) tq0ccic2 47h fffff12ah interrupt control register (inttq0cc3) tq0ccic3 47h fffff12ch interrupt control register (inttp0ov) tp0ovic 47h fffff12eh interrupt control register (inttp0cc0) tp0ccic0 47h fffff130h interrupt control regi ster (inttp0cc1) tp0ccic1 47h fffff132h interrupt control register (inttp1ov) tp1ovic 47h fffff134h interrupt control regi ster (inttp1cc0) tp1ccic0 47h fffff136h interrupt control regi ster (inttp1cc1) tp1ccic1 47h fffff138h interrupt control register (inttp2ov) tp2ovic 47h fffff13ah interrupt control register (inttp2cc0) tp2ccic0 47h fffff13ch interrupt control register (inttp2cc1) tp2ccic1 47h fffff13eh interrupt control register (inttp3ov) tp3ovic r/w 47h
v850es/jg3-l chapter 3 cpu function r01uh0165ej0700 rev.7.00 page 80 of 1113 sep 22, 2011 (3/11) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff140h interrupt control regi ster (inttp3cc0) tp3ccic0 47h fffff142h interrupt control regi ster (inttp3cc1) tp3ccic1 47h fffff144h interrupt control register (inttp4ov) tp4ovic 47h fffff146h interrupt control regi ster (inttp4cc0) tp4ccic0 47h fffff148h interrupt control regi ster (inttp4cc1) tp4ccic1 47h fffff14ah interrupt control register (inttp5ov) tp5ovic 47h fffff14ch interrupt control register (inttp5cc0) tp5ccic0 47h fffff14eh interrupt control register (inttp5cc1) tp5ccic1 47h fffff150h interrupt control regi ster (inttm0eq0) tm0eqic0 47h fffff1 52 h interrupt control register (intcb0r/intiic1) cb0ric/iicic1 47h fffff1 54 h interrupt control register (intcb0t) cb0tic 47h fffff156h interrupt control register (intcb1r) cb1ric 47h fffff158h interrupt control register (intcb1t) cb1tic 47h fffff15ah interrupt control register (intcb2r) cb2ric 47h fffff15ch interrupt control register (intcb2t) cb2tic 47h fffff15eh interrupt control register (intcb3r) cb3ric 47h fffff160h interrupt control register (intcb3t) cb3tic 47h fffff162h interrupt control register (intua0r/intcb4r) ua0ric/cb4ric 47h fffff164h interrupt control register (intua0t/intcb4t) ua0tic/cb4tic 47h fffff166h interrupt control register (intua1r/intiic2) ua1ric/iicic2 47h fffff168h interrupt control register (intua1t) ua1tic 47h fffff16ah interrupt control register (intua2r/intiic0) ua2ric/iicic0 47h fffff16ch interrupt control register (intua2t) ua2tic 47h fffff16eh interrupt control register (intad) adic 47h fffff170h interrupt control register (intdma0) dmaic0 47h fffff172h interrupt control register (intdma1) dmaic1 47h fffff174h interrupt control register (intdma2) dmaic2 47h fffff176h interrupt control register (intdma3) dmaic3 47h fffff178h interrupt control register (intkr) kric 47h fffff17ah interrupt control register (intwti/intrtc2) wtiic (/rtc2ic) note1 47h fffff17ch interrupt control register (intwt/intrtc0) wtic (/rtc0ic) note1 47h fffff17eh interrupt control register (intrtc1) rtc1c note1 47h fffff180h interrupt control register (intua3r) ua3ric note1 47h fffff182h interrupt control register (intua3t) ua3tic note1 47h fffff184h interrupt control register (intua4r) ua4ric note1 47h fffff186h interrupt control register (intua4t) ua4tic note1 47h fffff188h interrupt control register (intuc0r) uc0ric note1 47h fffff18ah interrupt control register (intuc0t) uc0tic note1 r/w 47h fffff1fah in-service priority register ispr r 00h fffff1fch command register prcmd w undefined fffff1feh power save control register psc note2 r/w 00h notes1. pd70f3792, 70f3793, 70f3841, 70f3842 only 2. this is a special register.
v850es/jg3-l chapter 3 cpu function r01uh0165ej0700 rev.7.00 page 81 of 1113 sep 22, 2011 (4/11) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff200h a/d converter mode register 0 ada0m0 00h fffff201h a/d converter mode register 1 ada0m1 00h fffff202h a/d converter channel specification register ada0s 00h fffff203h a/d converter mode register 2 ada0m2 00h fffff204h power-fail compare mode register ada0pfm 00h fffff205h power-fail compare threshold value register ada0pft r/w 00h fffff210h a/d conversion result register 0 ada0cr0 undefined fffff211h a/d conversion result register 0h ada0cr0h undefined fffff212h a/d conversion result register 1 ada0cr1 undefined fffff213h a/d conversion result register 1h ada0cr1h undefined fffff214h a/d conversion result register 2 ada0cr2 undefined fffff215h a/d conversion result register 2h ada0cr2h undefined fffff216h a/d conversion result register 3 ada0cr3 undefined fffff217h a/d conversion result register 3h ada0cr3h undefined fffff218h a/d conversion result register 4 ada0cr4 undefined fffff219h a/d conversion result register 4h ada0cr4h undefined fffff21ah a/d conversion result register 5 ada0cr5 undefined fffff21bh a/d conversion result register 5h ada0cr5h undefined fffff21ch a/d conversion result register 6 ada0cr6 undefined fffff21dh a/d conversion result register 6h ada0cr6h undefined fffff21eh a/d conversion result register 7 ada0cr7 undefined fffff21fh a/d conversion result register 7h ada0cr7h undefined fffff220h a/d conversion result register 8 ada0cr8 undefined fffff221h a/d conversion result register 8h ada0cr8h undefined fffff222h a/d conversion result register 9 ada0cr9 undefined fffff223h a/d conversion result register 9h ada0cr9h undefined fffff224h a/d conversion result register 10 ada0cr10 undefined fffff225h a/d conversion result register 10h ada0cr10h undefined fffff226h a/d conversion result register 11 ada0cr11 undefined fffff227h a/d conversion result register 11h ada0cr11h r undefined fffff280h d/a conversion value setting register 0 da0cs0 00h fffff281h d/a conversion value setting register 1 da0cs1 00h fffff282h d/a converter mode register da0m 00h fffff300h key return mode register krm 00h fffff308h selector operation control register 0 selcnt0 00h fffff310h crc input register crcin 00h fffff312h crc data register crcd 0000h fffff318h noise elimination control register nfc 00h fffff320h prescaler mode register 1 prsm1 00h fffff321h prescaler compare register 1 prscm1 00h fffff324h prescaler mode register 2 prsm2 00h fffff325h prescaler compare register 2 prscm2 00h fffff328h prescaler mode register 3 prsm3 00h fffff329h prescaler compare register 3 prscm3 r/w 00h
v850es/jg3-l chapter 3 cpu function r01uh0165ej0700 rev.7.00 page 82 of 1113 sep 22, 2011 (5/11) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff331h regulator protection register regpr 00h fffff332h regulator output voltage level control register regovl0 00h fffff340h iic division clock select register ocks0 00h fffff344h iic division clock select register ocks1 00h fffff380h clock through select register ckthsel note1 00h fffff400h port 0 register p0 00h note2 fffff402h port 1 register p1 00h note2 fffff406h port 3 register p3 0000h note2 fffff406h port 3 register l p3l 00h note2 fffff407h port 3 register h p3h 00h note2 fffff408h port 4 register p4 00h note2 fffff40ah port 5 register p5 00h note2 fffff40eh port 7 register l p7l 00h note2 fffff40fh port 7 register h p7h 00h note2 fffff412h port 9 register p9 0000h note2 fffff412h port 9 register l p9l 00h note2 fffff413h port 9 register h p9h 00h note2 fffff420h port 0 mode register pm0 ffh fffff422h port 1 mode register pm1 ffh fffff426h port 3 mode register pm3 ffffh fffff426h port 3 mode register l pm3l ffh fffff427h port 3 mode register h pm3h ffh fffff428h port 4 mode register pm4 ffh fffff42ah port 5 mode register pm5 ffh fffff42eh port 7 mode register l pm7l ffh fffff42fh port 7 mode register h pm7h ffh fffff432h port 9 mode register pm9 ffffh fffff432h port 9 mode register l pm9l ffh fffff433h port 9 mode register h pm9h ffh fffff440h port 0 mode control register pmc0 00h fffff446h port 3 mode control register pmc3 0000h fffff446h port 3 mode control register l pmc3l 00h fffff447h port 3 mode control register h pmc3h 00h fffff448h port 4 mode control register pmc4 00h fffff44ah port 5 mode control register pmc5 00h fffff452h port 9 mode control register pmc9 0000h fffff452h port 9 mode control register l pmc9l 00h fffff453h port 9 mode control register h pmc9h 00h fffff460h port 0 function control register pfc0 00h fffff466h port 3 function control register pfc3 0000h fffff466h port 3 function control register l pfc3l 00h fffff467h port 3 function control register h pfc3h r/w 00h notes1. pd70f3792, 70f3793, 70f3841, 70f3842 only 2. the output latch is 00h or 0000h. when these registers are input, the pin statuses are read.
v850es/jg3-l chapter 3 cpu function r01uh0165ej0700 rev.7.00 page 83 of 1113 sep 22, 2011 (6/11) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff468h port 4 function control register pfc4 00h fffff46ah port 5 function control register pfc5 00h fffff472h port 9 function control register pfc9 0000h fffff472h port 9 function control register l pfc9l 00h fffff473h port 9 function control register h pfc9h 00h fffff484h data wait control register 0 dwc0 7777h fffff488h address wait control register awc ffffh fffff48ah bus cycle control register bcc aaaah fffff540h tmq0 control register 0 tq0ctl0 00h fffff541h tmq0 control register 1 tq0ctl1 00h fffff542h tmq0 i/o control register 0 tq0ioc0 00h fffff543h tmq0 i/o control register 1 tq0ioc1 00h fffff544h tmq0 i/o control register 2 tq0ioc2 00h fffff545h tmq0 option register 0 tq0opt0 00h fffff546h tmq0 capture/compare register 0 tq0ccr0 0000h fffff548h tmq0 capture/compare register 1 tq0ccr1 0000h fffff54ah tmq0 capture/compare register 2 tq0ccr2 0000h fffff54ch tmq0 capture/compare register 3 tq0ccr3 r/w 0000h fffff54eh tmq0 counter read buffer register tq0cnt r 0000h fffff590h tmp0 control register 0 tp0ctl0 00h fffff591h tmp0 control register 1 tp0ctl1 00h fffff592h tmp0 i/o control register 0 tp0ioc0 00h fffff593h tmp0 i/o control register 1 tp0ioc1 00h fffff594h tmp0 i/o control register 2 tp0ioc2 00h fffff595h tmp0 option register 0 tp0opt0 00h fffff596h tmp0 capture/compare register 0 tp0ccr0 0000h fffff598h tmp0 capture/compare register 1 tp0ccr1 r/w 0000h fffff59ah tmp0 counter read buffer register tp0cnt r 0000h fffff5a0h tmp1 control register 0 tp1ctl0 00h fffff5a1h tmp1 control register 1 tp1ctl1 00h fffff5a2h tmp1 i/o control register 0 tp1ioc0 00h fffff5a3h tmp1 i/o control register 1 tp1ioc1 00h fffff5a4h tmp1 i/o control register 2 tp1ioc2 00h fffff5a5h tmp1 option register 0 tp1opt0 00h fffff5a6h tmp1 capture/compare register 0 tp1ccr0 0000h fffff5a8h tmp1 capture/compare register 1 tp1ccr1 r/w 0000h fffff5aah tmp1 counter read buffer register tp1cnt r 0000h fffff5b0h tmp2 control register 0 tp2ctl0 00h fffff5b1h tmp2 control register 1 tp2ctl1 00h fffff5b2h tmp2 i/o control register 0 tp2ioc0 00h fffff5b3h tmp2 i/o control register 1 tp2ioc1 00h fffff5b4h tmp2 i/o control register 2 tp2ioc2 00h fffff5b5h tmp2 option register 0 tp2opt0 00h fffff5b6h tmp2 capture/compare register 0 tp2ccr0 r/w 0000h
v850es/jg3-l chapter 3 cpu function r01uh0165ej0700 rev.7.00 page 84 of 1113 sep 22, 2011 (7/11) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff5b8h tmp2 capture/compare register 1 tp2ccr1 r/w 0000h fffff5bah tmp2 counter read buffer register tp2cnt r 0000h fffff5c0h tmp3 control register 0 tp3ctl0 00h fffff5c1h tmp3 control register 1 tp3ctl1 00h fffff5c2h tmp3 i/o control register 0 tp3ioc0 00h fffff5c3h tmp3 i/o control register 1 tp3ioc1 00h fffff5c4h tmp3 i/o control register 2 tp3ioc2 00h fffff5c5h tmp3 option register 0 tp3opt0 00h fffff5c6h tmp3 capture/compare register 0 tp3ccr0 0000h fffff5c8h tmp3 capture/compare register 1 tp3ccr1 r/w 0000h fffff5cah tmp3 counter read buffer register tp3cnt r 0000h fffff5d0h tmp4 control register 0 tp4ctl0 00h fffff5d1h tmp4 control register 1 tp4ctl1 00h fffff5d2h tmp4 i/o control register 0 tp4ioc0 00h fffff5d3h tmp4 i/o control register 1 tp4ioc1 00h fffff5d4h tmp4 i/o control register 2 tp4ioc2 00h fffff5d5h tmp4 option register 0 tp4opt0 00h fffff5d6h tmp4 capture/compare register 0 tp4ccr0 0000h fffff5d8h tmp4 capture/compare register 1 tp4ccr1 r/w 0000h fffff5dah tmp4 counter read buffer register tp4cnt r 0000h fffff5e0h tmp5 control register 0 tp5ctl0 00h fffff5e1h tmp5 control register 1 tp5ctl1 00h fffff5e2h tmp5 i/o control register 0 tp5ioc0 00h fffff5e3h tmp5 i/o control register 1 tp5ioc1 00h fffff5e4h tmp5 i/o control register 2 tp5ioc2 00h fffff5e5h tmp5 option register 0 tp5opt0 00h fffff5e6h tmp5 capture/compare register 0 tp5ccr0 0000h fffff5e8h tmp5 capture/compare register 1 tp5ccr1 r/w 0000h fffff5eah tmp5 counter read buffer register tp5cnt r 0000h fffff680h watch timer operation mode register wtm 00h fffff690h tmm0 control register 0 tm0ctl0 00h fffff694h tmm0 compare register 0 tm0cmp0 0000h fffff6c0h oscillation stabilization time select register osts 06h fffff6c1h pll lockup time specification register plls 03h fffff6d0h watchdog timer mode register 2 wdtm2 67h fffff6d1h watchdog timer enable register wdte 9ah fffff6e0h real-time output buffer register 0l rtbl0 00h fffff6e2h real-time output buffer register 0h rtbh0 00h fffff6e4h real-time output port mode register 0 rtpm0 00h fffff6e5h real-time output port control register 0 rtpc0 00h fffff700h port 0 function control expansion register pfce0 note 00h fffff706h port 3 function control expansion register l pfce3l 00h fffff70ah port 5 function control expansion register pfce5 r/w 00h note pd70f3792, 70f3793, 70f3841, 70f3842 only
v850es/jg3-l chapter 3 cpu function r01uh0165ej0700 rev.7.00 page 85 of 1113 sep 22, 2011 (8/11) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff712h port 9 function control expansion register pfce9 0000h fffff712h port 9 function control expansion register l pfce9l 00h fffff713h port 9 function control expansion register h pfce9h 00h fffff802h system status register sys 00h fffff80ch internal oscillation mode register rcm 00h fffff810h dma trigger factor register 0 dtfr0 r/w 00h fffff812h dma trigger factor register 1 dtfr1 00h fffff814h dma trigger factor register 2 dtfr2 00h fffff816h dma trigger factor register 3 dtfr3 00h fffff820h power save mode register psmr 00h fffff822h clock control register ckc 0ah fffff824h lock register lockr r 00h fffff828h processor clock control register pcc note 03h fffff82ch pll control register pllctl r/w 01h fffff82eh cpu operation clock status register ccls r 00h fffff870h clock monitor mode register clm 00h fffff888h reset source flag register resf 00h fffff890h low-voltage detection register lvim 00h fffff891h low-voltage detection level select register lvis 00h fffff8b0h prescaler mode register 0 prsm0 00h fffff8b1h prescaler compare register 0 prscm0 00h fffff9fch on-chip debug mode register ocdm note 01h fffffa00h uarta0 control register 0 ua0ctl0 10h fffffa01h uarta0 control register 1 ua0ctl1 00h fffffa02h uarta0 control register 2 ua0ctl2 ffh fffffa03h uarta0 option control register 0 ua0opt0 14h fffffa04h uarta0 status register ua0str r/w 00h fffffa06h uarta0 receive data register ua0rx r ffh fffffa07h uarta0 transmit data register ua0tx ffh fffffa10h uarta1 control register 0 ua1ctl0 10h fffffa11h uarta1 control register 1 ua1ctl1 00h fffffa12h uarta1 control register 2 ua1ctl2 ffh fffffa13h uarta1 option control register 0 ua1opt0 14h fffffa14h uarta1 status register ua1str r/w 00h fffffa16h uarta1 receive data register ua1rx r ffh fffffa17h uarta1 transmit data register ua1tx ffh fffffa20h uarta2 control register 0 ua2ctl0 10h fffffa21h uarta2 control register 1 ua2ctl1 00h fffffa22h uarta2 control register 2 ua2ctl2 ffh fffffa23h uarta2 option control register 0 ua2opt0 14h fffffa24h uarta2 status register ua2str r/w 00h fffffa26h uarta2 receive data register ua2rx r ffh fffffa27h uarta2 transmit data register ua2tx r/w ffh note this is a special register.
v850es/jg3-l chapter 3 cpu function r01uh0165ej0700 rev.7.00 page 86 of 1113 sep 22, 2011 (9/11) manipulatable bits address function register name symbol r/w 1 8 16 default value fffffa30h uarta3 control register 0 ua3ctl0 note 10h fffffa31h uarta3 control register 1 ua3ctl1 note 00h fffffa32h uarta3 control register 2 ua3ctl2 note ffh fffffa33h uarta3 option control register 0 ua3opt0 note r/w 14h fffffa34h uarta3 status register ua3str note 00h fffffa36h uarta3 receive data register ua3rx note r ffh fffffa37h uarta3 transmit data register ua3tx note r/w ffh fffffa40h uarta4 control register 0 ua4ctl0 note 10h fffffa41h uarta4 control register 1 ua4ctl1 note 00h fffffa42h uarta4 control register 2 ua4ctl2 note ffh fffffa43h uarta4 option control register 0 ua4opt0 note 14h fffffa44h uarta4 status register ua4str note 00h fffffa46h uarta4 receive data register ua4rx note r ffh fffffa47h uarta4 transmit data register ua4tx note ffh fffffa50h uarta5 control register 0 ua5ctl0 note 10h fffffa51h uarta5 control register 1 ua5ctl1 note 00h fffffa52h uarta5 control register 2 ua5ctl2 note ffh fffffa53h uarta5 option control register 0 ua5opt0 note 14h fffffa54h uarta5 status register ua5str note r/w 00h fffffa56h uarta5 receive data register ua5rx note r ffh fffffa57h uarta5 transmit data register ua5tx note ffh fffffaa0h uartc0 control register 0 uc0ctl0 note 10h fffffaa1h uartc0 control register 1 uc0ctl1 note 00h fffffaa2h uartc0 control register 2 uc0ctl2 note ffh fffffaa3h uartc0 option control register 0 uc0opt0 note 14h fffffaa4h uartc0 status register uc0str note r/w 00h fffffaa6h uartc0 receive data register uc0rx note 01ffh fffffaa6h uartc0 receive data register l uc0rxl note r ffh fffffaa8h uartc0 transmit data register uc0tx note 01ffh fffffaa8h uartc0 transmit data register l uc0txl note ffh fffffaaah uartc0 option control register 1 uc0opt1 note r/w 00h fffffad0h sub-count register rc1subc note r 0000h fffffad2h second count register rc1sec note 00h fffffad3h minute count register rc1min note 00h fffffad4h hour count register rc1hour note 12h fffffad5h week count register rc1week note 00h fffffad6h day count register rc1day note 01h fffffad7h month count register rc1month note 01h fffffad8h year count register rc1year note 00h fffffad9h time error correction register rc1subu note 00h fffffadah alarm minute set register rc1alm note 00h fffffadbh alarm time set register rc1alh note 12h fffffadch alarm week set register rc1alw note r/w 00h note pd70f3792, 70f3793, 70f3841, 70f3842 only
v850es/jg3-l chapter 3 cpu function r01uh0165ej0700 rev.7.00 page 87 of 1113 sep 22, 2011 (10/11) manipulatable bits address function register name symbol r/w 1 8 16 default value fffffaddh rtc control register 0 rc1cc0 note1 r/w 00h fffffadeh rtc control register 1 rc1cc1 note1 00h fffffadfh rtc control register 2 rc1cc2 note1 00h fffffae0h rtc control register 3 rc1cc3 note1 00h fffffb00h rtc backup control register 0 rtcbu mctl0 note1, 2 00h fffffb03h subclock low-power operation control register sosca mctl note1, 2 00h fffffc00h external interrupt falling edge specification register 0 intf0 00h fffffc06h external interrupt falling edge specification register 3 intf3 00h fffffc13h external interrupt falling edge specification register 9h intf9h 00h fffffc20h external interrupt rising edge specification register 0 intr0 00h fffffc26h external interrupt rising edge specification register 3 intr3 00h fffffc33h external interrupt rising edge specification register 9h intr9h 00h fffffc60h port 0 function register pf0 00h fffffc66h port 3 function register pf3 0000h fffffc66h port 3 function register l pf3l 00h fffffc67h port 3 function register h pf3h 00h fffffc68h port 4 function register pf4 00h fffffc6ah port 5 function register pf5 00h fffffc72h port 9 function register pf9 0000h fffffc72h port 9 function register l pf9l 00h fffffc73h port 9 function register h pf9h 00h fffffd00h csib0 control register 0 cb0ctl0 01h fffffd01h csib0 control register 1 cb0ctl1 00h fffffd02h csib0 control register 2 cb0ctl2 00h fffffd03h csib0 status register cb0str 00h fffffd04h csib0 receive data register cb0rx 0000h fffffd04h csib0 receive data register l cb0rxl r 00h fffffd06h csib0 transmit data register cb0tx 0000h fffffd06h csib0 transmit data register l cb0txl 00h fffffd10h csib1 control register 0 cb1ctl0 01h fffffd11h csib1 control register 1 cb1ctl1 00h fffffd12h csib1 control register 2 cb1ctl2 00h fffffd13h csib1 status register cb1str r/w 00h fffffd14h csib1 receive data register cb1rx 0000h fffffd14h csib1 receive data register l cb1rxl r 00h fffffd16h csib1 transmit data register cb1tx 0000h fffffd16h csib1 transmit data register l cb1txl 00h fffffd20h csib2 control register 0 cb2ctl0 01h fffffd21h csib2 control register 1 cb2ctl1 r/w 00h notes1. pd70f3792, 70f3793, 70f3841, 70f3842 only 2. this is a special register.
v850es/jg3-l chapter 3 cpu function r01uh0165ej0700 rev.7.00 page 88 of 1113 sep 22, 2011 (11/11) manipulatable bits address function register name symbol r/w 1 8 16 default value fffffd22h csib2 control register 2 cb2ctl2 00h fffffd23h csib2 status register cb2str r/w 00h fffffd24h csib2 receive data register cb2rx 0000h fffffd24h csib2 receive data register l cb2rxl r fffffd26h csib2 transmit data register cb2tx 0000h fffffd26h csib2 transmit data register l cb2txl 00h fffffd30h csib3 control register 0 cb3ctl0 01h fffffd31h csib3 control register 1 cb3ctl1 00h fffffd32h csib3 control register 2 cb3ctl2 00h fffffd33h csib3 status register cb3str r/w 00h fffffd34h csib3 receive data register cb3rx 0000h fffffd34h csib3 receive data register l cb3rxl r 00h fffffd36h csib3 transmit data register cb3tx 0000h fffffd36h csib3 transmit data register l cb3txl 00h fffffd40h csib4 control register 0 cb4ctl0 r/w 01h fffffd41h csib4 control register 1 cb4ctl1 00h fffffd42h csib4 control register 2 cb4ctl2 00h fffffd43h csib4 status register cb4str r/w 00h fffffd44h csib4 receive data register cb4rx 0000h fffffd44h csib4 receive data register l cb4rxl r 00h fffffd46h csib4 transmit data register cb4tx r/w 0000h fffffd46h csib4 transmit data register l cb4txl 00h fffffd80h iic shift register 0 iic0 00h fffffd82h iic control register 0 iicc0 00h fffffd83h slave address register 0 sva0 00h fffffd84h iic clock select register 0 iiccl0 00h fffffd85h iic function expansion register 0 iicx0 00h fffffd86h iic status register 0 iics0 r 00h fffffd8ah iic flag register 0 iicf0 00h fffffd90h iic shift register 1 iic1 00h fffffd92h iic control register 1 iicc1 00h fffffd93h slave address register 1 sva1 00h fffffd94h iic clock select register 1 iiccl1 00h fffffd95h iic function expansion register 1 iicx1 r/w 00h fffffd96h iic status register 1 iics1 r 00h fffffd9ah iic flag register 1 iicf1 00h fffffda0h iic shift register 2 iic2 00h fffffda2h iic control register 2 iicc2 00h fffffda3h slave address register 2 sva2 00h fffffda4h iic clock select register 2 iiccl2 00h fffffda5h iic function expansion register 2 iicx2 r/w 00h fffffda6h iic status register 2 iics2 r 00h fffffdaah iic flag register 2 iicf2 00h fffffdbeh external bus interface mode control register eximc r/w 00h
v850es/jg3-l chapter 3 cpu function r01uh0165ej0700 rev.7.00 page 89 of 1113 sep 22, 2011 3.4.7 special registers special registers are registers that are protected from being written with illegal data due to a program hang-up. the v850es/jg3-l has the following nine special registers. ? power save control register (psc) ? clock control register (ckc) ? processor clock control register (pcc) ? clock monitor mode register (clm) ? reset source flag register (resf) ? low-voltage detection register (lvim) ? on-chip debug mode register (ocdm) ? rtc backup control register 0 (rtcbumctl0) ? subclock low-power operation control register 0 (soscamctl) in addition, the prcdm register is provided to protect aga inst a write access to the s pecial registers so that the application system does not inadv ertently stop due to a program hang-up. a write access to the special registers is made in a specific sequence, and an illegal st ore operation is reported to the sys register.
v850es/jg3-l chapter 3 cpu function r01uh0165ej0700 rev.7.00 page 90 of 1113 sep 22, 2011 (1) setting data to special registers set data to the special registers in the following sequence. <1> disable dma operation. <2> prepare data to be set to the special register in a general-purpose register. <3> write the data prepared in <2> to the prcmd register. <4> write the setting data to the special regi ster (by using the following instructions). ? store instruction (st/sst instruction) ? bit manipulation instruction (set1/clr1/not1 instruction) (<5> to <9> insert nop inst ructions (5 instructions).) note <10> enable dma operation if necessary. note when switching to the idle mode or the stop mode (psc.stp bit = 1), 5 nop instructions must be inserted immediately after switching is performed. caution to resume the dma operation in the status before the dma operation was disabled after a special sequence, the dchcn regi ster status must be stored before the dma operation is disabled. after the dchcn register status is stored, the dchcn.tcn bit must be checked before the dma operation is resumed and the following processing must be executed according to the tcn bit status, because completion of dma transfer may occur before the dma operation is disabled. when the tcn bit is 0 (dma transfer not co mpleted), the contents of the dchcn register stored before the dma operation was disabled are written to the dchcn register again. when the tcn bit is 1 (dma transfer completed), dma transfer completion processing is executed. remark n = 0 to 3 [example] psc register (setting standby mode) st.b r11, psmr[r0] ; set psmr register (setting idle1, idle2, and stop modes). <1>clr1 0, dchcn[r0] ; disable dma operation. n = 0 to 3 <2>mov0x02, r10 <3>st.b r10, prcmd[r0] ; write prcmd register. <4>st.b r10, psc[r0] ; set psc register. <5>nop note ; dummy instruction <6>nop note ; dummy instruction <7>nop note ; dummy instruction <8>nop note ; dummy instruction <9>nop note ; dummy instruction <10>set1 0, dchcn[r0] ; enable dma operation. n = 0 to 3 (next instruction) there is no special sequence required to read a special register.
v850es/jg3-l chapter 3 cpu function r01uh0165ej0700 rev.7.00 page 91 of 1113 sep 22, 2011 note five nop instructions or more must be insert ed immediately after setting the idle1 mode, idle2 mode, or stop mode (by setting the psc.stp bit to 1). caution when a store instruction is executed to store data in the command register, interrupts are not acknowledged. this is because it is assumed that steps <3> and <4> above are performed by successive store instructions. if another instruction is placed between <3> and <4>, and if an interrupt is acknowledged by that instruction, the above sequence may not be established, causing malfunction. remark although dummy data is written to the prcmd register, use the same general-purpose register used to set the special register (<4> in the exampl e) to write data to the prcmd register (<3> in the example). the same applies when a gener al-purpose register is used for addressing. (2) command register (prcmd) the prcmd register is an 8-bit regist er that protects the r egisters that may seriously affect the application system from being written, so that the system does not inadvertently st op due to a program hang-up. the first write access to a special register is valid after data has been written in advance to the prcmd register. in this way, the value of the special register can be rewritten only in a spec ific sequence, so as to protect the register from an illegal write access. the prcmd register is write-only, in 8-bit units (undefined data is read when this register is read). 7 reg7 prcmd 6 reg6 5 reg5 4 reg4 3 reg3 2 reg2 1 reg1 0 reg0 after reset: undefined w address: fffff1fch
v850es/jg3-l chapter 3 cpu function r01uh0165ej0700 rev.7.00 page 92 of 1113 sep 22, 2011 (3) system status register (sys) status flags that indicate the ope ration status of the overall system are allocated to this register. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 protection error did not occur. protection error occurred. prerr 0 1 detects protection error sys 0 0 0 0 0 0 prerr after reset: 00h r/w address: fffff802h < > the prerr flag operates under the following conditions. (a) set condition (prerr flag = 1) (i) when data is written to a special register wit hout writing anything to t he prcmd register (when <4> is executed without executing <3> in 3.4.7 (1) setting data to special registers ) (ii) when data is written to an on-chip peripheral i/o register other than a spec ial register (including execution of a bit manipulation instruction) afte r writing data to the prcmd register (if <4> in 3.4.7 (1) setting data to special registers is not the setting of a special register) remark even if an on-chip peripheral i/o register is r ead (except by a bit manipulation instruction) or the internal ram is accessed between an operat ion to write the prcmd register and an operation to write a special register, the prerr flag is not set, and the set data can be written to the special register. (b) clear condition (prerr flag = 0) (i) when 0 is written to the prerr flag (ii) when the system is reset cautions 1. if 0 is written to the prerr bit of the sys register, which is not a special register, immediately after a write acces s to the prcmd register, th e prerr bit is cleared to 0 (the write access takes precedence). 2. if data is written to the prcmd register , which is not a special register, immediately after a write access to the prcmd regi ster, the prerr bit is set to 1.
v850es/jg3-l chapter 3 cpu function r01uh0165ej0700 rev.7.00 page 93 of 1113 sep 22, 2011 3.4.8 registers to be set first be sure to set the following registers first when using the v850es/jg3-l. ? system wait control register (vswc) ? on-chip debug mode register (ocdm) ? watchdog timer mode register 2 (wdtm2) after setting the vswc, ocdm, and wdtm2 registers, set the other registers as necessary. when using the external bus, set each pin to the alternate-function bus control pin mode by using the port-related registers after setting the above registers. (a) system wait control register (vswc) the vswc register controls wait of bus a ccess to the on-chip peripheral i/o registers. three clock cycles are required to access an on-chip peripheral i/o register (without a wait cycle). the v850es/jg3-l requires wait cycles according to the o perating frequency. set the following value to the vswc register in accordance with the frequency used. this register can be read or written in 8-bit units. reset sets this register to 77h (number of waits: 14). vswc after reset: 77h r/w address: fffff06eh 76543210 operating frequency (f clk ) set value of vswc number of waits 32 khz f clk < 16.6 mhz 00h 0 (no waits) 16.6 mhz f clk 20 mhz 01h 1 (b) on-chip debug mode register (ocdm) for details, see chapter 31 on-chip debug function . (c) watchdog timer mode register 2 (wdtm2) the wdtm2 register sets the overflow time a nd the operation clock of watchdog timer 2. watchdog timer 2 automatically starts in the reset mode after reset is released. to specify the operation of watchdog timer 2, write to the wdtm2 register after reset is released. for details, see chapter 12 watchdog timer 2 .
v850es/jg3-l chapter 3 cpu function r01uh0165ej0700 rev.7.00 page 94 of 1113 sep 22, 2011 3.4.9 cautions (1) accessing special on-chip peripheral i/o registers this product has two types of internal system buses. one is a cpu bus and the other is a peripheral bus t hat interfaces with low-speed peripheral hardware. the clock of the cpu bus and the clock of the perip heral bus are asynchronous. if an access to the cpu and an access to the peripheral hardware conflict, ther efore, unexpected illegal data may be transferred. if there is a possibility of a confli ct, the number of cycles for accessing the cpu changes when the peripheral hardware is accessed, so that correct data is transferred. as a result, the cpu does not start processing of the next instruction but enters the wait status. if this wait status occurs, the number of clocks required to execute an instruction increases by the number of wait clocks shown below. this must be taken into consideration if real-time processing is required. when special on-chip peripheral i/o regi sters are accessed, more wait stat es may be required in addition to the wait states set by the vswc register. the access conditions and how to calculate the number of wait states to be inserted (number of cpu clocks) at this time are shown below. table 3-3. registers that requires waits peripheral function register name access k tpncnt read 1 or 2 write ? 1 st access: no wait ? continuous write: 3 or 4 16-bit timer/event counter p (tmp) (n = 0 to 5) tpnccr0, tpnccr1 read 1 or 2 tq0cnt read 1 or 2 write ? 1 st access: no wait ? continuous write: 3 or 4 16-bit timer/event counter q (tmq) tq0ccr0 to tq0ccr3 read 1 or 2 watchdog timer 2 (wdt2) wdtm2 write (when wdt2 operating) 3 real-time output function (rto) rtbl0, rtbh0 write (rtpc0.rtpoe0 bit = 0) 1 ada0m0 read 1 or 2 ada0cr0 to ada0cr11 read 1 or 2 a/d converter ada0cr0h to ada0cr11h read 1 or 2 i 2 c00 to i 2 c02 iics0 to iics2 read 1 crc crcd write 1 number of clocks necessary for access = 3 + i + j + (2 + j) k caution accessing the above registers is prohibited in the following statuses. if a wait cycle is generated, it can only be cleared by a reset. ? when the cpu operates on the subclock and main clock oscillation is stopped ? when the cpu operates on th e internal oscillator clock (however, this only applies immediately after reset ends or if a wdt2 overflow occurs during the oscillation stabilization time.) remark i: value (0) of higher 4 bits of vswc register j: value (0 or 1) of lower 4 bits of vswc register
v850es/jg3-l chapter 3 cpu function r01uh0165ej0700 rev.7.00 page 95 of 1113 sep 22, 2011 (2) conflict between sld instruction and interrupt request (a) description if a conflict occurs between the deco de operation of an instruction in <2> immediately before the sld instruction following an instruction in <1> and an in terrupt request before the instruction in <1> is complete, the execution result of the instru ction in <1> may not be stored in a register. instruction <1> ? ld instruction: ld.b, ld.h, ld.w, ld.bu, ld.hu ? sld instruction: sld.b, sl d.h, sld.w, sld.bu, sld.hu ? multiplication instruction: mul, mulh, mulhi, mulu instruction <2> mov reg1, reg2 satadd reg1, reg2 and reg1, reg2 add reg1, reg2 mulh reg1, reg2 not reg1, reg2 satadd imm5, reg2 tst reg1, reg2 add imm5, reg2 shr imm5, reg2 satsubr reg1, reg2 or reg1, reg2 subr reg1, reg2 cmp reg1, reg2 sar imm5, reg2 satsub reg1, reg2 xor reg1, reg2 sub reg1, reg2 cmp imm5, reg2 shl imm5, reg2 ld.w [r11], r10 if the decode operation of the mo v instruction immediately before the sld instruction and an interrupt request conflict before execution of the ld instruction is complete, the executi on result of instruction may not be stored in a register. mov r10, r28 sld.w 0x28, r10 (b) countermeasure <1> when compiler (ca850) is used use ca850 ver. 2.61 or later because generation of the corresponding instruction sequence can be automatically suppressed. <2> for assembler when executing the sld instruction immediately after instruction , avoid the above operation using either of the following methods. ? insert a nop instruction immediat ely before the sld instruction. ? do not use the same register as the sld instruction destination r egister in the above instruction executed immediately bef ore the sld instruction. ? ? ?
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 96 of 1113 sep 22, 2011 chapter 4 port functions 4.1 features { i/o port pins: 84 ( pd70f3737, 70f3738) 83 ( pd70f3792, 70f3793, 70f3841, 70f3842) ? n-ch open-drain output selectable: 40 (5 v tolerant: 31) { input/output specifiable in 1-bit units 4.2 basic port configuration the v850es/jg3-l features a total of 84/ 83 i/o port pins organized as ports 0, 1, 3 to 5, 7, 9, cm, ct, dh, and dl. the port configuration is shown below. figure 4-1. port configuration p02 p06 port 0 pcm0 pcm3 port cm p90 p915 port 9 pct0 pct1 pct4 pct6 port ct pdh0 pdh4 pdh5 note port dh pdl0 pdl15 port dl p30 p39 port 3 port 1 p40 p42 port 4 p50 p55 port 5 p70 p711 port 7 p10 p11 note pd70f3737, 70f3738 only. caution ports 0, 3 to 5, and 9 (p90 to p96) are 5 v tolerant. table 4-1. i/o buffer power supplies for pins power supply corresponding pins av ref0 port 7 av ref1 port 1 ev dd reset, ports 0, 3 to 5, 9, cm, ct, dh, dl
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 97 of 1113 sep 22, 2011 4.3 port configuration the ports consist of the following hardware. table 4-2. port configuration item configuration control registers port n mode register (pmn: n = 0, 1, 3 to 5, 7, 9, cd, cm, ct, dh, dl) port n mode control register (pmcn: n = 0, 3 to 5, 9, cm, ct, dh, dl) port n function control register (pfcn: n = 0, 3 to 5, 9) port n function control expansion register (pfcen: n = 0, 3, 5, 9 ( pd70f3792, 70f3793, 70f3841, 70f3842) n = 3, 5, 9 ( pd70f3737, 70f3738)) port n function register (pfn: n = 0, 3 to 5, 9) port pins i/o: 84 ( pd70f3737, 70f3738) 83 ( pd70f3792, 70f3793, 70f3841, 70f3842)
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 98 of 1113 sep 22, 2011 (1) port n register (pn) data i/o with external devices is performed by writing to and reading from the pn regist er. the pn register is made up of a port latch that retains the outpu t data and a circuit that reads the pin status. each bit of the pn register corresponds to one pin of port n and can be read or written in 1-bit units. pn7 0 is output. 1 is output. pnm 0 1 control of output data (in output mode) pn6 pn5 pn4 pn3 pn2 pn1 pn0 0 1 2 3 7 5 6 7 pn after reset: 00h note (output latch) r/w note this value is undefined for input-only ports. the operation when writing or reading the pn regist er differs depending on the specified mode. table 4-3. reading an d writing pn register pmcn register setting pmn register setting writing pn register reading pn register output mode (pmnm bit = 0) write to the output latch note . the contents of the output latch are output from the pin. the value of the output latch is read. port mode (pmcnm bit = 0) input mode (pmnm bit = 1) write to the output latch note . the status of the pin is not affected. the pin status is read. output mode (pmnm bit = 0) write to the output latch note . the status of the pin is not affected. the pin operates as an alternate-function pin. the value of the output latch is read. alternate-function mode (pmcnm bit = 1) input mode (pmnm bit = 1) write to the output latch note . the status of the pin is not affected. the pin operates as an alternate-function pin. the pin status is read. note the value written to the output latch is retained until a new value is written to the output latch. the output latch value is cleared by a reset.
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 99 of 1113 sep 22, 2011 (2) port n mode register (pmn) pmn specifies the input mode or output mode of the port. each bit of the pmn register corresponds to one pin of port n and can be specified in 1-bit units. pmn7 output mode input mode pmnm 0 1 control of i/o mode pmn6 pmn5 pmn4 pmn3 pmn2 pmn1 pmn0 pmn after reset: ffh r/w (3) port n mode control register (pmcn) if the port function and the alternate function need to be switched, spec ify the port mode or the alternate function mode by using this register. each bit of the pmcn register corresponds to one pin of port n and can be specified in 1-bit units. port mode alternate function mode pmcnm 0 1 specification of operation mode pmcn7 pmcn6 pmcn5 pmcn4 pmcn3 pmcn2 pmcn1 pmcn0 pmcn after reset: 00h r/w
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 100 of 1113 sep 22, 2011 (4) port n function control register (pfcn) pfcn is a register that specifies the alternate function to be used when one pin has two or more alternate functions. each bit of the pfcn register corresponds to one pin of port n and can be specified in 1-bit units. pfcn7 pfcn6 pfcn5 pfcn4 pfcn3 pfcn2 pfcn1 pfcn0 pfcn after reset: 00h r/w alternate function 1 alternate function 2 pfcnm 0 1 specification of alternate function (5) port n function control expansion register (pfcen) the pfcen register specifies the altern ate function of a port pin in combi nation with the pfcn register if the pin has three or more alternate functions. each bit of the pfcen register corresponds to one pin of port n and can be specified in 1-bit units. pfcn7 pfcn6 pfcn5 pfcn4 pfcn3 pfcn2 pfcn1 pfcn0 pfcen7 pfcen6 pfcen5 pfcen4 pfcen3 pfcen2 pfcen1 pfcen0 after reset: 00h r/w pfcen pfcn alternate function 1 alternate function 2 alternate function 3 alternate function 4 pfcenm 0 0 1 1 specification of alternate function pfcnm 0 1 0 1
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 101 of 1113 sep 22, 2011 (6) port n function register (pfn) pfn is a register that specifies normal outp ut (cmos output) or n-ch open-drain output. each bit of the pfn register corresponds to one pin of port n and can be specified in 1-bit units. pfn7 pfn6 pfn5 pfn4 pfn3 pfn2 pfn1 pfn0 normal output (cmos output) n-ch open-drain output pfnm note 0 1 specification of normal output (cmos output)/n-ch open-drain output pfn after reset: 00h r/w note regardless of the settings of the pmcn re gister, the pfnm bit is valid only if the pmn.pmnm bit is set to 0 (output mode). if the pmnm bit is set to 1 (input mode), the values specified for the pfn register are invalid. example <1> the pfn register values are valid when: pfnm bit = 1 ? n-ch open drain output is specified. pmnm bit = 0 ? output mode is specified. pmcnm bit = any value <2> the pfn register values are invalid when: pfnm bit = 1 ? n-ch open drain output is specified. pmnm bit = 1 ? input mode is specified. pmcnm bit = any value
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 102 of 1113 sep 22, 2011 (7) port setting set a port as illustrated below. figure 4-2. setting of each register and pin function pmcn register output mode input mode pmn register ?0? ?1? ?0? ?1? ?0? ?1? (a) (b) (c) (d) alternate function (when two alternate functions are available) port mode alternate function 1 alternate function 2 pfcn register alternate function (when three or more alternate functions are available) alternate function 1 alternate function 2 alternate function 3 alternate function 4 pfcn register pfcen register pfcenm 0 1 0 1 0 0 1 1 (a) (b) (c) (d) pfcnm remark set the alternate functions in the following sequence. <1> set the pfcn and pfcen registers. <2> set the pmcn register. <3> set the intrn or intfn register (to specify an external interrupt pin). if the pmcn register is set first, an unintend ed function may be set while the pfcn and pfcen registers are being set.
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 103 of 1113 sep 22, 2011 4.3.1 port 0 port 0 is a 5-bit port for which i/o settings can be controlled in 1-bit units. port 0 includes the following alternate-function pins. table 4-4. port 0 alternate-function pins pin no. alternate function gf gc f1 function name name i/o remark block type 19 17 note1 , 7 note2 j2, g4 note2 p02 nmi (/a21) note2 input/ output note2 l-1 note1 , n-2 note2 20 18 g3 p03 intp0/adtrg (/rtc1hz) note2 i/o n-1 note1 , u-15 note2 21 19 h4 p04 intp1 (/rtcdiv/rtccl) note2 i/o l-1 note1 , n-2 note2 22 20 j3 p05 intp2/drst note3 input aa-1 23 21 j4 p06 intp3 input selectable as n-ch open-drain output l-1 notes 1. pd70f3737, 70f3738 only. 2. pd70f3792, 70f3793, 70f3841, 70f3842 only. 3. the drst pin is used for on-chip debugging. if on-chip debugging is not used, fix the p05/intp2/drst pin to low level between when the reset signal of the reset pin is released and when the ocdm.o cdm0 bit is cleared (0). for details, see 4.6.3 cautions on on-chip debug pins . caution the p02 to p06 pins have hysteresis character istics in the input mode of the alternate function, but do not have hysteresis characteristics in the port mode. remark gf: 100-pin plastic lqfp (14 20) ( pd70f3737, 70f3738 only) gc: 100-pin plastic lqfp (fine pitch) (14 14) f1: 121-pin plastic fbga (8 8) (1) port 0 register (p0) 0 outputs 0 outputs 1 p0n 0 1 output data control (in output mode) (n = 2 to 6) p0 p06 p05 p04 p03 p02 0 0 after reset: 00h (output latch) r/w address: fffff400h
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 104 of 1113 sep 22, 2011 (2) port 0 mode register (pm0) 1 output mode input mode pm0n 0 1 i/o mode control (n = 2 to 6) pm0 pm06 pm05 pm04 pm03 pm02 1 1 after reset: ffh r/w address: fffff420h (3) port 0 mode control register (pmc0) 0 pmc0 pmc06 pmc05 pmc04 pmc03 pmc02 0 0 i/o port (p06) intp3 input pmc06 0 1 specification of pin operation i/o port (p05) intp2 input pmc05 0 1 specification of pin operation i/o port (p04) intp1 input (/rtcdiv output/rtccl output) note pmc04 0 1 specification of pin operation i/o port (p03) intp0 input/adtrg input (/rtc1hz output) note pmc03 0 1 specification of pin operation i/o port (p02) nmi input (/a21 output) note pmc02 0 1 specification of pin operation after reset: 00h r/w address: fffff440h note pd70f3792, 70f3793, 70f3841, 70f3842 only. caution the p05/intp2/drst pin becomes the drst pin regardless of the value of the pmc05 bit when the ocdm.ocdm0 bit is 1.
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 105 of 1113 sep 22, 2011 (4) port 0 function control register (pfc0) pfc0 after reset: 00h r/w address: fffff460h 0 0 0 pfc04 note pfc03 pfc02 note 00 note pd70f3792, 70f3793, 70f3841, 70f3842 only remark for details of alternate function specification, see 4.3.1 (6) port 0 alternate function specifications . (5) port 0 function control expansion register (pfce0) ( pd70f3792, 70f3793, 70f 3841, 70f3842 only) 0 pfce0 pfce04 pfce03 0 0 0 00 after reset: 00h r/w address: fffff700h remark for details of alternate function specification, see 4.3.1 (6) port 0 alternate function specifications . (6) port 0 alternate f unction specifications pfce04 pfc04 specification of p04 pin alternate function 0 0 intp1 input 0 1 rtcdiv output note 1 0 rtccl output note 1 1 setting prohibited pfce03 pfc03 specification of p03 pin alternate function 0 0 intp0 input 0 1 adtrg input 1 0 setting prohibited 1 1 rtc1hz output note pfc02 specification of p02 pin alternate function 0 nmi input 1 a21 output note note pd70f3792, 70f3793, 70f3841, 70f3842 only.
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 106 of 1113 sep 22, 2011 (7) port 0 function register (pf0) 0 normal output (cmos output) n-ch open-drain output pf0n 0 1 specification of normal output (cmos output) or n-ch open-drain output (n = 2 to 6) pf0 pf06 pf05 pf04 pf03 pf02 0 0 after reset: 00h r/w address: fffffc60h caution when an output pin is pulled up to ev dd or higher, be sure to set the pf0n bit to 1.
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 107 of 1113 sep 22, 2011 4.3.2 port 1 port 1 is a 2-bit port for which i/o settings can be controlled in 1-bit units. port 1 includes the following alternate-function pins. table 4-5. port 1 alternate-function pins pin no. alternate function gf gc f1 function name name i/o remark block type 5 3 e3 p10 ano0 output ? a-2 6 4 e4 p11 ano1 output ? a-2 caution when the power is turned on, the p10 and p11 pins may output an undefined level temporarily even during reset. remark gf: 100-pin plastic lqfp (14 20) ( pd70f3737, 70f3738 only) gc: 100-pin plastic lqfp (fine pitch) (14 14) f1: 121-pin plastic fbga (8 8) (1) port 1 register (p1) 0 outputs 0 outputs 1 p1n 0 1 output data control (in output mode) (n = 0, 1) p1 0 0 0 0 0 p11 p10 after reset: 00h (output latch) r/w address: fffff402h caution do not read or write the p1 register during d/a conversion (see 15.4.3 cautions).
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 108 of 1113 sep 22, 2011 (2) port 1 mode register (pm1) 1 output mode input mode pm1n 0 1 i/o mode control (n = 0, 1) pm1 1 1 1 1 1 pm11 pm10 after reset: ffh r/w address: fffff422h cautions 1. when using p1n as the alternate func tion (anon pin output), specify the input mode (pm1n bit = 1). 2. when using one of the p10 and p11 pins as an i/o port and the other as a d/a output pin, do so in an applicatio n where the port i/o level does not change during d/a output.
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 109 of 1113 sep 22, 2011 4.3.3 port 3 port 3 is a 10-bit port for which i/o settings can be controlled in 1-bit units. port 3 includes the following alternate-function pins. table 4-6. port 3 alternate-function pins pin no. alternate function gf gc f1 function name name i/o remark block type 27 25 l3 p30 txda0/sob4 output g-3 28 26 k3 p31 rxda0/intp7/ sib4 input n-3 29 27 l4 p32 ascka0/sckb4/ tip00/top00 i/o u-1 30 28 k4 p33 tip01/top01 i/o g-1 31 29 k5 p34 tip10/top10 i/o g-1 32 30 j5 p35 tip11/top11 i/o g-1 33 31 h5 p36 txda3 note1 output c-1 note2 , d-2 note1 34 32 j6 p37 rxda3 note1 input c-1 note2 , d-1 note1 37 35 h6 p38 txda2/sda00 i/o g-12 38 36 h7 p39 rxda2/scl00 i/o selectable as n-ch open-drain output g-6 notes1. pd70f3792, 70f3793, 70f3841, 70f3842 only. 2. pd70f3737, 70f3738 only. caution the p31 to p35, p37, p38, and p39 pins have hysteresis characteristics in the input mode of the alternate-function pin, but do not have hysteresis characteristics in the port mode. remark gf: 100-pin plastic lqfp (14 20) ( pd70f3737, 70f3738 only) gc: 100-pin plastic lqfp (fine pitch) (14 14) f1: 121-pin plastic fbga (8 8)
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 110 of 1113 sep 22, 2011 (1) port 3 register (p3) outputs 0 outputs 1 p3n 0 1 output data control (in output mode) (n = 0 to 9) p3 (p3h) after reset: 0000h (output latch) r/w address: p3 fffff406h, p3l fffff406h, p3h fffff407h 0 0 0 0 0 0 p39 p38 p37 p36 p35 p34 p33 p32 p31 p30 8 9 10 11 12 13 14 15 (p3l) remarks 1. the p3 register can be read or written in 16-bit units. however, when using the higher 8 bits of t he p3 register as the p3 h register and the lower 8 bits as the p3l register, p3 can be read or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of the p3 register in 8- bit or 1-bit units, specify them as bits 0 to 7 of the p3h register. (2) port 3 mode register (pm3) 1 output mode input mode pm3n 0 1 i/o mode control (n = 0 to 9) 1 1 1 1 1 pm39 pm38 pm37 pm36 pm35 pm34 pm33 pm32 pm31 pm30 after reset: ffffh r/w address: pm3 fffff426h, pm3l fffff426h, pm3h fffff427h 8 9 10 11 12 13 14 15 pm3 (pm3h) (pm3l) remarks 1. the pm3 register can be read or written in 16-bit units. however, when using the higher 8 bits of the pm3 register as the pm3h register and the lower 8 bits as the pm3l register, pm3 can be read or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of the pm3 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pm3h register.
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 111 of 1113 sep 22, 2011 (3) port 3 mode control register (pmc3) i/o port (p39) rxda2 input/scl00 i/o pmc39 0 1 specification of pin operation i/o port (p38) txda2 output/sda00 i/o pmc38 0 1 specification of pin operation after reset: 0000h r/w address: pmc3 fffff446h, pmc3l fffff446h, pmc3h fffff447h pmc37 pmc36 pmc35 pmc34 pmc33 pmc32 pmc31 pmc30 0 0 0 0 0 0 pmc39 pmc38 8 9 10 11 12 13 14 15 pmc3 (pmc3h) (pmc3l) i/o port (p37) rxda3 input note pmc37 0 1 specification of pin operation i/o port (p36) txda3 output note pmc36 0 1 specification of pin operation i/o port (p35) tip11 input/top11 output pmc35 0 1 specification of pin operation i/o port (p34) tip10 input/top10 output pmc34 0 1 specification of pin operation i/o port (p33) tip01 input/top01 output pmc33 0 1 specification of pin operation i/o port (p32) ascka0 input/sckb4 i/o/tip00 input/top00 output pmc32 0 1 specification of pin operation i/o port (p31) rxda0 input/sib4 input/intp7 input pmc31 0 1 specification of pin operation i/o port (p30) txda0 output/sob4 output pmc30 0 1 specification of pin operation note pd70f3792, 70f3793, 70f 3841, 70f3842 only caution be sure to clea r bits 15 to 10 to ?0?. remarks 1. the pmc3 register can be read or written in 16-bit units. however, when using the higher 8 bits of th e pmc3 register as the pmc3h register and the lower 8 bits as the pmc3l register, pmc3 can be read or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of the pmc3 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pmc3h register.
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 112 of 1113 sep 22, 2011 (4) port 3 function control register (pfc3) after reset: 0000h r/w address: pfc3 fffff466h, pfc3l fffff466h, pfc3l fffff467h 0 0 0 0 0 0 pfc39 pfc38 0 0 pfc35 pfc34 pfc33 pfc32 pfc31 pfc30 8 9 10 11 12 13 14 15 pfc3 (pfc3h) (pfc3l) remarks 1. for details of alternate function specification, see 4.3.3 (6) port 3 alternate function specifications . 2. the pfc3 register can be read or written in 16-bit units. however, when using the higher 8 bits of th e pfc3 register as the pfc3h register and the lower 8 bits as the pfc3l register, pfc3 c an be read or written in 8-bit and 1-bit units. 3. to read/write bits 8 to 15 of the pfc3 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pfc3h register. (5) port 3 function control expansion register l (pfce3l) pfce3l after reset: 00h r/w address: fffff706h 0 0 0 0 0 pfce32 0 0 remark for details of alternate function specification, see 4.3.3 (6) port 3 alternate function specifications .
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 113 of 1113 sep 22, 2011 (6) port 3 alternate f unction specifications pfc39 specification of p39 pin alternate function 0 rxda2 input 1 scl00 i/o pfc38 specification of p38 pin alternate function 0 txda2 output 1 sda00 i/o pfc35 specification of p35 pin alternate function 0 tip11 input 1 top11 output pfc34 specification of p34 pin alternate function 0 tip10 input 1 top10 output pfc33 specification of p33 pin alternate function 0 tip01 input 1 top01 output pfce32 pfc32 specification of p32 pin alternate function 0 0 ascka0 input 0 1 sckb4 i/o 1 0 tip00 input 1 1 top00 output pfc31 specification of p31 pin alternate function 0 rxda0 input/intp7 note input 1 sib4 input pfc30 specification of p30 pin alternate function 0 txda0 output 1 sob4 output note intp7 and rxda0 are alternate functions. when using the pin for rxda0, disable edge detection for intp7 (clear the intf3.intf31 bit and the intr3.intr31 bit to 0). when using the pin for intp7, stop uarta0 reception (clear the ua0ctl0.ua0rxe bit to 0).
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 114 of 1113 sep 22, 2011 (7) port 3 function register (pf3) after reset: 0000h r/w address: pf3 fffffc66h, pf3l fffffc66h, pf3h fffffc67h pf37 pf36 pf35 pf34 pf33 pf32 pf31 pf30 0 0 0 0 0 0 pf39 pf38 8 9 10 11 12 13 14 15 normal output (cmos output) n-ch open-drain output pf3n 0 1 specification of normal output (cmos output) or n-ch open-drain output (n = 0 to 9) pf3 (pf3h) (pf3l) caution when an output pin is pulled up to ev dd or higher, be sure to set the pf3n bit to 1. remarks 1. the pf3 register can be read or written in 16-bit units. however, when using the higher 8 bits of the pf3 register as the pf3h register and the lower 8 bits as the pf3l register, pf3 can be re ad or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of the pf3 register in 8-bit or 1-bit units , specify them as bits 0 to 7 of the pf3h register.
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 115 of 1113 sep 22, 2011 4.3.4 port 4 port 4 is a 3-bit port that controls i/o in 1-bit units. port 4 includes the following alternate-function pins. table 4-7. port 4 alternate-function pins pin no. alternate function gf gc f1 function name name i/o remark block type 24 22 k1 p40 sib0/sda01 i/o g-6 25 23 k2 p41 sob0/scl01 i/o g-12 26 24 l2 p42 sckb0 i/o selectable as n-ch open-drain output e-3 caution the p40 to p42 pins have hysteresis characteristics in the input mode of the alternate-function pin, but do not have hysteresis characteristics in the port mode. remark gf: 100-pin plastic lqfp (14 20) ( pd70f3737, 70f3738 only) gc: 100-pin plastic lqfp (fine pitch) (14 14) f1: 121-pin plastic fbga (8 8) (1) port 4 register (p4) 0 outputs 0 outputs 1 p4n 0 1 output data control (in output mode) (n = 0 to 2) p4 0 0 0 0 p42 p41 p40 after reset: 00h (output latch) r/w address: fffff408h (2) port 4 mode register (pm4) 1 output mode input mode pm4n 0 1 i/o mode control (n = 0 to 2) pm4 1 1 1 1 pm42 pm41 pm40 after reset: ffh r/w address: fffff428h
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 116 of 1113 sep 22, 2011 (3) port 4 mode control register (pmc4) 0 pmc4 0 0 0 0 pmc42 pmc41 pmc40 i/o port (p42) sckb0 i/o pmc42 0 1 specification of pin operation i/o port (p41) sob0 output/scl01 i/o pmc41 0 1 specification of pin operation i/o port (p40) sib0 input/sda01 i/o pmc40 0 1 specification of pin operation after reset: 00h r/w address: fffff448h (4) port 4 function control register (pfc4) pfc4 after reset: 00h r/w address: fffff468h 0 0 0 0 0 0 pfc41 pfc40 sob0 output scl01 i/o pfc41 0 1 specification of p41 pin alternate function sib0 input sda01 i/o pfc40 0 1 specification of p40 pin alternate function (5) port 4 function register (pf4) 0 normal output (cmos output) n-ch open-drain output pf4n 0 1 specification of normal output (cmos output) or n-ch open-drain output (n = 0 to 2) pf4 0 0 0 0 pf42 pf41 pf40 after reset: 00h r/w address: fffffc68h caution when an output pin is pulled up to ev dd or higher, be sure to set the pf4n bit to 1.
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 117 of 1113 sep 22, 2011 4.3.5 port 5 port 5 is a 6-bit port that controls i/o in 1-bit units. port 5 includes the following alternate-function pins. table 4-8. port 5 alternate-function pins pin no. alternate function gf gc f1 function name name i/o remark block type 39 37 l7 p50 tiq01/kr0/toq01/rtp00 i/o u-5 40 38 k7 p51 tiq02/kr1/toq02/rtp01 i/o u-5 41 39 j7 p52 tiq03/kr2/toq03/rtp02/ ddi note i/o u-6 42 40 l8 p53 sib2/kr3/tiq00/toq00/ rtp03/ddo note i/o u-7 43 41 k8 p54 sob2/kr4/rtp04/dck note i/o u-8 44 42 j8 p55 sckb2/kr5/rtp05/dms note i/o selectable as n-ch open-drain output u-9 note the ddi, ddo, dck, and dms pins are used for on-chip debugging. cautions 1. when the power is turned on, the p53 pin may output an undefined level temporarily even during reset. 2. the p50 to p55 pins have hysteresis charact eristics in the input mode of the alternate function, but do not have hysteresis characteristics in the port mode. remark gf: 100-pin plastic lqfp (14 20) ( pd70f3737, 70f3738 only) gc: 100-pin plastic lqfp (fine pitch) (14 14) f1: 121-pin plastic fbga (8 8) (1) port 5 register (p5) 0 outputs 0 outputs 1 p5n 0 1 output data control (in output mode) (n = 0 to 5) p5 0 p55 p54 p53 p52 p51 p50 after reset: 00h (output latch) r/w address: fffff40ah
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 118 of 1113 sep 22, 2011 (2) port 5 mode register (pm5) 1 output mode input mode pm5n 0 1 i/o mode control (n = 0 to 5) pm5 1 pm55 pm54 pm53 pm52 pm51 pm50 after reset: ffh r/w address: fffff42ah (3) port 5 mode control register (pmc5) 0 pmc5 0 pmc55 pmc54 pmc53 pmc52 pmc51 pmc50 i/o port (p55) sckb2 i/o/kr5 input/rtp05 output pmc55 0 1 specification of pin operation i/o port (p54) sob2 output/kr4 input/rtp04 output pmc54 0 1 specification of pin operation i/o port (p53) sib2 input/kr3 input/tiq00 input/toq00 output/rtp03 output pmc53 0 1 specification of pin operation i/o port (p52) tiq03 input/kr2 input/toq03 output/rtp02 output pmc52 0 1 specification of pin operation i/o port (p51) tiq02 input/kr1 input/toq02 output/rtp01 output pmc51 0 1 specification of pin operation i/o port (p50) tiq01 input/kr0 input/toq01 output/rtp00 output pmc50 0 1 specification of pin operation after reset: 00h r/w address: fffff44ah
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 119 of 1113 sep 22, 2011 (4) port 5 function control register (pfc5) 0 pfc5 0 pfc55 pfc54 pfc53 pfc52 pfc51 pfc50 after reset: 00h r/w address: fffff46ah remark for details of alternate function specification, see 4.3.5 (6) port 5 alternate function specifications . (5) port 5 function contro l expansion register (pfce5) 0 pfce5 0 pfce55 pfce54 pfce53 pfce52 pfce51 pfce50 after reset: 00h r/w address: fffff70ah remark for details of alternate function specification, see 4.3.5 (6) port 5 alternate function specifications . (6) port 5 alternate f unction specifications pfce55 pfc55 specification of p55 pin alternate function 0 0 sckb2 i/o 0 1 kr5 input 1 0 setting prohibited 1 1 rtp05 output pfce54 pfc54 specification of p54 pin alternate function 0 0 sob2 output 0 1 kr4 input 1 0 setting prohibited 1 1 rtp04 output pfce53 pfc53 specification of p53 pin alternate function 0 0 sib2 input 0 1 tiq00 input/kr3 note input 1 0 toq00 output 1 1 rtp03 output
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 120 of 1113 sep 22, 2011 pfce52 pfc52 specification of p52 pin alternate function 0 0 setting prohibited 0 1 tiq03 input/kr2 note input 1 0 toq03 input 1 1 rtp02 output pfce51 pfc51 specification of p51 pin alternate function 0 0 setting prohibited 0 1 tiq02 input/kr1 note input 1 0 toq02 output 1 1 rtp01 output pfce50 pfc50 specification of p50 pin alternate function 0 0 setting prohibited 0 1 tiq01 input/kr0 note input 1 0 toq01 output 1 1 rtp00 output note krn and tiq0m are alternate functions. when using the pin for tiq0m, disable key return detection for krn (clear the krm.krmn bit to 0). when using the pin for krn, disable edge detection for tiq0m (n = 0 to 3, m = 0 to 3). alternate function name use as tiq0m function use as krn function kr0/tiq01 krm.krm0 bit = 0 tq0ioc1. tq0tig2, tq0ioc1. tq0tig3 bits = 0 kr1/tiq02 krm.krm1 bit = 0 tq0ioc1.tq0tig4, tq0ioc1.tq0tig5 bits = 0 kr2/tiq03 krm.krm2 bit = 0 tq0ioc1.tq0tig6, tq0ioc1.tq0tig7 bits = 0 kr3/tiq00 krm.krm3 bit = 0 tq0ioc1.tq0tig0, tq0ioc1.tq0tig1 bits = 0 tq0ioc2.tq0ees0, tq0ioc2.tq0ees1 bits = 0 tq0ioc2.tq0ets0, tq0ioc2.tq0ets1 bits = 0
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 121 of 1113 sep 22, 2011 (7) port 5 function register (pf5) 0 normal output (cmos output) n-ch open-drain output pf5n 0 1 specification of normal output (cmos output) or n-ch open-drain output (n = 0 to 5) pf5 0 pf55 pf54 pf53 pf52 pf51 pf50 after reset: 00h r/w address: fffffc6ah cautions 1. when an output pin is pulled up to ev dd or higher, be sure to set the pf5n bit to 1. 2. bits 6 and 7 of the pf5 re gister must always be set to 0.
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 122 of 1113 sep 22, 2011 4.3.6 port 7 port 7 is a 12-bit port for which i/o settings can be controlled in 1-bit units. port 7 includes the following alternate-function pins. table 4-9. port 7 alternate-function pins pin no. alternate function gf gc f1 function name name i/o remark block type 2 100 a3 p70 ani0 input a-1 1 99 b3 p71 ani1 input a-1 100 98 c3 p72 ani2 input a-1 99 97 d3 p73 ani3 input a-1 98 96 a4 p74 ani4 input a-1 97 95 b4 p77 ani5 input a-1 96 94 c4 p76 ani6 input a-1 95 93 d4 p77 ani7 input a-1 94 92 a5 p78 ani8 input a-1 93 91 b5 p79 ani9 input a-1 92 90 c5 p710 ani10 input a-1 91 89 d5 p711 ani11 input ? a-1 remark gf: 100-pin plastic lqfp (14 20) ( pd70f3737, 70f3738 only) gc: 100-pin plastic lqfp (fine pitch) (14 14) f1: 121-pin plastic fbga (8 8)
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 123 of 1113 sep 22, 2011 (1) port 7 register h, port 7 register l (p7h, p7l) outputs 0 outputs 1 p7n 0 1 output data control (in output mode) (n = 0 to 11) p7h p7l after reset: 00h (output latch) r/w address: p7l fffff40eh, p7h fffff40fh p77 p76 p75 p74 p73 p72 p71 p70 0 0 0 0 p711 p710 p79 p78 caution do not read or write the p7h and p7 l registers during a/d conversion (see 13.6 (4) alternate i/o). remark these registers cannot be accessed in 16-bit units as the p7 register. they can be read or written in 8-bit or 1-bit unit s as the p7h and p7l registers. (2) port 7 mode register h, port 7 mode register l (pm7h, pm7l) 1 output mode input mode pm7n 0 1 i/o mode control (n = 0 to 11) pm7h pm7l 1 1 1 pm711 pm710 pm79 pm78 pm77 pm76 pm75 pm74 pm73 pm72 pm71 pm70 after reset: ffh r/w address: pm7l fffff42eh, pm7h fffff42fh caution when using the p7n pin as its alternate function (anin pin), set the pm7n bit to 1. remark these registers cannot be accessed in 16-bit units as the pm7 register. they can be read or written in 8-bit or 1-bit units as the pm7h and pm7l registers.
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 124 of 1113 sep 22, 2011 4.3.7 port 9 port 9 is a 16-bit port for which i/o settings can be controlled in 1-bit units. port 9 includes the following alternate-function pins. table 4-10. port 9 alternate-function pins pin no. alternate function gf gc f1 function nam e name i/o remark block type 45 43 h8 p90 a0/kr6/txda1/sda02 i/o u-10 46 44 l9 p91 a1/kr7/rxda1/scl02 i/o u-11 47 45 k9 p92 a2/tip41/top41 (/txda4) note1 i/o u-12 note2 , u-16 note1 48 46 j9 p93 a3/tip40/top40 (/rxda4) note1 i/o u-12 note2 , u-14 note1 49 47 l10 p94 a4/tip31/top31 (/txda5) note1 i/o u-12 note2 , u-16 note1 50 48 k10 p95 a5/tip30/top30 (/rxda5) note1 i/o u-12 note2 , u-14 note1 51 49 k11 p96 a6 (/txdc0) note1 /tip21/top21 i/o u-13 note2 , u-16 note1 52 50 j11 p97 a7/sib1 (/rxdc0) note1 /tip20/top20 i/o u-14 53 51 j10 p98 a8/sob1 output g-3 54 52 h11 p99 a9/sckb1 i/o g-5 55 53 h10 p910 a10/sib3 i/o g-2 56 54 h9 p911 a11/sob3 output g-3 57 55 g11 p912 a12/sckb3 i/o g-5 58 56 g10 p913 a13/intp4 i/o n-2 59 57 g9 p914 a14/intp5/tip51/top51 i/o u-15 60 58 g8 p915 a15/intp6/tip50/top50 i/o selectable as n-ch open-drain output u-15 notes 1. pd70f3792, 70f3793, 70f3841, 70f3842 only. 2. pd70f3737, 70f3738 only. caution the p90 to p97, p99, p910, and p912 to p915 pins have hysteresis characteristics in the input mode of the alternate-function pin, but do not have hysteresis characteristics in the port mode. remark gf: 100-pin plastic lqfp (14 20) ( pd70f3737, 70f3738 only) gc: 100-pin plastic lqfp (fine pitch) (14 14) f1: 121-pin plastic fbga (8 8)
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 125 of 1113 sep 22, 2011 (1) port 9 register (p9) p915 outputs 0 outputs 1 p9n 0 1 output data control (in output mode) (n = 0 to 15) p914 p913 p912 p911 p910 p99 p98 after reset: 0000h (output latch) r/w address: p9 fffff412h, p9l fffff412h, p9h fffff413h p97 p96 p95 p94 p93 p92 p91 p90 8 9 10 11 12 13 14 15 p9 (p9h) (p9l) remarks 1. the p9 register can be read or written in 16-bit units. however, when using the higher 8 bits of t he p9 register as the p9 h register and the lower 8 bits as the p9l register, p9 can be read or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of the p9 register in 8- bit or 1-bit units, specify them as bits 0 to 7 of the p9h register. (2) port 9 mode register (pm9) pm97 output mode input mode pm9n 0 1 i/o mode control (n = 0 to 15) pm96 pm95 pm94 pm93 pm92 pm91 pm90 after reset: ffffh r/w address: pm9 fffff432h, pm9l fffff432h, pm9h fffff433h pm915 pm914 pm913 pm912 pm911 pm910 pm99 pm98 8 9 10 11 12 13 14 15 pm9 (pm9h) (pm9l) remarks 1. the pm9 register can be read or written in 16-bit units. however, when using the higher 8 bits of the pm9 register as the pm9h register and the lower 8 bits as the pm9l register, pm9 can be r ead or written in 8-bit and 1-bit units. 2. to read/write bits 8 to 15 of the pm9 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pm9h register.
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 126 of 1113 sep 22, 2011 (3) port 9 mode control register (pmc9) (1/2) i/o port (p915) a15 output/intp6 input/tip50 input/top50 output pmc915 0 1 specification of pin operation pmc97 pmc96 pmc95 pmc94 pmc93 pmc92 pmc91 pmc90 after reset: 0000h r/w address: pmc9 fffff452h, pmc9l fffff452h, pmc9h fffff453h pmc915 pmc914 pmc913 pmc912 pmc911 pmc910 pmc99 pmc98 i/o port (p914) a14 output/intp5 input/tip51 input/top51 output pmc914 0 1 specification of pin operation i/o port (p911) a11 output/sob3 output pmc911 0 1 specification of pin operation i/o port (p910) a10 output/sib3 input pmc910 0 1 specification of pin operation i/o port (p99) a9 output/sckb1 i/o pmc99 0 1 specification of pin operation i/o port (p913) a13 output/intp4 input pmc913 0 1 specification of pin operation i/o port (p912) a12 output/sckb3 i/o pmc912 0 1 specification of pin operation 8 9 10 11 12 13 14 15 pmc9 (pmc9h) (pmc9l) i/o port (p98) a8 output/sob1 output pmc98 0 1 specification of pin operation remarks 1. the pmc9 register can be read or written in 16-bit units. however, when using the higher 8 bits of th e pmc9 register as the pmc9h register and the lower 8 bits as the pmc9l register, pmc9 can be read or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of the pmc9 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pmc9h register.
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 127 of 1113 sep 22, 2011 (2/2) i/o port (p97) a7 output/sib1 input (/rxdc0 input) note /tip20 input/top20 output pmc97 0 1 specification of pin operation i/o port (p96) a6 output (/txdc0 output) note /tip21 input/top21 output pmc96 0 1 specification of pin operation i/o port (p95) a5 output/tip30 input/top30 output (/rxda5 input) note pmc95 0 1 specification of pin operation i/o port (p94) a4 output/tip31 input/top31 output (/txda5 output) note pmc94 0 1 specification of pin operation i/o port (p93) a3 output/tip40 input/top40 outputt (/rxda4 input) note pmc93 0 1 specification of pin operation i/o port (p92) a2 output/tip41 input/top41 output (/txda4 output) note pmc92 0 1 specification of pin operation i/o port (p91) a1 output/kr7 input/rxda1 input/scl02 i/o pmc91 0 1 specification of pin operation i/o port (p90) a0 output/kr6 input/txda1 output/sda02 i/o pmc90 0 1 specification of pin operation note pd70f3792, 70f3793, 70f3841, 70f3842 only. caution when using the a0 to a15 pins as the alternate functions of the p90 to p915 pins, be sure to set all 16 bits of the pmc9 register to ffffh at once.
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 128 of 1113 sep 22, 2011 (4) port 9 function control register (pfc9) caution when performing separate address bus output (a0 to a15), set the pmc9 register to ffffh for all 16 bits at once after clearing the pfc9 and pfce9 registers to 0000h. after reset: 0000h r/w address: pfc9 fffff472h, pfc9l fffff472h, pfc9h fffff473h pfc97 pfc96 pfc95 pfc94 pfc93 pfc92 pfc91 pfc90 pfc915 pfc914 pfc913 pfc912 pfc911 pfc910 pfc99 pfc98 8 9 10 11 12 13 14 15 pfc9 (pfc9h) (pfc9l) remarks 1. for details of alternate function specification, see 4.3.7 (6) port 9 alternate function specifications . 2. the pfc9 register can be read or written in 16-bit units. however, when using the higher 8 bits of th e pfc9 register as the pfc9h register and the lower 8 bits as the pfc9l register, pfc9 c an be read or written in 8-bit or 1-bit units. 3. to read/write bits 8 to 15 of the pfc9 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pfc9h register. (5) port 9 function control expansion register (pfce9) caution when performing separate address bus output (a0 to a15), set the pmc9 register to ffffh for all 16 bits at once after clearing the pfc9 and pfce9 registers to 0000h. after reset: 0000h r/w address: pfce9 fffff712h, pfce9l fffff712h, pfce9h fffff713h pfce97 pfce96 pfce95 pfce94 pfce93 pfce92 pfce91 pfce90 pfce915 pfce914 0 0 0 0 0 0 8 9 10 11 12 13 14 15 pfce9 (pfce9h) (pfce9l) remarks 1. for details of alternate function specification, see 4.3.7 (6) port 9 alternate function specifications . 2. the pfce9 register can be read or written in 16-bit units. however, when using the higher 8 bits of t he pfce9 register as the pfce9h register and the lower 8 bits as the pfce9l register, pfce9 can be read or written in 8-bit or 1-bit units. 3. to read/write bits 8 to 15 of the pfce9 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pfce9h register.
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 129 of 1113 sep 22, 2011 (6) port 9 alternate f unction specifications pfce915 pfc915 specification of p915 pin alternate function 0 0 a15 output 0 1 intp6 input 1 0 tip50 input 1 1 top50 output pfce914 pfc914 specification of p914 pin alternate function 0 0 a14 output 0 1 intp5 input 1 0 tip51 input 1 1 top51 output pfc913 specification of p913 pin alternate function 0 a13 output 1 intp4 input pfc912 specification of p912 pin alternate function 0 a12 output 1 sckb3 i/o pfc911 specification of p911 pin alternate function 0 a11 output 1 sob3 output pfc910 specification of p910 pin alternate function 0 a10 output 1 sib3 input pfc99 specification of p99 pin alternate function 0 a9 output 1 sckb1 i/o pfc98 specification of p98 pin alternate function 0 a8 output 1 sob1 output pfce97 pfc97 specification of p97 pin alternate function 0 0 a7 output 0 1 sib1 input (/rxdc0 input) notes 1, 2 1 0 tip20 input 1 1 top20 output notes 1. pd70f3792, 70f3793, 70f3841, 70f3842 only 2. the sib1 and rxdc0 functions cannot be us ed at the same time. when using the pin for sib1, stop uartc0 reception. (clear the uc0ctl0.uc0rxe bit to 0.) when using the pin for rxdc0, stop csib0 reception. (clear the cb1ctl0.cb1rxe bit to 0.)
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 130 of 1113 sep 22, 2011 pfce96 pfc96 specification of p96 pin alternate function 0 0 a6 output 0 1 txdc0 output note1 1 0 tip21 input 1 1 top21 output pfce95 pfc95 specification of p95 pin alternate function 0 0 a5 output 0 1 tip30 input 1 0 top30 output 1 1 rxda5 input note1 pfce94 pfc94 specification of p94 pin alternate function 0 0 a4 output 0 1 tip31 input 1 0 top31 output 1 1 txda5 output note1 pfce93 pfc93 specification of p93 pin alternate function 0 0 a3 output 0 1 tip40 input 1 0 top40 output 1 1 rxda4 input note1 pfce92 pfc92 specification of p92 pin alternate function 0 0 a2 output 0 1 tip41 input 1 0 top41 output 1 1 txda4 output note1 pfce91 pfc91 specification of p91 pin alternate function 0 0 a1 output 0 1 kr7 input 1 0 rxda1 input/kr7 input note2 1 1 scl02 i/o pfce90 pfc90 specification of p90 pin alternate function 0 0 a0 output 0 1 kr6 input 1 0 txda1 output 1 1 sda02 i/o notes 1. pd70f3792, 70f3793, 70f3841, 70f3842 only. 2. the rxda1 and kr7 functions cannot be used at the same time. when using the pin for rxda1, do not use the kr7 function. when using the pin for kr7, do not use the rxda1 function. (it is recommended to set the pfc91 bit to 1 and clear the pfce91 bit to 0.)
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 131 of 1113 sep 22, 2011 (7) port 9 function register (pf9) after reset: 0000h r/w address: pf9 fffffc72h, pf9l fffffc72h, pf9h fffffc73h pf97 pf96 pf95 pf94 pf93 pf92 pf91 pf90 pf915 pf914 pf913 pf912 pf911 pf910 pf99 pf98 normal output (cmos output) n-ch open-drain output pf9n 0 1 specification of normal output (cmos output) or n-ch open-drain output (n = 0 to 15) 8 9 10 11 12 13 14 15 pf9 (pf9h) (pf9l) caution when output pins p90 to p96 are pulled up to ev dd or higher, be sure to set the pf9n bit to 1. pull up output pins p97 to p915 to the same potential as ev dd , even when they are used as n-ch open-drain output pins. remarks 1. the pf9 register can be read or written in 16-bit units. however, when using the higher 8 bits of the pf9 register as the pf9h register and the lower 8 bits as the pf9l register, pf9 can be re ad or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of the pf9 register in 8-bit or 1-bit units , specify them as bits 0 to 7 of the pf9h register.
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 132 of 1113 sep 22, 2011 4.3.8 port cm port cm is a 4-bit port for which i/o setti ngs can be controlled in 1-bit units. port cm includes the following alternate-function pins. table 4-11. port cm alternate-function pins pin no. alternate function gf gc f1 function name name i/o remark block type 63 61 f11 pcm0 wait input d-1 64 62 f10 pcm1 clkout output d-2 65 63 e10 pcm2 hldak output d-2 66 64 e9 pcm3 hldrq input ? d-1 remark gf: 100-pin plastic lqfp (14 20) ( pd70f3737, 70f3738 only) gc: 100-pin plastic lqfp (fine pitch) (14 14) f1: 121-pin plastic fbga (8 8) (1) port cm register (pcm) 0 outputs 0 outputs 1 pcmn 0 1 output data control (in output mode) (n = 0 to 3) pcm 0 0 0 pcm3 pcm2 pcm1 pcm0 after reset: 00h (output latch) r/w address: fffff00ch (2) port cm mode register (pmcm) 1 output mode input mode pmcmn 0 1 i/o mode control (n = 0 to 3) pmcm 1 1 1 pmcm3 pmcm2 pmcm1 pmcm0 after reset: ffh r/w address: fffff02ch
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 133 of 1113 sep 22, 2011 (3) port cm mode control register (pmccm) 0 pmccm 0 0 0 pmccm3 pmccm2 pmccm1 pmccm0 i/o port (pcm3) hldrq input pmccm3 0 1 specification of pin operation i/o port (pcm2) hldak output pmccm2 0 1 specification of pin operation i/o port (pcm1) clkout output pmccm1 0 1 specification of pin operation i/o port (pcm0) wait input pmccm0 0 1 specification of pin operation after reset: 00h r/w address: fffff04ch
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 134 of 1113 sep 22, 2011 4.3.9 port ct port ct is a 4-bit port for which i/o setti ngs can be controlled in 1-bit units. port ct includes the following alternate-function pins. table 4-12. port ct alternate-function pins pin no. alternate function gf gc f1 function name name i/o remark block type 67 65 e8 pct0 wr0 output d-2 68 66 d10 pct1 wr1 output d-2 69 67 d9 pct4 rd output d-2 70 68 d8 pct6 astb output ? d-2 remark gf: 100-pin plastic lqfp (14 20) ( pd70f3737, 70f3738 only) gc: 100-pin plastic lqfp (fine pitch) (14 14) f1: 121-pin plastic fbga (8 8) (1) port ct register (pct) 0 outputs 0 outputs 1 pctn 0 1 output data control (in output mode) (n = 0, 1, 4, 6) pct pct6 0 pct4 0 0 pct1 pct0 after reset: 00h (output latch) r/w address: fffff00ah (2) port ct mode register (pmct) 1 output mode input mode pmctn 0 1 i/o mode control (n = 0, 1, 4, 6) pmct pmct6 1 pmct4 1 1 pmct1 pmct0 after reset: ffh r/w address: fffff02ah
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 135 of 1113 sep 22, 2011 (3) port ct mode control register (pmcct) 0 pmcct pmcct6 0 pmcct4 0 0 pmcct1 pmcct0 i/o port (pct6) astb output pmcct6 0 1 specification of pin operation i/o port (pct4) rd output pmcct4 0 1 specification of pin operation i/o port (pct1) wr1 output pmcct1 0 1 specification of pin operation i/o port (pct0) wr0 output pmcct0 0 1 specification of pin operation after reset: 00h r/w address: fffff04ah
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 136 of 1113 sep 22, 2011 4.3.10 port dh port dh is a 6-bit ( pd70f3737, 70f3738), or a 5-bit ( pd70f3792, 70f3793, 70f3 841, 70f3842) port for which i/o settings can be cont rolled in 1-bit units. port dh includes the following alternate-function pins. table 4-13. port dh alternate-function pins pin no. alternate function gf gc f1 function name name i/o remark block type 89 87 c6 pdh0 a16 output d-2 90 88 d6 pdh1 a17 output d-2 61 59 f9 pdh2 a18 output d-2 62 60 f8 pdh3 a19 output d-2 8 6 f4 pdh4 a20 output d-2 9 7 g4 pdh5 note a21 output ? d-2 note pd70f3737, pd70f3738 only caution when specifying the port or alternate function mode on a bit by bit basis, make sure that the address bus output functions normally. remark gf: 100-pin plastic lqfp (14 20) ( pd70f3737, 70f3738 only) gc: 100-pin plastic lqfp (fine pitch) (14 14) f1: 121-pin plastic fbga (8 8) (1) port dh register (pdh) outputs 0 outputs 1 pdhn 0 1 output data control (in output mode) (n = 0 to 5) pdh after reset: 00h (output latch) r/w address: fffff006h 0 0 pdh5 note pdh4 pdh3 pdh2 pdh1 pdh0 note pd70f3737, 70f3738 only
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 137 of 1113 sep 22, 2011 (2) port dh mode register (pmdh) 1 output mode input mode pmdhn 0 1 i/o mode control (n = 0 to 5) 1 pmdh5 note pmdh4 pmdh3 pmdh2 pmdh1 pmdh0 after reset: ffh r/w address: fffff026h pmdh note pd70f3737, 70f3738 only (3) port dh mode control register (pmcdh) i/o port (pdhn) ax output (address bus output) (x = 16 to 21) pmcdhn 0 1 specification of pin operation (n = 0 to 5) 00 pmcdh5 note pmcdh4 pmcdh3 pmcdh2 pmcdh1 pmcdh0 after reset: 00h r/w address: fffff046h pmcdh note pd70f3737, 70f3738 only caution when specifying the port or alternate function mode on a bit by bit basis, make sure that the address bus output functions normally.
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 138 of 1113 sep 22, 2011 4.3.11 port dl port dl is a 16-bit port for which i/o se ttings can be controll ed in 1-bit units. port dl includes the following alternate-function pins. table 4-14. port dl alternate-function pins pin no. alternate function gf gc f1 function name name i/o remark block type 73 71 c11 pdl0 ad0 i/o d-3 74 72 c10 pdl1 ad1 i/o d-3 75 73 c9 pdl2 ad2 i/o d-3 76 74 b11 pdl3 ad3 i/o d-3 77 75 b10 pdl4 ad4 i/o d-3 78 76 a10 pdl5 ad5/flmd1 note i/o d-3 79 77 a9 pdl6 ad6 i/o d-3 80 78 b9 pdl7 ad7 i/o d-3 81 79 a8 pdl8 ad8 i/o d-3 82 80 b8 pdl9 ad9 i/o d-3 83 81 c8 pdl10 ad10 i/o d-3 84 82 a7 pdl11 ad11 i/o d-3 85 83 b7 pdl12 ad12 i/o d-3 86 84 c7 pdl13 ad13 i/o d-3 87 85 d7 pdl14 ad14 i/o d-3 88 86 b6 pdl15 ad15 i/o ? d-3 note since this pin is set in the flash memory progra mming mode, it does not need to be manipulated by using the port control register. for details, see chapter 30 flash memory . remark gf: 100-pin plastic lqfp (14 20) ( pd70f3737, 70f3738 only) gc: 100-pin plastic lqfp (fine pitch) (14 14) f1: 121-pin plastic fbga (8 8)
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 139 of 1113 sep 22, 2011 (1) port dl register (pdl) pdl15 outputs 0 outputs 1 pdln 0 1 output data control (in output mode) (n = 0 to 15) pdl14 pdl13 pdl12 pdl11 pdl10 pdl9 pdl8 after reset: 0000h (output latch) r/w address: pdl fffff004h, pdll fffff004h, pdlh fffff005h pdl7 pdl6 pdl5 pdl4 pdl3 pdl2 pdl1 pdl0 8 9 10 11 12 13 14 15 pdl (pdlh) (pdll) remarks 1. the pdl register can be read or written in 16-bit units. however, when using the higher 8 bits of the pdl register as the pdlh register and the lower 8 bits as the pdll register, pdl can be read or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of the pdl register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pdlh register. (2) port dl mode register (pmdl) pmdl7 output mode input mode pmdln 0 1 i/o mode control (n = 0 to 15) pmdl6 pmdl5 pmdl4 pmdl3 pmdl2 pmdl1 pmdl0 after reset: ffffh r/w address: pmdl fffff024h, pmdll fffff024h, pmdlh fffff025h pmdl15 pmdl14 pmdl13 pmdl12 pmdl11 pmdl10 pmdl9 pmdl8 8 9 10 11 12 13 14 15 pmdl (pmdlh) (pmdll) remarks 1. the pmdl register can be read or written in 16-bit units. however, when using the higher 8 bits of the pmdl register as the pmdlh register and the lower 8 bits as the pmdll register, pmdl can be read or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of the pmdl register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pmdlh register.
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 140 of 1113 sep 22, 2011 (3) port dl mode control register (pmcdl) i/o port (pdln) adn i/o (address/data bus i/o) pmcdln 0 1 specification of pin operation (n = 0 to 15) pmcdl7 pmcdl6 pmcdl5 pmcdl4 pmcdl3 pmcdl2 pmcdl1 pmcdl0 after reset: 0000h r/w address: pmcdl fffff044h, pmcdll fffff044h, pmcdlh fffff045h pmcdl15 pmcdl14pmcdl13 pmcdl12 pmcdl11pmcdl10 pmcdl9 pmcdl8 8 9 10 11 12 13 14 15 pmcdl (pmcdlh) (pmcdll) cautions 1. when the smsel bit of the eximc register = 1 (separate mode) and the bs30 to bs00 bits of the bsc register = 0 (8-bit bus width), do not sp ecify the ad8 to ad15 pins. 2. when specifying th e port or adn i/o mode on a bit by bit basis, specify the mode in accordance with the external memory used. remarks 1. the pmcdl register can be read or written in 16-bit units. however, when using the higher 8 bits of the pmcdl register as the pmcdlh register and the lower 8 bits as the pmcdll register, pmcdl can be read or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of t he pmcdl register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pmcdlh register.
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 141 of 1113 sep 22, 2011 4.4 block diagrams figure 4-3. block diagram of type a-1 address rd a/d input signal wr pm pmmn wr port pmn pmn p-ch n-ch internal bus selector selector
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 142 of 1113 sep 22, 2011 figure 4-4. block diagram of type a-2 rd d/a output signal wr pm pmmn wr port pmn pmn p-ch n-ch internal bus selector selector address
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 143 of 1113 sep 22, 2011 figure 4-5. block diagram of type c-1 internal bus address selector selector rd wr port pmn wr pf pfmn wr pm pmmn pmn ev dd ev ss p-ch n-ch
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 144 of 1113 sep 22, 2011 figure 4-6. block diagram of type d-1 wr port pmn wr pm pmmn wr pmc pmcmn rd input signal when alternate function is used pmn internal bus selector selector address
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 145 of 1113 sep 22, 2011 figure 4-7. block diagram of type d-2 wr port pmn wr pm pmmn wr pmc pmcmn rd output signal when alternate function is used pmn internal bus selector selector selector address
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 146 of 1113 sep 22, 2011 figure 4-8. block diagram of type d-3 wr port pmn wr pm pmmn wr pmc pmcmn rd pmn output signal when alternate function is used input signal when alternate function is used output enable signal of address/data bus input enable signal of address/data bus output buffer off signal internal bus selector selector selector selector address
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 147 of 1113 sep 22, 2011 figure 4-9. block diagram of type e-3 rd wr port pmn wr pmc pmcmn wr pf pfmn wr pm pmmn pmn ev dd ev ss p-ch n-ch output signal when alternate function is used output enable signal when alternate function is used input signal when alternate function is used note internal bus selector selector selector address note there are no hysteresis characteristics in port mode.
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 148 of 1113 sep 22, 2011 figure 4-10. block diagram of type g-1 input signal when alternate function is used rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn output signal when alternate function is used pmn ev dd ev ss p-ch n-ch note internal bus selector selector selector address note there are no hysteresis characteristics in port mode.
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 149 of 1113 sep 22, 2011 figure 4-11. block diagram of type g-2 input signal when alternate function is used rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn output signal when alternate function is used pmn ev dd ev ss p-ch n-ch note internal bus selector selector selector address note there are no hysteresis characteristics in port mode.
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 150 of 1113 sep 22, 2011 figure 4-12. block diagram of type g-3 output signal 2 when alternate function is used rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn output signal 1 when alternate function is used pmn ev dd ev ss p-ch n-ch internal bus selector selector selector selector address
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 151 of 1113 sep 22, 2011 figure 4-13. block diagram of type g-5 rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn output signal 2 when alternate function is used output signal 1 when alternate function is used output enable signal when alternate function is used pmn ev dd ev ss p-ch n-ch input signal when alternate function is used note internal bus selector selector selector selector address note there are no hysteresis characteristics in port mode.
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 152 of 1113 sep 22, 2011 figure 4-14. block diagram of type g-6 output signal when alternate function is used input signal 1 when alternate function is used input signal 2 when alternate function is used note internal bus selector selector selector selector address rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn pmn ev dd ev ss p-ch n-ch note there are no hysteresis characteristics in port mode.
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 153 of 1113 sep 22, 2011 figure 4-15. block diagram of type g-12 input signal when alternate function is used output signal 1 when alternate function is used output signal 2 when alternate function is used note internal bus selector address rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn pmn ev dd ev ss p-ch n-ch selector selector selector note there are no hysteresis characteristics in port mode.
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 154 of 1113 sep 22, 2011 figure 4-16. block diagram of type l-1 input signal 1 when alternate function is used rd wr port pmn wr pmc pmcmn wr intr intrmn note 1 wr intf intfmn note 1 wr pf pfmn wr pm pmmn pmn ev dd ev ss p-ch n-ch edge detection noise elimination note 2 internal bus selector selector address notes 1. see 21.7 external interrupt request input pins (nmi and intp0 to intp7) . 2. there are no hysteresis characteristics in port mode.
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 155 of 1113 sep 22, 2011 figure 4-17. block diagram of type n-1 input signal 1 when alternate function is used rd wr port pmn wr pmc pmcmn wr intr intrmn note 1 wr intf intfmn note 1 wr pf pfmn wr pm wr pfc pfcmn pmmn pmn input signal 2 when alternate function is used ev dd ev ss p-ch n-ch edge detection noise elimination note 2 internal bus selector selector selector address notes 1. see 21.7 external interrupt request input pins (nmi and intp0 to intp7) . 2. there are no hysteresis characteristics in port mode.
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 156 of 1113 sep 22, 2011 figure 4-18. block diagram of type n-2 internal bus address input signal when alternate function is used selector selector selector rd wr port pmn wr pmc pmcmn wr intr intrmn note 1 wr intf intfmn note 1 wr pf pfmn wr pm wr pfc pfcmn pmmn pmn ev dd ev ss p-ch n-ch edge detection noise elimination note 2 output signal when alternate function is used notes 1. see 21.7 external interrupt request input pins (nmi and intp0 to intp7) . 2. there are no hysteresis characteristics in port mode.
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 157 of 1113 sep 22, 2011 figure 4-19. block diagram of type n-3 input signal 1-1 when alternate function is used input signal 1-2 when alternate function is used input signal 2 when alternate function is used rd wr port pmn wr pmc pmcmn wr intr intrmn note 1 wr intf intfmn note 1 wr pf pfmn wr pm wr pfc pfcmn pmmn pmn ev dd ev ss p-ch n-ch note 2 internal bus selector selector selector address edge detection noise elimination notes 1. see 21.7 external interrupt request input pins (nmi and intp0 to intp7) . 2. there are no hysteresis characteristics in port mode.
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 158 of 1113 sep 22, 2011 figure 4-20. block diagram of type u-1 rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn pmn ev dd ev ss p-ch n-ch wr pfce pfcemn input signal 2 when alternate function is used input signal 1 when alternate function is used input signal 3 when alternate function is used output signal 2 when alternate function is used output signal 1 when alternate function is used output enable signal whenalternate function is used note selector selector selector selector selector address internal bus note there are no hysteresis characteristics in port mode.
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 159 of 1113 sep 22, 2011 figure 4-21. block diagram of type u-5 input signal 1-1 when alternate function is used rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn input signal 1-2 when alternate function is used output signal 2 when alternate function is used output signal 1 when alternate function is used pmn ev dd ev ss p-ch n-ch wr pfce pfcemn note internal bus selector selector selector selector address noise elimination note there are no hysteresis characteristics in port mode.
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 160 of 1113 sep 22, 2011 figure 4-22. block diagram of type u-6 input signal 1-1 when alternate function is used rd wr port pmn wr pfc pfcmn wr pf pfmn wr ocdm0 ocdm0 wr pmc pmcmn wr pm pmmn input signal 1-2 when alternate function is used input signal when on-chip debugging pmn ev dd ev ss p-ch n-ch wr pfce pfcemn note internal bus selector selector selector selector address output signal 2 when alternate function is used output signal 1 when alternate function is used noise elimination note there are no hysteresis characteristics in port mode.
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 161 of 1113 sep 22, 2011 figure 4-23. block diagram of type u-7 input signal 1 when alternate function is used rd wr port pmn wr pfc pfcmn wr pf pfmn wr ocdm0 ocdm0 wr pmc pmcmn wr pm pmmn input signal 2-1 when alternate function is used input signal 2-2 when alternate function is used output signal when on-chip debugging pmn ev dd ev ss p-ch n-ch wr pfce pfcemn note internal bus selector selector selector selector selector selector address output signal 2 when alternate function is used output signal 1 when alternate function is used noise elimination note there are no hysteresis characteristics in port mode.
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 162 of 1113 sep 22, 2011 figure 4-24. block diagram of type u-8 input signal when alternate function is used rd wr port pmn wr pfc pfcmn wr pf pfmn wr ocdm0 ocdm0 wr pmc pmcmn wr pm pmmn input signal when on-chip debugging pmn ev dd ev ss p-ch n-ch wr pfce pfcemn note internal bus selector selector selector selector address output signal 2 when alternate function is used output signal 1 when alternate function is used noise elimination note there are no hysteresis characteristics in port mode.
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 163 of 1113 sep 22, 2011 figure 4-25. block diagram of type u-9 input signal 1 when alternate function is used rd wr port pmn wr pfc pfcmn wr pf pfmn wr ocdm0 ocdm0 wr pmc pmcmn wr pm pmmn input signal 2 when alternate function is used input signal when on-chip debugging output enable signal when alternate function is used pmn ev dd ev ss p-ch n-ch wr pfce pfcemn note internal bus selector selector selector selector selector address output signal 2 when alternate function is used output signal 1 when alternate function is used noise elimination note there are no hysteresis characteristics in port mode.
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 164 of 1113 sep 22, 2011 figure 4-26. block diagram of type u-10 internal bus address input signal 1 when alternate function is used selector selector selector selector rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn input signal 2 when alternate function is used output signal 2 when alternate function is used output signal 3 when alternate function is used output signal 1 when alternate function is used pmn ev dd ev ss p-ch n-ch wr pfce pfcemn noise elimination note selector note there are no hysteresis characteristics in port mode.
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 165 of 1113 sep 22, 2011 figure 4-27. block diagram of type u-11 internal bus address input signal 1 when alternate function is used selector selector selector selector rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn input signal 3 when alternate function is used output signal 2 when alternate function is used output signal 1 when alternate function is used pmn input signal 2 when alternate function is used ev dd ev ss p-ch n-ch wr pfce pfcemn noise elimination note selector note there are no hysteresis characteristics in port mode.
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 166 of 1113 sep 22, 2011 figure 4-28. block diagram of type u-12 input signal when alternate function is used rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn output signal 2 when alternate function is used output signal 1 when alternate function is used pmn ev dd ev ss p-ch n-ch wr pfce pfcemn note internal bus selector selector selector selector address note there are no hysteresis characteristics in port mode.
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 167 of 1113 sep 22, 2011 figure 4-29. block diagram of type u-13 input signal when alternate function is used rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn output signal 2 when alternate function is used output signal 1 when alternate function is used pmn ev dd ev ss p-ch n-ch wr pfce pfcemn note internal bus selector selector selector selector address note there are no hysteresis characteristics in port mode.
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 168 of 1113 sep 22, 2011 figure 4-30. block diagram of type u-14 input signal 1 when alternate function is used rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn input signal 2 when alternate function is used output signal 2 when alternate function is used output signal 1 when alternate function is used pmn ev dd ev ss p-ch n-ch wr pfce pfcemn note internal bus selector selector selector selector address selector note there are no hysteresis characteristics in port mode.
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 169 of 1113 sep 22, 2011 figure 4-31. block diagram of type u-15 input signal 1 when alternate function is used input signal 2 when alternate function is used rd wr port pmn wr pmc pmcmn wr intr intrmn note 1 wr intf intfmn note 1 wr pf pfmn wr pm wr pfc pfcmn wr pfce pfcemn pmmn pmn ev dd ev ss p-ch n-ch output signal 2 when alternate function is used output signal 1 when alternate function is used note 2 internal bus selector selector selector selector address edge detection noise elimination selector notes 1. see 21.7 external interrupt request input pins (nmi and intp0 to intp7) . 2. there are no hysteresis characteristics in port mode.
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 170 of 1113 sep 22, 2011 figure 4-32. block diagram of type u-16 internal bus address input signal when alternate function is used selector selector selector selector rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn output signal 2 when alternate function is used output signal 3 when alternate function is used output signal 1 when alternate function is used pmn ev dd ev ss p-ch n-ch wr pfce pfcemn note note there are no hysteresis characteristics in port mode.
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 171 of 1113 sep 22, 2011 figure 4-33. block diagram of type aa-1 rd wr port pmn wr intf intfmn note 1 wr pf pfmn wr ocdm0 ocdm0 wr pmc pmcmn wr pm pmmn pmn ev dd ev ss p-ch n-ch n-ch wr intr intrmn note 1 ev ss input signal when on-chip debugging external reset signal input signal when alternate function is used note 2 internal bus selector selector address edge detection noise elimination notes 1. see 21.7 external interrupt request input pins (nmi and intp0 to intp7) . 2. there are no hysteresis characteristics in port mode.
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 172 of 1113 sep 22, 2011 4.5 port register settings when alternate function is used table 4-15 shows the port register settings when each por t pin is used for an alternate function. when using a port pin as an alternate-function pin, refer to the description of each pin.
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 173 of 1113 sep 22, 2011 table 4-15. settings when pins are used for alternate functions (1/7) function name alternate function name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) p02 = setting not required p02 = setting not required p03 = setting not required p03 = setting not required p03 = setting not required p04 = setting not required p04 = setting not required p04 = setting not required p05 = setting not required p05 = setting not required p06 = setting not required p10 = setting not required p11 = setting not required p30 = setting not required p30 = setting not required p31 = setting not required p31 = setting not required p31 = setting not required p32 = setting not required p32 = setting not required p32 = setting not required p32 = setting not required p33 = setting not required p33 = setting not required p02 p03 p04 p05 p06 p10 p11 p30 p31 p32 p33 nmi a21 note1 intp0 adtrg rtc1hz note1 intp1 rtcdiv note1 rtccl note1 intp2 drst intp3 ano0 ano1 txda0 sob4 rxda0 intp7 sib4 ascka0 sckb4 tip00 top00 tip01 top01 input input input input input input output output input input input output output output output input input input input i/o input output input output ocdm0 (ocdm) = 1 pm02 = setting not required pm02 = setting not required pm03 = setting not required pm03 = setting not required pm03 = setting not required pm04 = setting not required pm04 = setting not required pm04 = setting not required pm05 = setting not required pm05 = setting not required pm06 = setting not required pm10 = 1 pm11 = 1 pm30 = setting not required pm30 = setting not required pm31 = setting not required pm31 = setting not required pm31 = setting not required pm32 = setting not required pm32 = setting not required pm32 = setting not required pm32 = setting not required pm33 = setting not required pm33 = setting not required ? ? ? ? ? ? ? ? ? ? ? ? ? ? pmc02 = 1 pmc02 = 1 pmc03 = 1 pmc03 = 1 pmc03 = 1 pmc04 = 1 pmc04 = 1 pmc04 = 1 pmc05 = 1 pmc05 = setting not required pmc06 = 1 pmc30 = 1 pmc30 = 1 pmc31 = 1 pmc31 = 1 pmc31 = 1 pmc32 = 1 pmc32 = 1 pmc32 = 1 pmc32 = 1 pmc33 = 1 pmc33 = 1 pfc02 = 0 pfc02 = 1 pfc03 = 0 pfc03 = 1 pfc03 = 1 pfc04 = 0 pfc04 = 1 pfc04 = 0 pfc30 = 0 pfc30 = 1 note2 , pfc31 = 0 note2 , pfc31 = 0 pfc31 = 1 pfc32 = 0 pfc32 = 1 pfc32 = 0 pfc32 = 1 pfc33 = 0 pfc33 = 1 ? ? ? ? ? ? ? pfce03 = 0 pfce03 = 0 pfce03 = 1 pfce04 = 0 pfce04 = 0 pfce04 = 1 pfce32 = 0 pfce32 = 0 pfce32 = 1 pfce32 = 1 notes 1. pd70f3792, 70f3793, 70f3841, 70f3842 only 2. intp7 and rxda0 are alternate functions. when using the pin for rxda0, disable edge detection for intp7 (clear the intf3.intf 31 bit and the intr3.intr31 bit to 0). when using the pin for intp7, stop uarta0 reception (clear the ua0ctl0.ua0rxe bit to 0). caution when using one of the p10/ano0 and p11/ano1 pins for the i/o port function and the other for d/a output (ano0, ano1), d o so in an application where the port i/o level does not change during d/a output.
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 174 of 1113 sep 22, 2011 table 4-15. settings when pins are used for alternate functions (2/7) function name alternate function name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? p34 p35 p36 p37 p38 p39 p40 p41 p42 p50 tip10 top10 tip11 top11 txda3 note rxda3 note txda2 sda00 rxda2 scl00 sib0 sda01 sob0 scl01 sckb0 tiq01 kr0 toq01 rtp00 p34 = setting not required p34 = setting not required p35 = setting not required p35 = setting not required p36 = setting not required p37 = setting not required p38 = setting not required p38 = setting not required p39 = setting not required p39 = setting not required p40 = setting not required p40 = setting not required p41 = setting not required p41 = setting not required p42 = setting not required p50 = setting not required p50 = setting not required p50 = setting not required p50 = setting not required pm34 = setting not required pm34 = setting not required pm35 = setting not required pm35 = setting not required pm36 = setting not required pm37 = setting not required pm38 = setting not required pm38 = setting not required pm39 = setting not required pm39 = setting not required pm40 = setting not required pm40 = setting not required pm41 = setting not required pm41 = setting not required pm42 = setting not required pm50 = setting not required pm50 = setting not required pm50 = setting not required pm50 = setting not required pmc34 = 1 pmc34 = 1 pmc35 = 1 pmc35 = 1 pmc36 = 1 pmc37 = 1 pmc38 = 1 pmc38 = 1 pmc39 = 1 pmc39 = 1 pmc40 = 1 pmc40 = 1 pmc41 = 1 pmc41 = 1 pmc42 = 1 pmc50 = 1 pmc50 = 1 pmc50 = 1 pmc50 = 1 pfc34 = 0 pfc34 = 1 pfc35 = 0 pfc35 = 1 pfc38 = 0 pfc38 = 1 pfc39 = 0 pfc39 = 1 pfc40 = 0 pfc40 = 1 pfc41 = 0 pfc41 = 1 pfc50 = 1 pfc50 = 1 pfc50 = 0 pfc50 = 1 input output input output outpt input output i/o input i/o input i/o output i/o i/o input input output output pfce50 = 0 pfce50 = 0 pfce50 = 1 pfce50 = 1 krm0 (krm) = 0 tq0tig2, tq0tig3 (tq0ioc1) = 0 pf38 (pf3) = 1 pf39 (pf3) = 1 pf40 (pf4) = 1 pf41 (pf4) = 1 ? note. pd70f3792, 70f3793, 70f3841, 70f3842 only
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 175 of 1113 sep 22, 2011 table 4-15. settings when pins are used for alternate functions (3/7) function name alternate function name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) input input output output input input output output input input input input output output output output input output input i/o input output input p51 p52 p53 p54 p55 tiq02 kr1 toq02 rtp01 tiq03 kr2 toq03 rtp02 ddi sib2 tiq00 kr3 toq00 rtp03 ddo sob2 kr4 rtp04 dck sckb2 kr5 rtp05 dms p51 = setting not required p51 = setting not required p51 = setting not required p51 = setting not required p52 = setting not required p52 = setting not required p52 = setting not required p52 = setting not required p52 = setting not required p53 = setting not required p53 = setting not required p53 = setting not required p53 = setting not required p53 = setting not required p53 = setting not required p54 = setting not required p54 = setting not required p54 = setting not required p54 = setting not required p55 = setting not required p55 = setting not required p55 = setting not required p55 = setting not required pm51 = setting not required pm51 = setting not required pm51 = setting not required pm51 = setting not required pm52 = setting not required pm52 = setting not required pm52 = setting not required pm52 = setting not required pm52 = setting not required pm53 = setting not required pm53 = setting not required pm53 = setting not required pm53 = setting not required pm53 = setting not required pm53 = setting not required pm54 = setting not required pm54 = setting not required pm54 = setting not required pm54 = setting not required pm55 = setting not required pm55 = setting not required pm55 = setting not required pm55 = setting not required pmc51 = 1 pmc51 = 1 pmc51 = 1 pmc51 = 1 pmc52 = 1 pmc52 = 1 pmc52 = 1 pmc52 = 1 pmc52 = setting not required pmc53 = 1 pmc53 = 1 pmc53 = 1 pmc53 = 1 pmc53 = 1 pmc53 = setting not required pmc54 = 1 pmc54 = 1 pmc54 = 1 pmc54 = setting not required pmc55 = 1 pmc55 = 1 pmc55 = 1 pmc55 = setting not required pfce51 = 0 pfce51 = 0 pfce51 = 1 pfce51 = 1 pfce52 = 0 pfce52 = 0 pfce52 = 1 pfce52 = 1 pfce52 = setting not required pfce53 = 0 pfce53 = 0 pfce53 = 0 pfce53 = 1 pfce53 = 1 pfce53 = setting not required pfce54 = 0 pfce54 = 0 pfce54 = 1 pfce54 = setting not required pfce55 = 0 pfce55 = 0 pfce55 = 1 pfce55 = setting not required pfc51 = 1 pfc51 = 1 pfc51 = 0 pfc51 = 1 pfc52 = 1 pfc52 = 1 pfc52 = 0 pfc52 = 1 pfc52 = setting not required pfc53 = 0 pfc53 = 1 pfc53 = 1 pfc53 = 0 pfc53 = 1 pfc53 = setting not required pfc54 = 0 pfc54 = 1 pfc54 = 1 pfc54 = setting not required pfc55 = 0 pfc55 = 1 pfc55 = 1 pfc55 = setting not required krm1 (krm) = 0 tq0tig4, tq0tig5 (tq0ioc1) = 0 krm2 (krm) = 0 tq0tig6, tq0tig7 (tq0i0c1) = 0 ocdm0 (ocdm) = 1 krm3 (krm) = 0 tq0tig0, tq0tig1 (tq0ioc1) = 0, tq0ees0, tq0ees1 (tq0ioc2) = 0, tq0ets0, tq0ets1 (tq0ioc2) = 0 ocdm0 (ocdm) = 1 ocdm0 (ocdm) = 1 ocdm0 (ocdm) = 1
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 176 of 1113 sep 22, 2011 table 4-15. settings when pins are used for alternate functions (4/7) function name alternate function name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) ? ? ? ? ? ? ? ? ? ? ? ? note 1 pf90 (pf9) = 1 note 1 pf91 (pf9) = 1 input input input input input input input input input input input input output input output i/o output input input i/o p70 p71 p72 p73 p74 p75 p76 p77 p78 p79 p710 p711 p90 p91 ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 ani8 ani9 ani10 ani11 a0 kr6 txda1 sda02 a1 kr7 rxda1/kr7 note 2 scl02 p70 = setting not required p71 = setting not required p72 = setting not required p73 = setting not required p74 = setting not required p75 = setting not required p76 = setting not required p77 = setting not required p78 = setting not required p79 = setting not required p710 = setting not required p711 = setting not required p90 = setting not required p90 = setting not required p90 = setting not required p90 = setting not required p91 = setting not required p91 = setting not required p91 = setting not required p91 = setting not required pm70 = 1 pm71 = 1 pm72 = 1 pm73 = 1 pm74 = 1 pm75 = 1 pm76 = 1 pm77 = 1 pm78 = 1 pm79 = 1 pm710 = 1 pm711 = 1 pm90 = setting not required pm90 = setting not required pm90 = setting not required pm90 = setting not required pm91 = setting not required pm91 = setting not required pm91 = setting not required pm91 = setting not required pmc90 = 1 pmc90 = 1 pmc90 = 1 pmc90 = 1 pmc91 = 1 pmc91 = 1 pmc91 = 1 pmc91 = 1 pfce90 = 0 pfce90 = 0 pfce90 = 1 pfce90 = 1 pfce91 = 0 pfce91 = 0 pfce91 = 1 pfce91 = 1 pfc90 = 0 pfc90 = 1 pfc90 = 0 pfc90 = 1 pfc91 = 0 pfc91 = 1 pfc91 = 0 pfc91 = 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? notes 1. when using the pin for the alternate function a0 to a15, set all 16 bits of the pmc9 register to ffffh at once. 2. the rxda1 and kr7 functions cannot be used at the same time. when using the pin for rxda1, do not use the kr7 function. when using the pin for kr7, do not use the rxda1 function. (it is recommended to set the pfc91 bit to 1 and clear the pfce91 bit to 0.)
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 177 of 1113 sep 22, 2011 table 4-15. settings when pins are used for alternate functions (5/7) function name alternate function name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) note1 note1 note1 note1 note1 note1 note1 note1 output input output output output input output input output input output output output input output input output input output output output input input input output output output output i/o p92 p93 p94 p95 p96 p97 p98 p99 a2 tip41 top41 txda4 note2 a3 tip40 top40 rxda4 note2 a4 tip31 top31 txda5 note2 a5 tip30 top30 rxda5 note2 a6 txdc0 note2 tip21 top21 a7 sib1 note3 rxdc0 notes2,3 tip20 top20 a8 sob1 a9 sckb1 p92 = setting not required p92 = setting not required p92 = setting not required p92 = setting not required p93 = setting not required p93 = setting not required p93 = setting not required p93 = setting not required p94 = setting not required p94 = setting not required p94 = setting not required p94 = setting not required p95 = setting not required p95 = setting not required p95 = setting not required p95 = setting not required p96 = setting not required p96 = setting not required p96 = setting not required p96 = setting not required p97 = setting not required p97 = setting not required p97 = setting not required p97 = setting not required p97 = setting not required p98 = setting not required p98 = setting not required p99 = setting not required p99 = setting not required pm92 = setting not required pm92 = setting not required pm92 = setting not required pm92 = setting not required pm93 = setting not required pm93 = setting not required pm93 = setting not required pm93 = setting not required pm94 = setting not required pm94 = setting not required pm94 = setting not required pm94 = setting not required pm95 = setting not required pm95 = setting not required pm95 = setting not required pm95 = setting not required pm96 = setting not required pm96 = setting not required pm96 = setting not required pm96 = setting not required pm97 = setting not required pm97 = setting not required pm97 = setting not required pm97 = setting not required pm97 = setting not required pm98 = setting not required pm98 = setting not required pm99 = setting not required pm99 = setting not required pmc92 = 1 pmc92 = 1 pmc92 = 1 pmc92 = 1 pmc93 = 1 pmc93 = 1 pmc93 = 1 pmc93 = 1 pmc94 = 1 pmc94 = 1 pmc94 = 1 pmc94 = 1 pmc95 = 1 pmc95 = 1 pmc95 = 1 pmc95 = 1 pmc96 = 1 pmc96 = 1 pmc96 = 1 pmc96 = 1 pmc97 = 1 pmc97 = 1 pmc97 = 1 pmc97 = 1 pmc97 = 1 pmc98 = 1 pmc98 = 1 pmc99 = 1 pmc99 = 1 pfce92 = 0 pfce92 = 0 pfce92 = 1 pfce92 = 1 pfce93 = 0 pfce93 = 0 pfce93 = 1 pfce93 = 1 pfce94 = 0 pfce94 = 0 pfce94 = 1 pfce94 = 1 pfce95 = 0 pfce95 = 0 pfce95 = 1 pfce95 = 1 pfce96 = 0 pfce96 = 0 pfce96 = 1 pfce96 = 1 pfce97 = 0 pfce97 = 0 pfce97 = 0 pfce97 = 1 pfce97 = 1 ? ? ? ? pfc92 = 0 pfc92 = 1 pfc92 = 0 pfc92 = 1 pfc93 = 0 pfc93 = 1 pfc93 = 0 pfc93 = 1 pfc94 = 0 pfc94 = 1 pfc94 = 0 pfc94 = 1 pfc95 = 0 pfc95 = 1 pfc95 = 0 pfc95 = 1 pfc96 = 0 pfc96 = 1 pfc96 = 0 pfc96 = 1 pfc97 = 0 pfc97 = 1 pfc97 = 1 pfc97 = 0 pfc97 = 1 pfc98 = 0 pfc98 = 1 pfc99 = 0 pfc99 = 1 notes 1. when using the pin for the alternate function a0 to a15, set all 16 bits of the pmc9 register to ffffh at once. 2. pd70f3792, 70f3793, 70f3841, 70f3842 only 3. the sib1 and rxdc0 functions cannot be used at the same time. when using the pin for sib1, stop uartc0 reception. (clear the uc0ctl0.uc0rxe bit to 0.) when using the pin for rxdc0, stop csib0 rec eption. (clear the cb1ctl0.cb1rxe bit to 0.)
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 178 of 1113 sep 22, 2011 table 4-15. settings when pins are used for alternate functions (6/7) function name alternate function name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) output input output output output i/o output input output input input output output input input output input output output input output output output output p910 p911 p912 p913 p914 p915 pcm0 pcm1 pcm2 pcm3 pct0 pct1 pct4 pct6 a10 sib3 a11 sob3 a12 sckb3 a13 intp4 a14 intp5 tip51 top51 a15 intp6 tip50 top50 wait clkout hldak hldrq wr0 wr1 rd astb p910 = setting not required p910 = setting not required p911 = setting not required p911 = setting not required p912 = setting not required p912 = setting not required p913 = setting not required p913 = setting not required p914 = setting not required p914 = setting not required p914 = setting not required p914 = setting not required p915 = setting not required p915 = setting not required p915 = setting not required p915 = setting not required pcm0 = setting not required pcm1 = setting not required pcm2 = setting not required pcm3 = setting not required pct0 = setting not required pct1 = setting not required pct4 = setting not required pct6 = setting not required pm910 = setting not required pm910 = setting not required pm911 = setting not required pm911 = setting not required pm912 = setting not required pm912 = setting not required pm913 = setting not required pm913 = setting not required pm914 = setting not required pm914 = setting not required pm914 = setting not required pm914 = setting not required pm915 = setting not required pm915 = setting not required pm915 = setting not required pm915 = setting not required pmcm0 = setting not required pmcm1 = setting not required pmcm2 = setting not required pmcm3 = setting not required pmct0 = setting not required pmct1 = setting not required pmct4 = setting not required pmct6 = setting not required pmc910 = 1 pmc910 = 1 pmc911 = 1 pmc911 = 1 pmc912 = 1 pmc912 = 1 pmc913 = 1 pmc913 = 1 pmc914 = 1 pmc914 = 1 pmc914 = 1 pmc914 = 1 pmc915 = 1 pmc915 = 1 pmc915 = 1 pmc915 = 1 pmccm0 = 1 pmccm1 = 1 pmccm2 = 1 pmccm3 = 1 pmcct0 = 1 pmcct1 = 1 pmcct4 = 1 pmcct6 = 1 pfce914 = 0 pfce914 = 0 pfce914 = 1 pfce914 = 1 pfce915 = 0 pfce915 = 0 pfce915 = 1 pfce915 = 1 pfc910 = 0 pfc910 = 1 pfc911 = 0 pfc911 = 1 pfc912 = 0 pfc912 = 1 pfc913 = 0 pfc913 = 1 pfc914 = 0 pfc914 = 1 pfc914 = 0 pfc914 = 1 pfc915 = 0 pfc915 = 1 pfc915 = 0 pfc915 = 1 note note note note note note ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? note when using the pin for the alternate function a0 to a15, set all 16 bits of the pmc9 register to ffffh at once.
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 179 of 1113 sep 22, 2011 table 4-15. settings when pins are used for alternate functions (7/7) function name alternate function name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? output output output output output output i/o i/o i/o i/o i/o i/o input i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o pdh0 pdh1 pdh2 pdh3 pdh4 pdh5 note1 pdl0 pdl1 pdl2 pdl3 pdl4 pdl5 pdl6 pdl7 pdl8 pdl9 pdl10 pdl11 pdl12 pdl13 pdl14 pdl15 a16 a17 a18 a19 a20 a21 ad0 ad1 ad2 ad3 ad4 ad5 flmd1 note2 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 pdh0 = setting not required pdh1 = setting not required pdh2 = setting not required pdh3 = setting not required pdh4 = setting not required pdh5 = setting not required pdl0 = setting not required pdl1 = setting not required pdl2 = setting not required pdl3 = setting not required pdl4 = setting not required pdl5 = setting not required pdl5 = setting not required pdl6 = setting not required pdl7 = setting not required pdl8 = setting not required pdl9 = setting not required pdl10 = setting not required pdl11 = setting not required pdl12 = setting not required pdl13 = setting not required pdl14 = setting not required pdl15 = setting not required pmdh0 = setting not required pmdh1 = setting not required pmdh2 = setting not required pmdh3 = setting not required pmdh4 = setting not required pmdh5 = setting not required pmdl0 = setting not required pmdl1 = setting not required pmdl2 = setting not required pmdl3 = setting not required pmdl4 = setting not required pmdl5 = setting not required pmdl5 = setting not required pmdl6 = setting not required pmdl7 = setting not required pmdl8 = setting not required pmdl9 = setting not required pmdl10 = setting not required pmdl11 = setting not required pmdl12 = setting not required pmdl13 = setting not required pmdl14 = setting not required pmdl15 = setting not required pmcdh0 = 1 pmcdh1 = 1 pmcdh2 = 1 pmcdh3 = 1 pmcdh4 = 1 pmcdh5 = 1 pmcdl0 = 1 pmcdl1 = 1 pmcdl2 = 1 pmcdl3 = 1 pmcdl4 = 1 pmcdl5 = 1 pmcdl5 = setting not required pmcdl6 = 1 pmcdl7 = 1 pmcdl8 = 1 pmcdl9 = 1 pmcdl10 = 1 pmcdl11 = 1 pmcdl12 = 1 pmcdl13 = 1 pmcdl14 = 1 pmcdl15 = 1 notes 1. pd70f3737, 70f3738, 70f3841, 70f3842 only 2. since this pin is set in the flash memory programming mode, it does not need to be manipulated by using the port control regist er. for details, see chapter 32, chapter 33, chapter 34 .
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 180 of 1113 sep 22, 2011 4.6 cautions 4.6.1 cautions on setting port pins (1) in the v850es/jg3-l, general-purpose port pins are sh ared with several peripheral i/o functions. to switch between using a pin as a general-purpose port pin (port mode) and as a peripheral function i/o pin (alternate-function mode), use the pmcn register. note the follo wing when setting this register. (a) cautions when switching from port mode to alternate-function mode switch from the port mode to the alter nate-function mode in the following order: <1> set the pfn register note 1 : n-ch open-drain setting <2> set the pfcn and pfcen regist ers: alternate-function selection <3> set the corresponding bit of the pmcn regist er to 1: switch to alternate-function mode <4> set the intrn and intfn registers note 2 : external interrupt setting note that if the pmcn register is set first, an unex pected operation may occur at the moment the register is set or when the pin states change in accord ance with the setting of the pfn, pfcn, and pfcen registers. a specific example is shown below. notes 1. n-ch open-drain output pin only. 2. only when the external in terrupt function is selected. caution regardless of the port mode/alternate-function mode setting, the pn register is read and written as follows: ? pn register read: the port output latch va lue is read (when pmn.pmnm bit = 0), or the pin state is read (pmn.pmnm bit = 1). ? pn register write: the port output latch is written [example] scl01 pin setting example the scl01 pin is used alternately as the p41/so b0 pin. select the desired pin function by using the pmc4, pfc4, and pf4 registers. pmc41 bit pfc41 bit pf41 bit pin function 0 don?t care 1 p41 (in output port mode, n-ch open-drain output) 0 1 sob0 output (n-ch open-drain output) 1 1 1 scl01 i/o (n-ch open-drain output)
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 181 of 1113 sep 22, 2011 the setting order that may cause a malfunction when switching from the p41 pin function to the scl01 pin function is shown below. setting order setting pin state pin level <1> initial value (pmc41 bit = 0, pfc41 bit = 0, pf41 bit = 0) port mode (input) hi-z <2> pmc41 bit 1 sob0 output low level (may be high level depending on the csib0 setting) <3> pfc41 bit 1 scl01 i/o high level (cmos output) <4> pf41 bit 1 scl01 i/o hi-z (n-ch open-drain output) in <2>, i 2 c communication may be affected since the al ternate-function sob0 output is output to the pin. in the cmos output period of <2> or <3>, an unnecessary current may be generated. (b) cautions on alternate-function mode (input) the signal input to the alternate-function block is low level when the pmcn.pmcnm bit is 0 due to the anded output of the pmcn register set value and the pin level. thus, depending on the port setting and alternate-function operation enable timing, an unexpected operation may occur. therefore, switch between the port mode and alternate-function mode in the following sequence. ? switching from port mode to alternate-function mode (input) set the pins to the alternate-function mode using the pmcn register and then enable the alternate-function operation. ? switching from alternate-function mode (input) to port mode stop the alternate-function operation and then switch the pins to the port mode. specific examples are shown below. [example 1] switching from general-purpose port pin (p02) to external interrupt pin (nmi) when the p02/nmi pin is pulled up as shown in figure 4-33 and the rising edge is specified by the nmi pin edge detection setting, even though a high level is input continuously to the nmi pin while switching from the p02 pin to the nmi pin (pmc02 bit = 0 1), this is detected as a rising edge, as if the low leve l changed to a high level, and an nmi interrupt occurs. to avoid this, set the nmi pin?s valid edge after switching from the p02 pin to the nmi pin.
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 182 of 1113 sep 22, 2011 figure 4-34. example of switching from p02 to nmi (incorrect) pmc0 nmi interrupt occurrence 76543 2 p02/nmi 3 v 10 0 10 00 pmc0m bit = 0: port mode pmc0m bit = 1: alternate-function mode rising edge detector pmc02 bit = 0: low level pmc02 bit = 1: high level remark m = 2 to 6 [example 2] switching from external pin (nmi) to general-purpose port pin (p02) when the p02/nmi pin is pulled up as shown in figure 4-34 and the falling edge is specified by the nmi pin edge detection setting, even though a high level is input continuously to the nmi pin when switching fr om the nmi pin to the p02 pin (pmc02 bit = 1 0), this is detected as a falling edge, as if the high level changed to a low level, and an nmi interrupt occurs. to avoid this, set the nmi pin edge detection as ?no edge detected? before switching to the p02 pin. figure 4-35. example of switching from nmi to p02 (incorrect) pmc0 76543 2 p02/nmi 3 v 10 nmi interrupt occurrence 1 0 pmc0m bit = 0: port mode pmc0m bit = 1: alternate-function mode falling edge detector pmc02 bit = 1: high level pmc02 bit = 0: low level 0 00 remark m = 2 to 6 (2) in port mode, the pfn.pfnm bit is valid only in the output mode (pmn.pmnm bit = 0). in the input mode (pmnm bit = 1), the value of the pfnm bit is not reflected in the buffer.
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 183 of 1113 sep 22, 2011 4.6.2 cautions on bit manipulation instruction for port n register (pn) when a 1-bit manipulation instruction is executed on a por t that provides both input and output functions or port/alternate functions, the value of t he output latch of an input port that is not subject to manipulation may be written in addition to the targeted bit. therefore, it is recommended to rewr ite the output latch when switching a port from input mode to output mode. when the p90 pin is an output pin, the p91 to p 97 pins are input pins (the st atus of all pins is high level), and the value of the port latch is 00h, if the output of the p90 pin is changed from low level to high level via a bit manipulation instruct ion, the value of the port latch is ffh. explanation: when writing to and reading from the pn register of a port whose pmnm bit is 1, the output latch is written and the pin status is read. a bit manipulation instruction is executed in the following order in the v850es/jg3-l. <1> the pn register is read in 8-bit units. <2> the targeted bit is manipulated. <3> the pn register is written in 8-bit units. in step <1>, the value of the output latch (0) of t he p90 pin, which is an out put pin, is read, while the pin statuses of the p91 to p 97 pins, which are input pins, are re ad. if the pin statuses of the p91 to p97 pins are high level at this time, the value read is feh. the value is changed to ffh by the manipulation in <2>. ffh is written to the output la tch by the manipulation in <3>. figure 4-36. bit manipula tion instruction (p90 pin) low-level output bit manipulation instruction (set1 0, p9l[r0]) is executed for p90 bit. pin status: high level p90 p91 to p97 port 9l latch 00000000 high-level output pin status: high level p90 p91 to p97 port 9l latch 11111111 bit manipulation instruction for p90 bit <1> the p9l register is read in 8-bit units. ? in the case of p90, an output pin, the value of the port latch (0) is read. ? in the case of p91 to p97, input pins, the pin status (1) is read. <2> set (1) to the p90 bit. <3> write the results of <2> to the output latch of the p9l register in 8-bit units.
v850es/jg3-l chapter 4 port functions r01uh0165ej0700 rev.7.00 page 184 of 1113 sep 22, 2011 4.6.3 cautions on on-chip debug pins the drst, dck, dms, ddi, and ddo pins are on-chip debug pins. after reset by the reset pin, the p05 /intp2/drst pin is initialized to func tion as an on-chip debug pin (drst). if a high level is input to the drst pin at this time, the on-chip debug mode is set, and the dck, dms, ddi, and ddo pins can be used. the following action must be taken if on-chip debugging is not used. ? clear the ocdm0 bit of the ocdm register (special register) (0) at this time, fix the p05/intp2/drst pin to low level from when reset by the reset pin is released until the above action is taken. if a high level is input to the drst pin before the abov e action is taken, it may cause a malfunction (cpu deadlock). handle the p05 pin with the utmost care. caution after reset by the wdt2res signal, clock m onitor (clm), or low-voltage detector (lvi), the p05/intp2/drst pin is not initialized to function as an on-chip debug pin (drst). the ocdm register holds the current value. 4.6.4 cautions on p05/intp2/drst pin the p05/intp2/drst pin has an internal pull-down resistor (30 k typ.). after a reset by the reset pin, the pull-down resistor is connected. the pull-down resistor is disconnected when the ocdm0 bit is cleared (0). 4.6.5 cautions on p10, p11, and p53 pins when power is turned on when the power is turned on, the following pins may ou tput an undefined level temporarily even during reset. ? p10/ano0 pin ? p11/ano1 pin ? p53/sib2/kr3/tiq00/toq00/rtp03/ddo pin 4.6.6 hysteresis characteristics in port mode, the following port pins do not have hysteresis characteristics. p02 to p06 p31 to p35, p37 to p39 p40 to p42 p50 to p55 p90 to p97, p99, p910, p912 to p915
v850es/jg3-l chapter 5 bus control function r01uh0165ej0700 rev.7.00 page 185 of 1113 sep 22, 2011 chapter 5 bus control function the external bus interface function is used to connect extern al devices to areas other t han the internal rom, ram, or on-chip i/o registers via ports 9, cm, ct, dl, and dh . these ports control ad dress/data i/o, the read/write strobe signal, waits, the clock output, bus hold, and the address strobe signal. the v850es/jg3-l is provided with an ex ternal bus interface function by which external memories such as rom and ram, and external i/o dev ices can be connected. 5.1 features { output can be selected from a mu ltiplexed bus with a minimum of 3 bus cycles and a separate bus with a minimum of 2 bus cycles ( pd70f3737, 70f3738, 70f3792, 70f3793). { a multiplexed bus with a minimum of 3 bus cycles and a separate bus output are available ( pd70f3841, 70f3842). { an 8-bit or 16-bit data bus can be selected (specifiable for each memory block). { wait function ? programmable wait function of up to 7 st ates (specifiable for each memory block) ? external wait function using wait pin { idle state insertion function ? a low-speed device can be connected by in serting an idle state after a read cycle. { bus hold function { misalign access is possible. { up to 4 mb of physical memory can be connected.
v850es/jg3-l chapter 5 bus control function r01uh0165ej0700 rev.7.00 page 186 of 1113 sep 22, 2011 5.2 bus control pins the following signals can be used to control an external device in each bus mode. when use a separate bus in pd70f3841 and pd70f3842, refer to table 5-1 . table 5-1. bus control signals (w hen multiplexed bus is selected) bus control signal i/o function alternate function r egister to switch between port mode/alternate-function mode ad0 to ad15 i/o address/data bus pdl0 to pdl15 pmcdl register a0 to a15 note1 output address bus (capable of separate output) p90 to p915 pmc9 register a16 to a21 output address bus pdh0 to pdh4, pdh5 note2 , p02 note3 pmcdh register, pmc0 register note3 wait input external wait control pcm0 pmccm register clkout output internal system clock output pcm1 pmccm register wr0, wr1 output write strobe signal pct0, pct1 pmcct register rd output read strobe signal pct4 pmcct register astb output address strobe signal pct6 pmcct register hldrq input pcm3 hldak output bus hold control pcm2 pmccm register notes 1. pd70f3841, 70f3842 only 2. pd70f3737, 70f3738 only 3. pd70f3792, 70f3793, 70f 3841, 70f3842 only table 5-2. bus control signals (w hen separate bus is selected) ( pd70f3737, 70f3738, 70f3792, 70f3793) bus control signal i/o function alternate function r egister to switch between port mode/alternate-function mode ad0 to ad15 i/o data bus pdl0 to pdl15 pmcdl register a0 to a15 output address bu s p90 to p915 pmc9 register a16 to a21 output address bus pdh0 to pdh4, pdh5 note1 , p02 note2 pmcdh register, pmc0 register note2 wait input external wait control pcm0 pmccm register clkout output internal system clock output pcm1 pmccm register wr0, wr1 output write strobe signal pct0, pct1 pmcct register rd output read strobe signal pct4 pmcct register hldrq input pcm3 hldak output bus hold control pcm2 pmccm register notes 1. pd70f3737, 70f3738 only 2. pd70f3792, 70f3793 only
v850es/jg3-l chapter 5 bus control function r01uh0165ej0700 rev.7.00 page 187 of 1113 sep 22, 2011 5.2.1 pin status when internal rom, internal ram , on-chip peripheral i/o , or expanded internal ram is accessed when the internal rom, internal ram, on-chip peripheral i/o or expanded intern al ram is accessed, the status of each pin is as follows. when use a separate bus in pd70f3841 and pd70f3842, refer to the case of multiplexed bus mode. table 5-3. pin statuses when intern al rom, internal ram, on-chip peri pheral i/o, or expanded internal ram is accessed separate bus mode multiplexed bus mode bus control pin internal rom/ram internal peripheral i/o internal rom/ram internal peripheral i/o expanded internal ram note address/data bus (ad15 to ad0) hi-z hi-z undefined undefined undefined address bus (a21 to a16) low level undefined low level undefined undefined address bus (a15 to a0) undefined undefined undefined undefined undefined control signal inactive inactive inactive inactive inactive note pd70f3841, 70f3842 only caution when the internal rom area is written, address, data, and control signals are activated in the same way as when the external memory area is written. 5.2.2 pin status in each operation mode for the status of the v850es/jg3-l pins in each operation mode, see 2.2 pin states .
v850es/jg3-l chapter 5 bus control function r01uh0165ej0700 rev.7.00 page 188 of 1113 sep 22, 2011 5.3 memory block function the lower 16 mb of the 64 mb memory space is reserv ed for external memory expansion and is divided into memory blocks of 2 mb, 2 mb, 4 mb, and 8 mb. the bus width and programmable wait function can be independently specified for each block. figure 5-1. data memory map: physical addresses ( pd70f3737, 70f3738, 70f3792, 70f3793) (64 kb) use prohibited memory block 3 (8 mb) internal rom area note 2 (1 mb) external memory area note 1 (1 mb) internal ram area (60 kb) on-chip peripheral i/o area (4 kb) memory block 2 (4 mb) memory block 1 (2 mb) memory block 0 (2 mb) 03ffffffh 03ff0000h 03feffffh 01000000h 00ffffffh 00800000h 007fffffh 00400000h 003fffffh 00200000h 001fffffh 00000000h 03ffffffh 03fff000h 03ffefffh 001fffffh 00100000h 000fffffh 00000000h 03ff0000h external memory area note 1 notes 1. the v850es/jg3-l has 22 address pins, so the exte rnal memory area appears as a repeated 4 mb image. 2. when the internal rom area is read, the data in the internal rom is read. when the area is written, a bus cycle occurs.
v850es/jg3-l chapter 5 bus control function r01uh0165ej0700 rev.7.00 page 189 of 1113 sep 22, 2011 figure 5-2. data memory map: physical addresses ( pd70f3841, 70f3842) (64 kb) use prohibited memory block 3 (8 mb) internal rom area note 2 (1 mb) external memory area note 1 (1 mb) internal ram area (60 kb) on-chip peripheral i/o area (4 kb) memory block 2 (4 mb) memory block 1 (2 mb) memory block 0 (2 mb) 03ffffffh 03ff0000h 03feffffh 01000000h 00ffffffh 00800000h 007fffffh 00400000h 003fffffh 00200000h 001fffffh 00000000h 03ffffffh 03fff000h 03ffefffh 001fffffh 00100000h 000fffffh 00000000h 003fffffh 003fa000h 003f9fffh 00200000h 03ff0000h external memory area note 1 expanded internal ram area(24 kb) use prohibited notes 1. the v850es/jg3-l has 22 address pins, so the exte rnal memory area appears as a repeated 4 mb image. 2. when the internal rom area is read, the data in the internal rom is read. when the area is written, a bus cycle occurs.
v850es/jg3-l chapter 5 bus control function r01uh0165ej0700 rev.7.00 page 190 of 1113 sep 22, 2011 5.4 external bus interface mode control function the pd70f3737, 70f3738, 70f3792, and 70f 3793 include the following two external bus interface modes. ? multiplexed bus mode ? separate bus mode these two modes can be selected by using the eximc register in pd70f3737, 70f373 8, 70f3792, and 70f3793. in pd70f3841 and pd70f3842, the mode is fixed to multiplex ed bus mode but separate bus is available with using address bus (a0 to a15). in this case, eximc register is not supported. (1) external bus interface mode control register (eximc) ( pd70f3737, 70f3738, 70f3 792, 70f3793 only) the eximc register selects the multip lexed bus mode or separate bus mode. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 multiplexed bus mode separate bus mode smsel 0 1 mode selection eximc 0 0 0 0 0 0 smsel after reset: 00h r/w address: ffffffbeh caution set the eximc register from the internal rom or internal ram area before executing an external access. after setting the eximc register, be sure to insert a nop instruction.
v850es/jg3-l chapter 5 bus control function r01uh0165ej0700 rev.7.00 page 191 of 1113 sep 22, 2011 5.5 bus access 5.5.1 number of clock cycles required for access the following table shows the number of basic cl ock cycles required for accessing each resource. table 5-4. number of clock cycles required for access area (bus width) bus cycle type internal rom (32 bits) internal ram (32 bits) expanded internal ram (16 bits) external memory (16 bits) on-chip peripheral i/o (16 bits) instruction fetch (normal access) 1 1 note 1 4 note 5 3 + n + i notes 2, 3 ? instruction fetch (branch) 2 2 note 1 4 note 5 3+ n + i notes 2, 3 ? operand data access 3 1 4 note 5 3 +n + i notes 2, 3 3 note 4 dma transfer ? 2 4 note 5 3 +n + i notes 2, 3 3 note 4 notes 1. if the access conflicts with a data access, the number of clock is increased by 1. 2. value when the multiplexed bus is selected. 2 + n + i clocks (n: number of wait states) when the separate bus mode is selected. 3. i = idle state 4. this value varies depending on the setting of the vswc register. 5. expanded internal ram is connected to external bus interface. this value includ e 1 data wait specified by dwc0 register ( pd70f3841, 70f3842). remark unit: clock cycles/access
v850es/jg3-l chapter 5 bus control function r01uh0165ej0700 rev.7.00 page 192 of 1113 sep 22, 2011 5.5.2 bus size setting function the external memory area of the v850es/jg 3-l is selected by memory blocks 0 to 3. the bus size of each external memory area selected by memo ry block n can be set (to 8 bits or 16 bits) by using the bsc register. if a 16-bit bus width is specified, the lower 8 bits are used for even addresses and the higher 8 bits are used for odd addresses. (1) bus size configuration register (bsc) this register controls the bus wid th of the memory block space. this register can be read or written in 16-bit units. reset sets this register to 5555h. caution write to the bsc register after reset, and then do not change the set values. also, do not access an external memory area until the initial settings of the bsc register are complete. after reset: 5555h r/w address: fffff066h 0 0 bsn0 0 1 8 bits 16 bits note2 bsc 1 bs30 0 0 1 bs20 0 0 1 bs10 note1 0 0 1 bs00 8 9 10 11 12 13 data bus width of memory block n space (n = 0 to 3) 14 15 1 2 3 4 5 6 7 0 memory block 0 memory block 3 memory block n signal memory block 2 memory block 1 notes1. the bs10 bit is used to specify the bus size for the expanded internal ram area. when using the expanded internal ram area, set this bit to 1 (which spec ifies bus size is 16 bit). 2. if a 16-bit bus width is specifi ed, writing can be controlled in 8-bit units via two control pins (wr0 and wr1) but reading can be controlled only in 16-bit units because reading is controlled via one control pin (rd). in the v850 es/jg3-l, however, unnecessary data is ignored, so byte access is possible. caution be sure to set bits 14, 12, 10, and 8 to ?1?, and clear bits 15, 13, 11, 9, 7, 5, 3, and 1 to ?0?.
v850es/jg3-l chapter 5 bus control function r01uh0165ej0700 rev.7.00 page 193 of 1113 sep 22, 2011 5.5.3 access according to bus size the v850es/jg3-l accesses the on-chip peripheral i/o and external memory in 8-bit, 16-bit, or 32-bit units. the bus size is as follows. ? the bus size of the on-chip peripheral i/o is fixed to 16 bits. ? the bus size of the external memory is selectable from 8 bits or 16 bits (by using the bsc register). the operation when each of the above is accessed is described below. all data is accessed starting from the lower side. the v850es/jg3-l supports only the little endian format. figure 5-3. little endian address in word data 000bh 000ah 0009h 0008h 0007h 0006h 0005h 0004h 0003h 0002h 0001h 0000h 31 24 23 16 15 8 7 0 (1) data space the v850es/jg3-l has an a ddress misalign function. with this function, data can be placed at all addresses, regardless of the format of the data (word data or halfword data). however, if the word data or halfwor d data is not aligned at the boundary, redundant bus cycles are generated, causing the bus efficiency to drop. examples of an 8-bit, 16-bit, and 32-bit access are shown below.
v850es/jg3-l chapter 5 bus control function r01uh0165ej0700 rev.7.00 page 194 of 1113 sep 22, 2011 (2) byte access (8 bits) (a) 16-bit data bus width 8-bit data is transmitted/received via a 16-bit bus. ther efore, if an even address is specified, the lower byte of the external data bus addre ss is accessed. if an odd address is s pecified, the hig her byte of the external data bus address is accessed. <1> access to even address (2n) <2> access to odd address (2n + 1) 7 0 7 0 byte data 15 8 external data bus 2n address 7 0 7 0 15 8 2n + 1 address byte data external data bus (b) 8-bit data bus width 8-bit data is transmitted/received via an 8-bit bus. therefore, the s pecified even/odd address of the external data bus is accessed. <1> access to even address (2n) <2> access to odd address (2n + 1) 7 0 7 0 2n address byte data external data bus 7 0 7 0 2n + 1 address byte data external data bus
v850es/jg3-l chapter 5 bus control function r01uh0165ej0700 rev.7.00 page 195 of 1113 sep 22, 2011 (3) halfword access (16 bits) (a) 16-bit data bus width 16-bit data is transmitted/received via a 16-bit bus. t herefore, if an even address is specified, the lower and higher bytes of the external data bus address are accessed at the same time. if an odd address is specified, the lower byte of the data is transmitted/received to/fr om an odd address via the higher byte of the external data bus address in the first access. in the second access, the high er byte of the data is transmitted/received to/from an odd address via the lowe r byte of the external data bus address. <1> access to even address (2n) <2> access to odd address (2n + 1) first access second access 7 0 7 0 15 8 2n address 15 8 2n + 1 halfword data external data bus 7 0 7 0 15 8 15 8 7 0 7 0 15 8 15 8 2n + 2 2n address address 2n + 1 halfword data external data bus halfword data external data bus (b) 8-bit data bus width 16-bit data is transmitted/received via an 8-bit bus. therefore, the data is tr ansmitted/received in two accesses. the lower/higher byte of the data is transmitted/received to/from the corresponding lower/higher byte of the external bus address. <1> access to even address (2n) <2> access to odd address (2n + 1) first access second access first access second access 7 0 7 0 15 8 address 7 0 7 0 15 8 2n + 1 address 2n halfword data external data bus halfword data external data bus 7 0 7 0 15 8 7 0 7 0 15 8 2n + 2 2n + 1 address address halfword data external data bus halfword data external data bus
v850es/jg3-l chapter 5 bus control function r01uh0165ej0700 rev.7.00 page 196 of 1113 sep 22, 2011 (4) word access (32 bits) (a) 16-bit data bus width (1/2) 32-bit data is transmitted/received via a 16-bit bus. t herefore, if an even address is specified, the data is transmitted/received in two accesses in 16-bit units. if an odd address is specified, the lower quarter-word data is transmitted/received to/from the higher byte (first access), the middle halfword data is transmitted/received to/from the middle bytes (second access), and the upper quarter-word data is transmitted/received to/from the lower byte (third access), of the external data bus address. <1> access to address (4n) first access second access 7 0 7 0 15 8 4n 15 8 4n + 1 23 16 31 24 7 0 7 0 15 8 4n + 2 15 8 4n + 3 23 16 31 24 word data external data bus address word data external data bus address <2> access to address (4n + 1) first access second access third access 7 0 7 0 15 8 15 8 4n + 1 23 16 31 24 7 0 7 0 15 8 4n + 2 15 8 4n + 3 23 16 31 24 7 0 7 0 15 8 4n + 4 15 8 23 16 31 24 address address address word data external data bus word data external data bus word data external data bus
v850es/jg3-l chapter 5 bus control function r01uh0165ej0700 rev.7.00 page 197 of 1113 sep 22, 2011 (a) 16-bit data bus width (2/2) <3> access to address (4n + 2) first access second access 7 0 7 0 15 8 4n + 2 15 8 4n + 3 23 16 31 24 7 0 7 0 15 8 4n + 4 15 8 4n + 5 23 16 31 24 address address word data external data bus word data external data bus <4> access to address (4n + 3) first access second access third access 7 0 7 0 15 8 15 8 4n + 3 23 16 31 24 7 0 7 0 15 8 4n + 4 15 8 4n + 5 23 16 31 24 7 0 7 0 15 8 4n + 6 15 8 23 16 31 24 address address address word data external data bus word data external data bus word data external data bus
v850es/jg3-l chapter 5 bus control function r01uh0165ej0700 rev.7.00 page 198 of 1113 sep 22, 2011 (b) 8-bit data bus width (1/2) 32-bit data is transmitted/received via an 8-bit bus. t herefore, the data is trans mitted/received in four accesses. the data is transmitted/received to/from the specified even/odd address of the external data bus. <1> access to address (4n) first access second access third access fourth access 7 0 7 0 15 8 4n 23 16 31 24 7 0 7 0 4n + 1 15 8 23 16 31 24 7 0 7 0 4n + 2 15 8 23 16 31 24 7 0 7 0 4n + 3 15 8 23 16 31 24 word data external data bus address address address address word data external data bus word data external data bus word data external data bus <2> access to address (4n + 1) first access second access third access fourth access 7 0 7 0 15 8 4n + 1 23 16 31 24 7 0 7 0 4n + 2 15 8 23 16 31 24 7 0 7 0 4n + 3 15 8 23 16 31 24 7 0 7 0 4n + 4 15 8 23 16 31 24 address address address address word data external data bus word data external data bus word data external data bus word data external data bus
v850es/jg3-l chapter 5 bus control function r01uh0165ej0700 rev.7.00 page 199 of 1113 sep 22, 2011 (b) 8-bit data bus width (2/2) <3> access to address (4n + 2) first access second access third access fourth access address address address address 7 0 7 0 15 8 4n + 2 23 16 31 24 7 0 7 0 4n + 3 15 8 23 16 31 24 7 0 7 0 4n + 4 15 8 23 16 31 24 7 0 7 0 4n + 5 15 8 23 16 31 24 word data external data bus word data external data bus word data external data bus word data external data bus <4> access to address (4n + 3) first access second access third access fourth access 7 0 7 0 15 8 4n + 3 23 16 31 24 7 0 7 0 4n + 4 15 8 23 16 31 24 7 0 7 0 4n + 5 15 8 23 16 31 24 7 0 7 0 4n + 6 15 8 23 16 31 24 address address address address word data external data bus word data external data bus word data external data bus word data external data bus
v850es/jg3-l chapter 5 bus control function r01uh0165ej0700 rev.7.00 page 200 of 1113 sep 22, 2011 5.6 wait function 5.6.1 programmable wait function (1) data wait control register 0 (dwc0) to realize interfacing with a low-s peed memory or i/o device, up to seven data wait stat es can be inserted in the bus cycle that is executed for each memory block space. the number of wait states can be pr ogrammed by using the dw c0 register. immediately after system reset, 7 data wait states are inserted fo r all the memory block areas. the dwc0 register can be read or written in 16-bit units. reset sets this register to 7777h. cautions 1. the internal rom and internal ram ar eas are not subject to programmable wait, and are always accessed without a wait state. the on-chip peripheral i/o area is also not subject to programmable wait, and only wait control from each peripheral function is performed. 2. write to the dwc0 register after reset, and then do not change the set values. also, when changing the initial values of the dwc0 register, do not access an external memory area until the settings are complete. after reset: 7777h r/w address: fffff484h 0 0 dwn2 0 0 0 0 1 1 1 1 dwn1 0 0 1 1 0 0 1 1 dwn0 0 1 0 1 0 1 0 1 none 1 2 3 4 5 6 7 dwc0 dw32 dw12 note dw31 dw11 note dw30 dw10 note 0 0 dw22 dw02 dw21 dw01 dw20 dw00 8 9 10 11 12 13 number of wait states inserted in memory block n space (n = 0 to 3) 14 15 1 2 3 4 5 6 7 0 memory block 0 memory block 3 memory block n signal memory block n signal memory block 2 memory block 1 note the dw12 to dw10 bits are used to specify whether to insert access wait states for the expand ed internal ram area. when using the expanded internal ram area, set these bits to 001 (which specifies inserting 1 wait state). ( pd70f3841, 70f3842) caution be sure to clear bits 15, 11, 7, and 3 to ?0?.
v850es/jg3-l chapter 5 bus control function r01uh0165ej0700 rev.7.00 page 201 of 1113 sep 22, 2011 5.6.2 external wait function to synchronize a low-speed device or asynchronous system, any number of wait states can be inserted in the bus cycle by using the extern al wait pin (wait). access to each area of the internal ro m, internal ram, on-chip peripheral i/o, and expanded internal ram is not subject to control by the external wait function, in the same manner as the programmable wait function. the wait signal can be input asynchronously to clkout, and is sampled at the falling edge of the clock in the t2 and tw states of the bus cycle in t he multiplexed bus mode. in the separ ate bus mode, it is sampled at the rising edge of the clock immediately afte r the t1 and tw states of the bus cycle. if the setup/hold time of the sampling timing is not satisfied, whether a wait state is inserted in t he next state is undefined. the wait input function is enabled by setting the pmccm.pmccm0 bit to 1 (see 4.3.8 port cm ).
v850es/jg3-l chapter 5 bus control function r01uh0165ej0700 rev.7.00 page 202 of 1113 sep 22, 2011 5.6.3 relationship between progra mmable wait and external wait wait cycles are inserted as the result of an or oper ation between the wait cycles specified by the set programmable wait value an d the wait cycles controll ed by the wait pin. wait control programmable wait wait via wait pin for example, if the timing of the prog rammable wait and the wait pin signal is as shown in the figure 5-4, three wait states will be inserted in the bus cycle. if wait insertion is controlled by t he wait pin, wait st ates might not be inserted at the expected timing. in th is case, adjust the insertion timing by specifying a programmable wait value. figure 5-4. example of inserting wait states (a) in separate bus mode t1 tw tw tw t2 clkout wait pin wait via wait pin programmable wait wait control remark the circles indicate the sampling timing. (b) in multiplexed bus mode clkout t1 t2 tw tw tw t3 wait pin wait via wait pin programmable wait wait control remark the circles indicate the sampling timing.
v850es/jg3-l chapter 5 bus control function r01uh0165ej0700 rev.7.00 page 203 of 1113 sep 22, 2011 5.6.4 programmable address wait function address-setup or address-hold waits to be inserted in each bus cycle can be set by using the awc register. address wait insertion is set for each me mory block area (memo ry blocks 0 to 3). if an address-setup wait is inserted, it seems that the high-clock per iod of the t1 state is extended by 1 clock. if an address-hold wait is inserted, it seems that the low-clock period of t he t1 state is extended by 1 clock. (1) address wait cont rol register (awc) this register can be read or written in 16-bit units. reset sets this register to ffffh. cautions 1. the internal rom, internal ram, a nd on-chip peripheral i/o areas are not subject to address-setup wait or address-hold wait insertion. 2. write the awc register after reset, and th en do not change the set values. also, when changing the initial values of the awc register, do not access an external memory area until the settings are complete. after reset: ffffh r/w address: fffff488h 1 ahw3 ahwn 0 1 not inserted inserted awc 1 asw3 1 ahw2 1 asw2 1 ahw1 note 1 asw1 note 1 ahw0 1 asw0 8 9 10 11 12 13 specifies insertion of address-hold wait (n = 0 to 3) 14 15 1 2 3 4 5 6 7 0 aswn 0 1 not inserted inserted specifies insertion of address-setup wait (n = 0 to 3) memory block 0 memory block 3 memory block n signal memory block 2 memory block 1 note the ahw1 and asw1 bits are used to specify whether to insert wait states for the expanded internal ram area. when using the expanded internal ram area, set these bits to 00. ( pd70f3841, 70f3842) caution be sure to set bits 15 to 8 to ?1?.
v850es/jg3-l chapter 5 bus control function r01uh0165ej0700 rev.7.00 page 204 of 1113 sep 22, 2011 5.7 idle state insertion function to realize interfacing with a low-speed device, one idle state (ti) can be insert ed after the t3 state only in the read access of the bus cycle that is exec uted for each space selected by the memory block in the multiplexed address/data bus mode. in the separate bus mode, one idle state (ti) can be inserted after the t2 state. by inserting idle states, the data output float delay time of the memory can be secured during a read access (an idle state cannot be inserted during a write access). whether an idle state is to be inserted can be programmed by using the bcc register. an idle state is inserted for all t he areas immediately after system reset. (1) bus cycle control register (bcc) this register can be read or written in 16-bit units. reset sets this register to aaaah. cautions 1. the internal rom, in ternal ram, and on-chip peripheral i/o areas are not subject to idle state insertion. 2. write to the bcc register after reset, a nd then do not change the set values. also, when changing the initial values of the bcc register, do not access an external memory area until the settings are complete. after reset: aaaah r/w address: fffff48ah 1 bc31 bcn1 0 1 not inserted inserted bcc 0 0 1 bc21 0 0 1 bc11 note 0 0 1 bc01 0 0 8 9 10 11 12 13 specifies insertion of idle state (n = 0 to 3) 14 15 1 2 3 4 5 6 7 0 memory block 0 memory block 3 memory block n signal memory block 2 memory block 1 note the bc11 bit is used to specify whet her to insert idle states for the expanded internal ram area. when using the expanded internal ram area, set this bit to 0. ( pd70f3841, 70f3842) caution be sure to set bi ts 15, 13, 11, and 9 to ?1 ?, and clear bits 14, 12, 10, 8, 6, 4, 2, and 0 to ?0?.
v850es/jg3-l chapter 5 bus control function r01uh0165ej0700 rev.7.00 page 205 of 1113 sep 22, 2011 5.8 bus hold function 5.8.1 functional outline the hldrq and hldak signals are valid if the pcm2 and pcm3 pins are set to the control mode. when the hldrq signal is asserted (low level), indicating that another bus master has requested bus mastership, the external address/data bus goes into a high-impedance st ate, the hldak signal is asserted (low level), and the bus is released (bus hold status). if the request for the bus mastership is cleared and the hldrq signal is deasserted (high level), driving t hese signals is started again. during the bus hold period, the cpu continues executing the program in the internal rom and internal ram until an on-chip peripheral i/o register, expanded internal ram, or the external memory is accessed. the bus hold function enables the configuration of mu lti-processor type systems in which two or more bus masters exist. note that a bus hold request is not acknowledged during a multiple-acce ss cycle initiated by the bus sizing function or a bit manipulation instruction. the timing at which a bus hold request is not acknowledged is shown below. table 5-6. timing at which bus ho ld request is not acknowledged status data bus width access type timing at which bus hold request is not acknowledged word access to even address between first and second access between first and second access word access to odd address between second and third access 16 bits halfword access to odd address between first and second access between first and second access between second and third access word access between third and fourth access cpu bus lock 8 bits halfword access between first and second access read-modify-write access by bit manipulation instruction ? ? between read access and write access
v850es/jg3-l chapter 5 bus control function r01uh0165ej0700 rev.7.00 page 206 of 1113 sep 22, 2011 5.8.2 bus hold procedure the bus hold status transiti on procedure is shown below. <1> a low level signal is input to the hldrq pin. <2> all bus cycle start requests are inhibited. <3> end of the current bus cycle. <4> shift to the bus idle status. <5> a low level signal is output from the hldak pin. <6> a high level signal is input to the hldrq pin. <7> a high level signal is output from the hldak pin. <8> bus cycle start request inhibition is released. <9> the bus cycle starts. normal status bus hold status normal status hldak (output) hldrq (input) <1> <2> <5> <3><4> <7><8><9> <6> 5.8.3 operation in power save mode because the internal system clock is stopped in the st op and idle modes, the bus hold status is not entered even if the hldrq pin is asserted. in the halt mode, the hldak pin is asserted as soon as the hldrq pin has be en asserted, and the bus hold status is entered. when the hldrq pin is later deasserted, the hldak pi n is also deasserted, and the bus hold status is exited.
v850es/jg3-l chapter 5 bus control function r01uh0165ej0700 rev.7.00 page 207 of 1113 sep 22, 2011 5.9 bus priority bus hold, branch instruction fetch, successive instru ction fetch, operand data access, and dma transfer are executed in the external bus cycle. bus hold has the highest priority, followed by dma transfe r, operand data access, branch instruction fetch, and then successive instruction fetch. however, an instruction fetch may be inserted between t he read access and write access in a read-modify-write access. if an instruction is executed for two or more accesses, an instruction fetch and bus ho ld are not inserted between accesses due to bus size limitations. table 5-7. bus priority priority external bus cycle bus master high bus hold external device dma transfer dmac operand data access cpu branch instruction fetch cpu low successive instruction fetch cpu
v850es/jg3-l chapter 5 bus control function r01uh0165ej0700 rev.7.00 page 208 of 1113 sep 22, 2011 5.10 bus timing typical bus timing diagrams are shown below. when use a separate bus in pd70f3841, 70f3842, refer to timing of multiplexed bus mode. figure 5-5. multiplexed bus read timi ng (bus size: 16 bits, 16-bit access) a1 a2 a3 d1 d2 a3 a2 a1 t1 t2 t3 t1 t2 tw tw t3 ti t1 programmable wait external wait idle state clkout a21 to a16 note astb wait ad15 to ad0 rd note pd70f3841, 70f3842 have a21 to a0 (when using separate output) remarks 1. the validity of data if 8-bit access is executed when 16-bit a ccess has been specified is shown below. 8-bit access odd address even address ad15 to ad8 valid data invalid data ad7 to ad0 invalid data valid data 2. the broken lines indicate high impedance. figure 5-6. multiplexed bus r ead timing (bus size: 8 bits) a1 a2 a3 d1 d2 a3 a2 a1 t1 t2 t3 t1 t2 tw tw t3 ti t1 programmable wait external wait idle state clkout a21 to a16 note , ad15 to ad8 astb wait ad7 to ad0 rd note pd70f3841, 70f3842 have a21 to a0 (when using separate output) remark the broken lines indicate high impedance.
v850es/jg3-l chapter 5 bus control function r01uh0165ej0700 rev.7.00 page 209 of 1113 sep 22, 2011 figure 5-7. multiplexed bus write timi ng (bus size: 16 bits, 16-bit access) a1 11 00 11 11 00 11 a2 a3 d1 d2 a3 a2 a1 t2 t3 t1 t1 t2 tw tw t3 t1 programmable wait external wait clkout a21 to a16 note astb wait ad15 to ad0 wr1, wr0 note pd70f3841, 70f3842 have a21 to a0 (when using separate output) remark the validity of data if 8-bit access is executed when 16-bit access has been specified is shown below. 8-bit access odd address even address ad15 to ad8 valid data invalid data ad7 to ad0 invalid data valid data wr1, wr0 01 10 figure 5-8. multiplexed bus wr ite timing (bus size: 8 bits) a1 11 10 11 11 10 11 a2 a3 d1 d2 a3 a2 a1 t2 t3 t1 t1 t2 tw tw t3 t1 programmable wait external wait clkout a21 to a16 note , ad15 to ad8 astb wait ad7 to ad0 wr1, wr0 note pd70f3841, 70f3842 have a21 to a0 (when using separate output)
v850es/jg3-l chapter 5 bus control function r01uh0165ej0700 rev.7.00 page 210 of 1113 sep 22, 2011 figure 5-9. multiplexed bus hold timi ng (bus size: 16 bits, 16-bit access) t1 a1 undefined a1 a2 t2 t3 ti note1 th th th th ti note1 t1 t2 t3 d1 clkout hldrq hldak a21 to a16 note2 astb ad15 to ad0 rd undefined undefined undefined a2 d2 notes1. this idle state (ti) does not depend on the bcc register settings. 2. pd70f3841, 70f3842 have a21 to a0 (when using separate output) remarks 1. see table 2-2 for the pin statuses in the bus hold mode. 2. the broken lines indicate high impedance. figure 5-10. address wait timing (bus size: 16 bits, 16-bit access) tasw t1 tahw t2 clkout astb ad15 to ad0 a1 d1 wait rd t1 t2 clkout astb ad15 to ad0 wait rd d1 a1 a21 to a16 note a21 to a16 note a1 a1 note pd70f3841, 70f3842 have a21 to a0 remarks 1. tasw (address-setup wait): image of hi gh-level width of t1 state expanded. 2. tahw (address-hold wait): image of lo w-level width of t1 state expanded. 3. the broken lines indicate high impedance.
v850es/jg3-l chapter 5 bus control function r01uh0165ej0700 rev.7.00 page 211 of 1113 sep 22, 2011 figure 5-11. separate bus read timi ng (bus size: 16 bits, 16-bit access) ( pd70f3737, 70f3738, 70f3792, 70f3793 only) t1 a1 a2 a3 t2 t1 tw tw t2 t2 ti t1 d3 d2 programmable wait external wait idle state d1 clkout a21 to a0 wait ad15 to ad0 note rd remarks 1. the validity of data if 8-bit access is executed when 16-bit a ccess has been specified is shown below. 8-bit access odd address even address ad15 to ad8 valid data invalid data ad7 to ad0 invalid data valid data 2. the broken lines indicate high impedance. figure 5-12. separate bus read timing (bus size: 8 bits) ( pd70f3737, 70f3738, 70f3792, 70f3793 only) t1 a1 a2 a3 t2 t1 tw tw t2 t2 ti t1 d3 d2 programmable wait external wait idle state d1 clkout a21 to a0 wait ad7 to ad0 rd remark the broken lines indicate high impedance.
v850es/jg3-l chapter 5 bus control function r01uh0165ej0700 rev.7.00 page 212 of 1113 sep 22, 2011 figure 5-13. separate bus write ti ming (bus size: 16 bits, 16-bit access) ( pd70f3737, 70f3738, 70f3792, 70f3793 only) t1 a1 11 00 00 00 11 11 11 11 a2 a3 t2 t1 tw tw t2 t1 t2 d3 d2 programmable wait external wait d1 clkout a21 to a0 wait ad15 to ad0 wr1, wr0 remarks 1. the validity of data if 8-bit access is executed when 16-bit a ccess has been specified is shown below. 8-bit access odd address even address ad15 to ad8 valid data invalid data ad7 to ad0 invalid data valid data wr1, wr0 01 10 2. the broken lines indicate high impedance. figure 5-14. separate bus write timing (bus size: 8 bits) ( pd70f3737, 70f3738, 70f3792, 70f3793 only) t1 a1 a2 a3 t2 t1 tw tw t2 t1 t2 d3 d2 programmable wait external wait d1 clkout a21 to a0 wait ad7 to ad0 wr1, wr0 11 10 10 10 11 11 11 11 remark the broken lines indicate high impedance.
v850es/jg3-l chapter 5 bus control function r01uh0165ej0700 rev.7.00 page 213 of 1113 sep 22, 2011 figure 5-15. separate bus hold timing (bus size: 8 bits, write) ( pd70f3737, 70f3738, 70f3792, 70f3793 only) clkout t1 t2 a1 d1 d2 undefined a2 undefined 11 11 10 d3 a3 t1 t2 th ti note ti note th th th t1 t2 hldrq hldak a21 to a0 ad7 to ad0 wr1, wr0 11 10 11 10 11 note this idle state (ti) does not de pend on the bcc register settings. remark the broken lines indicate high impedance. figure 5-16. address wait timing (separat e bus read, bus size: 16 bits, 16-bit access) ( pd70f3737, 70f3738, 70f3792, 70f3793 only) tasw t1 tahw t2 clkout astb a21 to a0 wait ad15 to ad0 rd d1 a1 t1 t2 clkout astb a21 to a0 wait ad15 to ad0 rd d1 a1 remarks 1. tasw (address setup wait): image of hi gh-level width of t1 state expanded. 2. tahw (address hold wait): image of lo w-level width of t1 state expanded. 3. the broken lines indicate high impedance.
v850es/jg3-l chapter 5 bus control function r01uh0165ej0700 rev.7.00 page 214 of 1113 sep 22, 2011 5.11 sram connection examples examples of connecting the v850es/jg 3-l to sram in separate mode using the following configurations are shown below. ? connecting an sram with an 8-bit data bu s to the v850es/jg3-l via an 8-bit bus ? connecting two srams with an 8-bit data bus to the v850es/jg3-l via a 16-bit bus ? connecting an sram with a 16-bit data bu s to the v850es/jg3-l via a 16-bit bus figure 5-17. connecting sram with 8-bit data bus to v850es/ jg3-l via 8-bit bus a0 to a17 ad0 to ad7 wr0 rd a18 note a0 to a17 i/o1 to i/o8 we oe ce sram (256 k words 8 bit) v850es/jg3-l ev dd ev dd ev dd damping resistor damping resistor damping resistor note generate the chip select sign al using the higher address. figure 5-18. connecting two srams with 8-bi t data bus to v850es/ jg3-l via 16-bit bus ev dd ev dd ev dd ev dd a1 to a18 ad8 to ad15 wr1 rd a19 note a0 to a17 i/o1 to i/o8 we oe ce sram (256 k words 8 bit) v850es/jg3-l ad0 to ad7 wr0 a0 to a17 i/o1 to i/o8 we oe ce sram (256 k words 8 bit) damping resistor damping resistor damping resistor damping resistor damping resistor note generate the chip select sign al using the higher address.
v850es/jg3-l chapter 5 bus control function r01uh0165ej0700 rev.7.00 page 215 of 1113 sep 22, 2011 figure 5-19. connecting sram with 16-bit data bus to v850es/ jg3-l via 16-bit bus ev dd ev dd ev dd ev dd a1 to a18 ad0 to ad15 wr1 wr0 rd a0 to a17 i/o1 to i/o16 we oe ub lb ce sram (256 k words 16 bit) v850es/jg3-l a19 note damping resistor damping resistor damping resistor note generate the chip select sign al using the higher address.
v850es/jg3-l chapter 6 clock generator r01uh0165ej0700 rev.7.00 page 216 of 1113 sep 22, 2011 chapter 6 clock generator 6.1 overview the clock generator generates the clock signals that ar e input to the cpu and peripherals. the clock generator includes a pll circuit, which enables the clock frequency to be multiplied by four. the clock frequency can also be divided before clock signals are input to the cpu or on-c hip peripherals. clock oscillation can also be stopped to save power. the clock generator has the following features: { main clock oscillator ? in clock-through mode f x = 2.5 to 10 mhz (f xx = 2.5 to 10 mhz) ( pd70f3737, 70f3738) (f xx = 1.25 to 10 mhz) ( pd70f3792, 70f3793, 70f3841, 70f3842) ? in pll mode f x = 2.5 to 5 mhz ( 4 : f xx = 10 to 20 mhz) { subclock oscillator ? f xt = 32.768 khz { internal oscillator ? f r = 220 khz (typ.) { multiplication ( 4) function via pll (phase locked loop) ? clock-through mode/pll mode selectable (f x = 2.5 to 5 mhz) { internal system clock generation ? 7 steps (f xx , f xx /2, f xx /4, f xx /8, f xx /16, f xx /32, f xt ) { peripheral clock generation { clock output { external clock input remark f x : main clock oscillation frequency f xx : main clock frequency f xt : subclock frequency f r : internal oscillator clock frequency
v850es/jg3-l chapter 6 clock generator r01uh0165ej0700 rev.7.00 page 217 of 1113 sep 22, 2011 6.2 configuration figure 6-1. clock generator selector selector note1 frc bit mfrc bit mck bit ck2 to ck0 bits selpll bit ckthsel bit pllon bit ck3 bits stop mode subclock oscillator port cm prescaler 1 prescaler 2 idle control halt control halt mode cpu clock rtc note2 /watch timer clock timer m clock rtc note2 /watch timer clock, watchdog timer 2 clock peripheral clock, watchdog timer 2 clock watchdog timer 2 clock, timer m clock internal system clock main clock oscillator main clock oscillator stop control rstop bit internal oscillator 1/8 divider xt1 xt2 clkout x1 x2 idle mode pll 1/2 f xx /32 f xx /16 f xx /8 f xx /4 f xx /2 f xx f cpu f clk f xx to f xx /1,024 f x /2-f x /2 12 f xt f xt f xx f x f r f r /8 idle control selector selector note2 selector notes1. the internal oscillator clock is selected when watchdog timer 2 overflows during the oscillation stabilization time. 2. the feature shown in the dotted line is only available in the pd70f3792, 70f3793, 70f3841, 70f3842. remark f x : main clock oscillation frequency f xx : main clock frequency f clk : internal system clock frequency f xt : subclock frequency f cpu : cpu clock frequency f r : internal oscillator clock frequency
v850es/jg3-l chapter 6 clock generator r01uh0165ej0700 rev.7.00 page 218 of 1113 sep 22, 2011 (1) main clock oscillator the main clock oscillator uses a ceramic/crystal reso nator connected to x1 and x2 pins to oscillate the following frequencies (f x ). ? in clock-through mode f x = 2.5 to 10 mhz (f xx = 2.5 to 10 mhz) ( pd70f3737, 70f3738) (f xx = 1.25 to 10 mhz) ( pd70f3792, 70f3793, 70f3841, 70f3842) ? in pll mode f x = 2.5 to 5 mhz ( 4 : f xx = 10 to 20 mhz) an external clock of the following frequency is input to the x1 pin. ? in clock-through/pll mode f x = 2.5 to 5 mhz (2) subclock oscillator the subclock oscillator oscillat es a frequency of 32.768 khz (f xt ). in the pd70f3792,70f3793, 70f3841, 70f3842, this is in the rtc backu p area and causes the subclock to continue oscillating even in the rtc backup mode. (3) main clock oscillator stop control this circuit generates a control signal that stops oscillation of the main clock oscillator. oscillation of the main clock oscillator is stopped in t he stop mode or when the p cc.mck bit is 1 (valid only when the pcc.cls bit is 1). (4) internal oscillator oscillates a frequency (f r ) of 220 khz (typ.). (5) prescaler 1 this prescaler generates the clock (f xx to f xx /1,024) to be supplied to the following on-chip peripheral functions: tmp0 to tmp5, tmq0, tmm0, csib0 to csib4, uarta0 to uarta5, uartc0, i 2 c00 to i 2 c02, adc, and wdt2 (6) prescaler 2 this circuit divides the main clock (f xx ). the clock generated by prescaler 2 (f xx to f xx /32) is supplied to the selector that generates the cpu clock (f cpu ) and internal system clock (f clk ). f clk is the clock supplied to the intc, rom, ram, and dma blocks, and can be output from the clkout pin. (7) pll this circuit multiplies the clock generated by the main clock oscillator (f x ) by 4. it operates in two modes: clock-through mode in which f x is output as is, and pll mode in which a multiplied clock is output. these modes can be selected by using the pllctl.selpll bit. pll is started or stopped by the pllctl.pllon bit. (8) clock i/o circuit this circuit outputs the internal system clock to the clkout pin. the pmccm1 bit of the pmccm register for port cm c ontrols whether the pmc1 pin operates as an i/o port or as clkout output.
v850es/jg3-l chapter 6 clock generator r01uh0165ej0700 rev.7.00 page 219 of 1113 sep 22, 2011 6.3 registers (1) processor clock control register (pcc) the pcc register is a special register . data can be written to this regist er only in combination of specific sequences (see 3.4.7 special registers ). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 03h. (1/2) frc notes1, 2 used not used frc notes1, 2 0 1 use of subclock on-chip feedback resistor pcc mck mfrc cls note3 ck3 ck2 ck1 ck0 oscillation enabled oscillation stopped mck 0 1 main clock oscillator control used (when ceramic/crystal resonator is used) not used (when external clock is used) mfrc 0 1 use of main clock on-chip feedback resistor after reset: 03h r/w address: fffff828h main clock operation subclock operation cls note3 0 1 status of cpu clock (f cpu ) < > < > < > f xx f xx /2 f xx /4 f xx /8 (initial value) f xx /16 f xx /32 setting prohibited f xt ck2 0 0 0 0 1 1 1 clock selection (f clk /f cpu ) ck1 0 0 1 1 0 0 1 ck0 0 1 0 1 0 1 ck3 0 0 0 0 0 0 0 1 notes1. when the frc bit is set (to 1) , the subclock stops oscillating ( pd70f3792, 70f3793, 70f3841, 70f3842 ). 2. when return to the rtc backup mode, specify rtcbumctl0. rbmset (to 0) and then set the frc bit (to 1) ( pd70f3792, 70f3793, 70f3841, 70f3842 ). 3. the cls bit is a read-only bit.
v850es/jg3-l chapter 6 clock generator r01uh0165ej0700 rev.7.00 page 220 of 1113 sep 22, 2011 (2/2) cautions 1. do not change the cpu clock (by using the ck3 to ck0 bits) while clkout is being output. 2. use a bit manipulation instruction to ma nipulate the ck3 bit. when using an 8-bit manipulation instruction, do not change the set values of the ck2 to ck0 bits. 3. when the external clock is used, set the mfrc bit to ?1? so as not to u se the internal feedback resistor. 4. even if the mck bit is set (1) while the s ystem is operating with th e main clock as the cpu clock, the operation of the ma in clock does not stop. it stops after the cpu clock has been changed to the subclock. 5. before changing the mck bit from 0 to 1, stop the on-chip peripheral functions operating on the main clock. 6. when the main clock is st opped and the device is operating on the subclock, clear (0) the mck bit and secure the oscillati on stabilization time by softw are before switching the cpu clock to the main clock or operating the on-chip peripheral functions. remark : don?t care
v850es/jg3-l chapter 6 clock generator r01uh0165ej0700 rev.7.00 page 221 of 1113 sep 22, 2011 (a) example of changing main cl ock operation to subclock operation <1> ck3 bit 1: use of a bit manipulation instruct ion is recommended. do not change the ck2 to ck0 bits. <2> subclock operation: read the cls bit to check if subclock operation has started. it takes the following time after the ck3 bit is se t until subclock operation is started. max.: 1/f xt (1/subclock frequency) <3> mck bit 1: set the mck bit to 1 only when stopping the main clock. cautions 1. when stopping the main clock, stop the pll. al so stop the operations of the on-chip peripheral functions operating on the main clock. 2. if the following condition is not satisfi ed, change the ck2 to ck0 bits so that the condition is satisfied, then change to the subclock operation mode. internal system clock (f clk ) > subclock (f xt : 32.768 khz) 4 remark internal system clock (f clk ): clock generated from the main clock (f xx ) by setting bits ck2 to ck0 [description example] _dma_disable: clrl 0, dchcn[r0] -- dma operation disabled. n = 0 to 3 <1> _set_sub_run : st.b r0, prcmd[r0] set1 3, pcc[r0] -- ck3 bit 1 <2> _check_cls : tst1 4, pcc[r0] -- wait until subclock operation starts. bz _check_cls <3> _stop_main_clock : st.b r0, prcmd[r0] set1 6, pcc[r0] -- mck bit 1, main clock is stopped. _dma_enable: setl 0, dchcn[r0] -- dma operation enabled. n = 0 to 3 remark the description above is simply an example. note that in <2> above, the cls bit is checked in a closed loop.
v850es/jg3-l chapter 6 clock generator r01uh0165ej0700 rev.7.00 page 222 of 1113 sep 22, 2011 (b) example of changing subclock operation to main clock operation <1> mck bit 0: main clock starts oscillating <2> insert waits by program and wait until the osc illation stabilization time of the main clock has elapsed. <3> ck3 bit 0: use of a bit manipulation instru ction is recommended. do not change the ck2 to ck0 bits. <4> main clock operation: it takes the following time after the ck3 bit is set until main clock operation is started. max.: 1/f xt (1/subclock frequency) therefore, insert one nop instruction immediately after setting the ck3 bit to 0. caution enable operation of the on-chip periphe ral functions operating on the main clock only after the oscillation of the main clock stabiliz es. if their operations are enabled before the lapse of the oscillation stabilizat ion time, a malfunction may occur. [description example] _dma_disable: clrl 0, dchcn[r0] -- dma operation disabled. n = 0 to 3 <1> _start_main_osc : st.b r0, prcmd[r0] -- release of protection of special registers clr1 6, pcc[r0] -- main clock starts oscillating. <2> movea 0x55, r0, r11 -- wait for oscillation stabilization time. _wait_ost : nop nop nop addi -1, r11, r11 bnz _wait_ost <3> st.b r0, prcmd[r0] clr1 3, pcc[r0] -- ck3 0 <4> nop _dma_enable: setl 0, dchcn[r0] -- dma operation enabled. n = 0 to 3
v850es/jg3-l chapter 6 clock generator r01uh0165ej0700 rev.7.00 page 223 of 1113 sep 22, 2011 (2) internal oscillator mode register (rcm) the rcm register is an 8-bit register that sets the operation mode of the internal oscillator. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 rcm 0 0 0 00 0 rstop do not stop internal oscillator oscillation stop internal oscillator rstop 0 1 oscillation/stop of internal oscillator after reset: 00h r/w address: fffff80ch < > cautions 1. the internal osc illator cannot be stopped while the cpu is operating on the internal oscillator clock ( ccls.cclsf bit = 1). do not set the rstop bit to 1. 2. the internal oscillator oscillates if a watchdog timer overflow occurs while the oscillator signal is stabilizing afte r stop mode has been canceled by the occurrence of an interrupt (that is, if the ccls.cclsf bit is set to 1), even if the internal oscillator is stopped (the rs top bit is 1). at this time, rstop remains set to 1. 3. the settings of the rcm register are va lid by setting the option byte only in the pd70f3792, 70f3793, 70f3841 and 70f3842 . for details, see chapter 29 option byte. (3) cpu operation clock status register (ccls) the ccls register indicates the stat us of the cpu operation clock. this register is read-only, in 8-bit or 1-bit units. reset sets this register to 00h. 0 ccls 0 0 0 0 0 0 cclsf after reset: 00h note r address: fffff82eh operating on main clock (f x ) or subclock (f xt ). operating on internal oscillator clock (f r ). cclsf 0 1 cpu operation clock status note if a wdt overflow occurs during oscillation stabilization after a reset is released or stop mode is released, the cclsf bit is set to 1 and the reset value is 01h.
v850es/jg3-l chapter 6 clock generator r01uh0165ej0700 rev.7.00 page 224 of 1113 sep 22, 2011 (4) clock-through select register (ckthsel) ( pd70f3792, 70f3793, 70f 3841, 70f3842 only) the ckthsel register is used to select the clock- through frequency or the clock-through frequency divided by 2 when in the clock-through mode. this register can be read or written in 8-bit or 1bit units. reset sets this register to 00h. 0 ckthsel0 0 1 clock-through select register ckthsel 0 0 0 0 0 0 ckthsel0 after reset: 00h r/w address: fffff380h clock-through frequency clock-through frequency divided by 2 < >
v850es/jg3-l chapter 6 clock generator r01uh0165ej0700 rev.7.00 page 225 of 1113 sep 22, 2011 6.4 operations 6.4.1 operation of each clock the following table shows the oper ation status of each clock. table 6-1. operation status of each clock pcc register clk bit = 0, mck bit = 0 cls bit = 1, mck bit = 0 cls bit = 1, mck bit = 1 - note3 register setting and operation status target clock during reset during oscillation stabilization time count halt mode idle1 mode, idle2 mode stop mode subclock mode sub-idle mode subclock mode sub-idle mode rtc backup mode note5 main clock oscillator (f x ) - note4 subclock oscillator (f xt ) cpu clock (f cpu ) - note4 internal system clock (f clk ) - note4 main clock (in pll mode, f xx ) note1 note2 note2 - note4 peripheral clock (f xx to f xx /1,024) - note4 wt clock (main) - note4 wt clock (sub) - note4 wdt2 clock (internal oscillation) - note4 wdt2 clock (main) - note4 wdt2 clock (sub) - note4 rtc clock (main) note5 - note4 rtc clock (sub) note5 notes 1. lockup time 2. be sure to set the pllctl.pllon to 0. 3. because v dd is less than the guaranteed operating volt age, the register value is undefined. 4. because v dd is less than the guaranteed operating volt age, the operating st atus is undefined. 5. pd70f3792, 70f3793, 70f3841, 70f3842 only remark : operating : stopped -: undefined
v850es/jg3-l chapter 6 clock generator r01uh0165ej0700 rev.7.00 page 226 of 1113 sep 22, 2011 6.4.2 clock output function the clock output function is used to output the internal system clock (f clk ) from the clkout pin. the internal system clock (f clk ) is selected by using the pcc.ck3 to pcc.ck0 bits. the clkout pin functions alternately as the pcm1 pin and functions as a clo ck output pin if so specified by the control register of port cm. the status of the clko ut pin is the same as the internal system clock in table 6-1 and the pin can output the clock when it is in the operable status . it outputs a low level in the stopped st atus. however, the clkout pin is in the port mode (pcm1 pin: input mode) after reset and until it is set in the output mode. t herefore, the st atus of the pin is hi-z. 6.4.3 external clock signal input an external clock signal can be directly input to the oscill ator. input the clock to the x1 pin and leave the x2 pin open. set the pcc.mfrc bit to 1 (on-chip feedback resistor not used). note, however, that time is required to stabilize the oscillator signal even when inputting an external clock signal. 6.5 pll function 6.5.1 overview in the v850es/jg3-l, an operating clock that is the oscillation frequency mult iplied by 4 by the pll function or an unmultiplied clock (clock-through mode) can be selected as the operating clock of t he cpu and on-chip peripheral functions. when pll function is used: input clock = 2.5 to 5 mhz (output: 10 to 20 mhz) clock-through mode: input clock = 2.5 to 10 mhz (output: 2.5 to 10 mhz) ( pd70f3737, 70f3738) = 2.5 to 10 mhz (output: 1.25 to 10 mhz) ( pd70f3792, 70f3793, 70f3841, 70f3842)
v850es/jg3-l chapter 6 clock generator r01uh0165ej0700 rev.7.00 page 227 of 1113 sep 22, 2011 6.5.2 registers (1) pll control register (pllctl) the pllctl register is an 8-bit regi ster that controls the pll function. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 01h. 0 pllctl 0 0 0 00 selpll pllon disable pll operation enable pll operation (after pll operation starts, a lockup time is required for frequency stabilization.) pllon 0 1 control of pll operation clock-through mode pll mode selpll 0 1 selection of cpu operation clock mode after reset: 01h r/w address: fffff82ch < > < > cautions 1. when the pllon bit is cleared to 0, the selpll bit is automatically cleared to 0 (clock-through mode). 2. the selpll bit can be set to 1 only when th e pll clock frequency is stabilized. if not (if the pll is unlocked), ?0? is written to the selpll bit whatever data is written to it. (2) clock control register (ckc) the ckc register is a special register. data can be wri tten to this register only in a combination of specific sequences (see 3.4.7 special registers ). the ckc register controls the inte rnal system clock in the pll mode. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 0ah. 0 ckc 0 0 0 1 0 1 ckdiv0 after reset: 0ah r/w address: fffff822h f xx = 4 f x (f x = 2.5 to 5.0 mhz) setting prohibited ckdiv0 0 1 internal system clock (f xx ) in pll mode cautions 1. the pll mode cannot be used when f x = 5.0 to 10.0 mhz. 2. be sure to set the ckc regist er to 0ah. if a value other th an 0ah is set, the operation is not guaranteed.
v850es/jg3-l chapter 6 clock generator r01uh0165ej0700 rev.7.00 page 228 of 1113 sep 22, 2011 (3) lock register (lockr) the pll locks the phase at a given frequency after the power is turned on or immediately after the stop mode is canceled. the time required for the frequency to stabilize is the lockup time (frequency stabilization time). this state until the frequency st abilizes is called the lockup status, and the state in which the frequency is stabilized is called the locked status. the lockr register includes a lock bit that re flects the pll frequency stabilization status. this register is read-only, in 8-bit or 1-bit units. reset sets this register to 00h. 0 lockr 0 0 0 00 0 lock locked status unlocked status lock 0 1 pll lock status check after reset: 00h r address: fffff824h < > caution the lock register does not reflect the lock status of the pll in real time. the set/clear conditions are as follows. [set conditions] ? upon system reset note ? in idle2 or stop mode ? upon setting of pll stop (clearing of pllctl.pllon bit to 0) ? upon stopping main clock and using cpu on subclock (setting of pcc.ck3 bit to 1 and setting of pcc.mck bit to 1) note this register is set to 01h by reset and cleared to 00h after the reset has been released and the oscillation stabilization time has elapsed. [clear conditions] ? upon overflow of oscillation stabilization time fo llowing reset release (osts register default time (see chapter 29 option byte )) ? upon oscillation stabilization timer overflow (time set by osts register) following stop mode release, when the stop mode was set in the pll operating status ? upon pll lockup time timer overflow (time se t by plls register) when the pllctl.pllon bit is changed from 0 to 1 ? after the setup time inserted upon release of t he idle2 mode (time set by the osts register) has elapsed when the idle2 mode is set during pll operation.
v850es/jg3-l chapter 6 clock generator r01uh0165ej0700 rev.7.00 page 229 of 1113 sep 22, 2011 (4) pll lockup time specification register (plls) the plls register is an 8-bit regi ster used to select the pll lockup time when the pllctl.pllon bit is changed from 0 to 1. this register can be read or written in 8-bit units. reset sets this register to 03h. 0 2 10 /f x 2 11 /f x 2 12 /f x 2 13 /f x (default value) plls1 0 0 1 1 plls0 0 1 0 1 selection of pll lockup time plls 0 0 0 0 0 plls1 plls0 after reset: 03h r/w address: fffff6c1h cautions 1. set so that the lockup time is at least 400 s. 2. do not change the plls regi ster setting during the lockup period.
v850es/jg3-l chapter 6 clock generator r01uh0165ej0700 rev.7.00 page 230 of 1113 sep 22, 2011 6.5.3 usage (1) when pll is used ? after the reset signal has been released, the p ll operates (pllctl.pllon bit = 1), but because the default mode is the clock-through mode (pllctl.selpll bit = 0), select the pll mode (selpll bit = 1). ? to enable pll operation, first set the pllon bit to 1, and then set the selpll bit to 1 after the lockr.lock bit becomes 0. to st op the pll, first select the clock-through mode (selpll bit = 0), wait for 8 clocks or more, and then stop the pll (pllon bit = 0). ? the pll stops during transition to the idle2 or stop mode regardless of the setting and is restored from the idle2 or stop mode to the status before transition. the time requir ed for restoration is as follows. (a) when transitioning to the idle2 or stop mode from the clock through mode ? stop mode: set the osts register so that the oscillation stabilization time is at least 400 s. ? idle2 mode: set the osts register so that the setup time is at least 200 s. (b) when transitioning to the idle 2 or stop mode while remaining in the pll operation mode ? stop mode: set the osts register so that the oscillation stabilization time is at least 400 s. ? idle2 mode: set the osts register so that the setup time is at least 400 s. when transitioning to the idle1 mode, the pll does not stop. stop the pll if necessary. (2) when pll is not used ? the clock-through mode (selpll bit = 0) is selected a fter the reset signal has been released, but the pll is operating (pllon bit = 1) and must therefore be stopped (pllon bit = 0). the time required for restoration from the idle2 and stop modes is as follows. ? stop mode: set the osts register so that the oscillation stabilization time is at least 400 s. ? idle2 mode: set the osts register so that the setup time is at least 200 s.
v850es/jg3-l chapter 6 clock generator r01uh0165ej0700 rev.7.00 page 231 of 1113 sep 22, 2011 6.6 how to connect a resonator 6.6.1 main clock oscillator the signal input to the main clock oscillator is oscillated by a ceramic or crystal resonator connected to the x1 and x2 pins. the frequency of the resonator is 2.5 to 10 mhz. an external clock signal can also be input to the main clock oscillator. figure 6-2 shows an example of the circuit connected to the main clock oscillator. figure 6-2. example of circuit c onnected to main clock oscillator (a) crystal or ceramic reso nator (b) external clock v ss x1 x2 x2 x1 external clock open cautions related to connecting these circuits are shown on the following page. 6.6.2 subclock oscillator the signal input to the subclock oscillator is oscillate d by a crystal resonator connected to the xt1 and xt2 pins. the frequency of the resonat or is 32.768 khz (standard). figure 6-3 shows an example of the circui t connected to the subclock oscillator. figure 6-3. example of circuit connected to subclock oscillator (a) crystal resonator xt2 v ss xt1 32.768 khz cautions related to connecting this circuit are shown on the following page.
v850es/jg3-l chapter 6 clock generator r01uh0165ej0700 rev.7.00 page 232 of 1113 sep 22, 2011 caution 1. when using the main clock or subclock o scillator, wire as follows in the area enclosed by the broken lines in figures 6-2 and 6-3 to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line th rough which a high fluctuating current flows. ? always make the ground point of the osci llator capacitor the same potential as v ss . ? do not ground the capacitor to a ground pa ttern through which a high current flows. ? do not fetch signals from the oscillator. the subclock oscillator is designed as a low-amplitude circuit for reducing power consumption. particular care is theref ore required with the wiring method when the subclock is used. figure 6-4 shows examples of incorrect resonator connections. figure 6-4. examples of incorre ct resonator connections (1/2) (a) the wiring is too long. (b) the wiring crosses other signal lines. x2 v ss x1 x1 v ss x2 port remark for the subsystem clock, read x1 and x2 as xt 1 and xt2. note that a resistor must be inserted in series on the xt2 side.
v850es/jg3-l chapter 6 clock generator r01uh0165ej0700 rev.7.00 page 233 of 1113 sep 22, 2011 figure 6-4. examples of incorre ct resonator connections (2/2) (c) the wiring is routed near a signal line (d) a cu rrent with a higher potenti al than that of the through which a high fluctuating current flows. ground line of the oscillator block is flowing. (the potential differs at points a, b, and c.) v ss x1 x2 v ss x1 x2 ab c pmn v dd high current high current (e) signals are being fetched. v ss x1 x2 remark for the subsystem clock, read x1 and x2 as xt 1 and xt2. note that a resistor must be inserted in series on the xt2 side. cautions2. if x2 and xt1 are wired in parallel, crosstalk noise from xt1 may have a synergistic effect on x2, causing a malfunction.
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 234 of 1113 sep 22, 2011 chapter 7 16-bit timer/event counter p (tmp) timer p (tmp) is a 16-bit timer/event counter. the v850es/jg3-l has six timer/event counter channels, tmp0 to tmp5 (tmpn). 7.1 overview tmpn has the following features. (1) interval timer tmpn generates an interrupt at a preset interval and can output a square wave. (2) external event counter tmpn counts the number of externally input signal pulses. (3) external trigger pulse output tmpn starts counting and outputs a pulse when the specified external signal is input. (4) one-shot pulse output tmpn outputs a one-shot pulse with an output width that can be freely specified. (5) pwm output tmpn outputs a pulse with a constant cycle whose active width can be changed. the pulse duty can also be changed freely even while the timer is operating. (6) free-running timer tmpn increments from 0000h to ffffh and then resets. (7) pulse width measurement tmpn can be used to measure the pulses of a signal input externally. remark n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 235 of 1113 sep 22, 2011 7.2 configuration tmpn includes the following hardware. table 7-1. configuration of tmpn item configuration registers 16-bit counter tmpn counter read buffer register (tpncnt) tmpn capture/compare registers 0, 1 (tpnccr0, tpnccr1) ccr0, ccr1 buffer registers tmpn control registers 0, 1 (tpnctl0, tpnctl1) tmpn i/o control registers 0 to 2 (tpnioc0 to tpnioc2) tmpn option register 0 (tpnopt0) timer inputs 2 (tipn0, tipn1 pins) timer outputs 2 (topn0, topn1 pins) figure 7-1. block diagram of tmpn f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 note 1 , f xx /256 note 2 f xx /128 note 1 , f xx /512 note 2 selector internal bus internal bus topn0 topn1 tipn0 tipn1 selector edge detector ccr0 buffer register ccr1 buffer register tpnccr0 tpnccr1 16-bit counter tpncnt inttpnov inttpncc0 inttpncc1 output controller clear notes 1. tmp0, tmp2, tmp4 2. tmp1, tmp3, tmp5 remark f xx : main clock frequency n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 236 of 1113 sep 22, 2011 (1) 16-bit counter this is a 16-bit counter that counts internal clocks and external events. this counter can be read by using the tpncnt register. when the tpnctl0.tpnce bit is 0 and the counter is stopped, the counter value is ffffh. if the tpncnt register is read at this time, 0000h is read. reset sets the tpnce bit to 0, stopping the counter, and setting its value to ffffh. (2) tmpn counter read buffer register (tpncnt) this is a read buffer register from which the value of the 16-bit counter can be read. (3) tmpn capture/compare regist ers 0 and 1 (tpnccr0 and tpnccr1) these registers can be used as either capture regist ers or compare registers, in accordance with the specified mode. (4) ccr0 buffer register this is a 16-bit compare register that co mpares the value of the 16-bit counter. when the tpnccr0 register is used as a compare regist er, the value written to the tpnccr0 register is transferred to the ccr0 buffer register. if the value of the 16-bit counter matches the value of the ccr0 buffer register, a compare match interrupt request signal (inttpncc0) is generated. the ccr0 buffer register cannot be read or written directly. the ccr0 buffer register is cleared to 0000h after reset because the tpnccr0 register is cleared to 0000h. (5) ccr1 buffer register this is a 16-bit compare register that co mpares the value of the 16-bit counter. when the tpnccr1 register is used as a compare regist er, the value written to the tpnccr1 register is transferred to the ccr1 buffer register. if the count value of the 16-bit counter matches the value of the ccr1 buffer register, a compare match interrupt request signal (inttpncc1) is generated. the ccr1 buffer register cannot be read or written directly. the ccr1 buffer register is cleared to 0000h after reset because the tpnccr1 register is cleared to 0000h. (6) tmpn control registers 0 and 1 (tpnctl0 and tpnctl1) these are 8-bit registers that c ontrol the operations of tmpn. (7) tmpn i/o control registers 0 to 2 (tpnioc0 to tpnioc2) these are 8-bit registers that c ontrol the input and output of tmpn. (8) tmpn option register 0 (tpnopt0) this is an 8-bit register that controls the specif ication of settings such as capture and compare. (9) edge detector this circuit detects the valid edges input to the tipn0 and tipn1 pins. no edge, rising edge, falling edge, or both the rising and falling edges can be selected as the valid edge by using the tpnioc1 and tpnioc2 registers.
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 237 of 1113 sep 22, 2011 (10) output controller this circuit controls the output of the topn0 and top n1 pins. the output controll er is controlled by the tpnioc0 register. (11) selector the selector selects the count clock for the 16-bit counter . one of eight internal clocks or the input of an external event can be selected as the count clock. remark n = 0 to 5 7.2.1 pins used by tmpn the input and output pins used by tmpn are shown in table 7-2 below. when using these pins for tmpn, first set them to port mode. for details, see table 4-15 settings when pins are used for alternate functions . table 7-2. pins used by tmpn pin no. timer channel gf gc f1 port tmp input tmp output alternate function tmp0 29 27 l4 p32 tip00 note1 top00 ascka0/sckb4 30 28 k4 p33 tip01 top01 ? tmp1 31 29 k5 p34 tip10 note1 top10 ? 32 30 j5 p35 tip11 top11 ? tmp2 52 50 j11 p97 tip20 note1 top20 a7/sib1(/rxdc0) note2 51 49 k11 p96 tip21 top21 a6 (/txdc0) note2 tmp3 50 48 k10 p95 tip30 note1 top30 a5 (/rxda5) note2 49 47 l10 p94 tip31 top31 a4 (/txda5) note2 tmp4 48 46 j9 p93 tip40 note1 top40 a3 (/rxda4) note2 47 45 k9 p92 tip41 top41 a2 (/txda4) note2 tmp5 60 58 g8 p915 tip50 note1 top50 a15/intp6 59 57 g9 p914 tip51 top51 a14/intp5 notes1. the tipn0 pin functions as a capture trigger inpu t, as an external event input, and as an external trigger input (n = 0 to 5). 2. pd70f3792, 70f3793, 70f3841, 70f3842 only caution other than alternate function pins above, intua5t interrupt of uart5 and intp3cc1 interrupt of tmp3, and intu a5r interrupt of uart5 and intp3ov interrupt of tmp3 are alternate interrupt signals and therefore cannot be used simultaneously ( pd70f3792, 70f3793, 70f3841, 70f3842 only). remark gf: 100-pin plastic lqfp (14 20) ( pd70f3737, 70f3738 only) gc: 100-pin plastic lqfp (fine-pitch) (14 14) f1: 121-pin plastic fbga (8 8)
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 238 of 1113 sep 22, 2011 7.2.2 interrupts the following three types of interrupt signals are used by tmpn: (1) inttpncc0 this signal is generated when the value of the 16-bit count er matches the value of the ccr0 buffer register, or when a capture signal is input from the tipn0 pin. (2) inttpncc1 this signal is generated when the value of the 16-bit count er matches the value of the ccr1 buffer register, or when a capture signal is input from the tipn1 pin. (3) inttpnov this signal is generated when the 16-bit coun ter overflows after incr ementing up to ffffh.
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 239 of 1113 sep 22, 2011 7.3 registers the registers that control tmpn are as follows. ? tmpn control register 0 (tpnctl0) ? tmpn control register 1 (tpnctl1) ? tmpn i/o control register 0 (tpnioc0) ? tmpn i/o control register 1 (tpnioc1) ? tmpn i/o control register 2 (tpnioc2) ? tmpn option register 0 (tpnopt0) ? tmpn capture/compare register 0 (tpnccr0) ? tmpn capture/compare register 1 (tpnccr1) ? tmpn counter read buffer register (tpncnt) remarks 1. when using the functions of the tip n0, tipn1, topn0, and topn1 pins, see table 4-15 settings when pins are used for alternate functions . 2. n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 240 of 1113 sep 22, 2011 (1) tmpn control register 0 (tpnctl0) the tpnctl0 register is an 8-bit register that controls the operation of tmpn. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. the same value can always be written to the tpnctl0 register by software. tpnce tmpn operation disabled (tmpn reset asynchronously note ). tmpn operation enabled. tmpn operation started. tpnce 0 1 tmpn operation control tpnctl0 (n = 0 to 5) 0 0 0 0 tpncks2 tpncks1 tpncks0 654321 after reset: 00h r/w address: tp0ctl0 fffff590h, tp1ctl0 fffff5a0h, tp2ctl0 fffff5b0h, tp3ctl0 fffff5c0h, tp4ctl0 fffff5d0h, tp5ctl0 fffff5e0h <7> 0 f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 f xx /512 tpncks2 0 0 0 0 1 1 1 1 internal count clock selection n = 0, 2, 4 n = 1, 3, 5 tpncks1 0 0 1 1 0 0 1 1 tpncks0 0 1 0 1 0 1 0 1 note tpnopt0.tpnovf bit, 16-bit counter , timer output (topn0, topn1 pins) cautions 1. set the tpncks2 to tpncks0 bits when the tpnce bit = 0. when the value of the tpnce bi t is changed from 0 to 1, the tpncks2 to tpncks0 bits can be set simultaneously. 2. be sure to clear bits 3 to 6 to ?0?. remark f xx : main clock frequency
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 241 of 1113 sep 22, 2011 (2) tmpn control register 1 (tpnctl1) the tpnctl1 register is an 8-bit register that controls the operation of tmpn. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 tpnest 0 1 software trigger control tpnctl1 (n = 0 to 5) tpnest tpneee 0 0 tpnmd2 tpnmd1 tpnmd0 <6> <5> 4 3 2 1 after reset: 00h r/w address: tp0ctl1 fffff591h, tp1ctl1 fffff5a1h, tp2ctl1 fffff5b1h, tp3ctl1 fffff5c1h, tp4ctl1 fffff5d1h, tp5ctl1 fffff5e1h generate a valid signal for external trigger input. ? in one-shot pulse output mode: a one-shot pulse is output with writing 1 to the tpnest bit as the trigger. ? in external trigger pulse output mode: a pwm waveform is output with writing 1 to the tpnest bit as the trigger. disable operation with external event count input. (perform counting with the internal count clock selected by the tpnctl0.tpnck0 to tpnck2 bits.) tpneee 0 1 count clock selection 7 0 interval timer mode external event count mode external trigger pulse output mode one-shot pulse output mode pwm output mode free-running timer mode pulse width measurement mode setting prohibited tpnmd2 0 0 0 0 1 1 1 1 timer mode selection tpnmd1 0 0 1 1 0 0 1 1 tpnmd0 0 1 0 1 0 1 0 1 enable operation with external event count input. (perform counting at the valid edge of the external event count input signal.) ? cautions 1. the tpnest bit is valid only in the external trigger pulse output mode or the one-shot pulse output mode. in any other mode, writing 1 to this bit is ignored. 2. external event count input is selected in the external event count mode regardless of the value of the tpneee bit. 3. set the tpneee and tpnmd2 to tpnmd0 bits when the timer operation is stopped (tpnctl0.tpnce bit = 0). (the same value can be written when the tpnce bit = 1.) the operation is not guaranteed when rewriting is performed with the tpnce bit = 1. if rewriting was mistakenly performed, clear the tpnce bit to 0 and then set the bits again. 4. be sure to clear bits 3, 4, and 7 to ?0?.
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 242 of 1113 sep 22, 2011 (3) tmpn i/o control register 0 (tpnioc0) the tpnioc0 register is an 8-bit register that contro ls the operation of timer output (topn0, topn1 pins). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 tpnol1 0 1 topn1 pin output level setting note topn1 pin starts output at high level topn1 pin starts output at low level tpnioc0 (n = 0 to 5) 0 0 0 tpnol1 tpnoe1 tpnol0 tpnoe0 6543<2>1 after reset: 00h r/w address: tp0ioc0 fffff592h, tp1ioc0 fffff5a2h, tp2ioc0 fffff5b2h, tp3ioc0 fffff5c2h, tp4ioc0 fffff5d2h, tp5ioc0 fffff5e2h tpnoe1 0 1 topn1 pin output setting timer output disabled ? when tpnol1 bit = 0: low level is output from the topn1 pin ? when tpnol1 bit = 1: high level is output from the topn1 pin tpnol0 0 1 topn0 pin output level setting note topn0 pin starts output at high level topn0 pin starts output at low level tpnoe0 0 1 topn0 pin output setting timer output disabled ? when tpnol0 bit = 0: low level is output from the topn0 pin ? when tpnol0 bit = 1: high level is output from the topn0 pin 7 <0> timer output enabled (a pulse is output from the topn1 pin). timer output enabled (a pulse is output from the topn0 pin). note the output level of the timer out put pin (topnm) specified by the tpnolm bit is shown below (m = 0, 1). tpnce bit topnm output pin 16-bit counter ? when tpnolm bit = 0 tpnce bit topnm output pin 16-bit counter ? when tpnolm bit = 1 cautions 1. rewrite the tpnol1, tpnoe1, tpnol0, and tpnoe0 bits when the tpnctl0.tpnce bit = 0. (the same value can be written when the tpnce bit = 1.) if rewriting was mistakenly performed, clear the tpnce bit to 0 and then set the bits again. 2. even if the tpnolm bit is manipulated when the tpnce and tpnoem bits are 0, the topnm pin output level varies (m = 0, 1).
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 243 of 1113 sep 22, 2011 (4) tmpn i/o control register 1 (tpnioc1) the tpnioc1 register is an 8-bit regi ster that controls t he valid edge of the capture trigger input signals (tipn0, tipn1 pins). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 tpnis3 0 0 1 1 tpnis2 0 1 0 1 capture trigger input signal (tipn1 pin) valid edge setting no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges tpnioc1 (n = 0 to 5) 0 0 0 tpnis3 tpnis2 tpnis1 tpnis0 654321 after reset: 00h r/w address: tp0ioc1 fffff593h, tp1ioc1 fffff5a3h, tp2ioc1 fffff5b3h, tp3ioc1 fffff5c3h, tp4ioc1 fffff5d3h, tp5ioc1 fffff5e3h tpnis1 0 0 1 1 tpnis0 0 1 0 1 capture trigger input signal (tipn0 pin) valid edge setting no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges 7 0 cautions 1. rewrite the tpnis3 to tpnis0 bits when the tpnctl0.tpnce bit = 0. (the same value can be written when the tpnce bit = 1.) if rewriting was mistakenly performed, clear the tpnce bit to 0 and then set the bits again. 2. the tpnis3 to tpnis0 bits are valid only in the free-running timer mode and the pulse width measurement mode. in all other modes, a capture operation is not possible.
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 244 of 1113 sep 22, 2011 (5) tmpn i/o control register 2 (tpnioc2) the tpnioc2 register is an 8-bit regist er that controls the valid edge of the external event count input signal (tipn0 pin) and external trigger input signal (tipn0 pin). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 tpnees1 0 0 1 1 tpnees0 0 1 0 1 external event count input signal (tipn0 pin) valid edge setting no edge detection (external event count invalid) detection of rising edge detection of falling edge detection of both edges tpnioc2 (n = 0 to 5) 0 0 0 tpnees1 tpnees0 tpnets1 tpnets0 654321 after reset: 00h r/w address: tp0ioc2 fffff594h, tp1ioc2 fffff5a4h, tp2ioc2 fffff5b4h, tp3ioc2 fffff5c4h, tp4ioc2 fffff5d4h, tp5ioc2 fffff5e4h tpnets1 0 0 1 1 tpnets0 0 1 0 1 external trigger input signal (tipn0 pin) valid edge setting no edge detection (external trigger invalid) detection of rising edge detection of falling edge detection of both edges 7 0 cautions 1. rewrite the tpnees1 , tpnees0, tpnets1, and tpnets0 bits when the tpnctl0.tpnce bit = 0. (the same value can be written when the tpnce bit = 1.) if rewriting was mistakenly performed, clear the tpnce bit to 0 and then set the bits again. 2. the tpnees1 and tpnees0 bits are valid only when the tpnctl1.tpneee bit = 1 or wh en the external event count mode (tpnctl1.tpnmd2 to tp nctl1.tpnmd0 bits = 001) has been set. 3. the tpnets1 and tpnets0 bits are valid only when the external trigger pulse output mode (tpnctl1.tpnmd2 to tpnctl1.tpnmd0 bits = 010) or the one-shot pulse output mode (tpnctl1.tpnmd2 to tpnctl1.tpnmd0 = 011) is set.
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 245 of 1113 sep 22, 2011 (6) tmpn option register 0 (tpnopt0) the tpnopt0 register is an 8-bit register used to set the capture/ compare operation and indicate the detection of an overflow. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 tpnccs1 0 1 tpnccr1 register capture/compare selection the tpnccs1 bit setting is valid only in the free-running timer mode. compare register selected capture register selected tpnopt0 (n = 0 to 5) 0 tpnccs1 tpnccs0 0 0 0 tpnovf 654321 after reset: 00h r/w address: tp0opt0 fffff595h, tp1opt0 fffff5a5h, tp2opt0 fffff5b5h, tp3opt0 fffff5c5h, tp4opt0 fffff5d5h, tp5opt0 fffff5e5h tpnccs0 0 1 tpnccr0 register capture/compare selection the tpnccs0 bit setting is valid only in the free-running timer mode. compare register selected capture register selected tpnovf 0 1 tmpn overflow detection flag ? the tpnovf bit is set when the 16-bit counter count value overflows from ffffh to 0000h in the free-running timer mode or the pulse width measurement mode. ? an interrupt request signal (inttpnov) is generated at the same time that the tpnovf bit is set to 1. the inttpnov signal is not generated in modes other than the free-running timer mode and the pulse width measurement mode. ? the tpnovf bit is not cleared even when the tpnovf bit or the tpnopt0 register are read when the tpnovf bit = 1. ? the tpnovf bit can be both read and written, but the tpnovf bit cannot be set to 1 by software. writing 1 has no influence on the operation of tmpn. tpnovf bit 0 written or tpnctl0.tpnce bit = 0 overflow occurred 7 <0> cautions 1. rewrite the tpnccs1 and tpnccs0 bits when the tpnce bit = 0. (the same value can be written when the tpnce bit = 1.) if rewriting was mi stakenly performed, clear the tpnce bit to 0 and then set the bits again. 2. be sure to clear bits 1 to 3, 6, and 7 to ?0?.
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 246 of 1113 sep 22, 2011 (7) tmpn capture/compare register 0 (tpnccr0) the tpnccr0 register can be used as a capture register or a com pare register depending on the mode. this register can be selected as a c apture register or a compare register only in the free-running timer mode, according to the setting of the tpnopt0.tpnccs0 bit. in the pulse width measurement mode, the tpnccr0 register can be used only as a capture register . in any other mode, this register can be used only as a compare register. the tpnccr0 register can be r ead or written during operation. this register can be read or written in 16-bit units. reset sets this register to 0000h. caution accessing the tpnccr0 register is prohibi ted in the following statuses. moreover, if the system is in the wait status, the only way to cancel the wait status is to execute a reset. for details, see 3.4.9 (1) accessing speci fic on-chip peripheral i/o registers. ? when the cpu operates on the subclock and main clock oscillation is stopped ? when the cpu operates on th e internal oscillator clock tpnccr0 (n = 0 to 5) 12 10 8 6 4 2 after reset: 0000h r/w address: tp0ccr0 fffff596h, tp1ccr0 fffff5a6h, tp2ccr0 fffff5b6h, tp3ccr0 fffff5c6h, tp4ccr0 fffff5d6h, tp5ccr0 fffff5e6h 14 0 13 11 9 7 5 3 15 1
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 247 of 1113 sep 22, 2011 (a) function as compare register the tpnccr0 register can be rewritten even when the tpnctl0.tpnce bit = 1. the set value of the tpnccr0 register is transferred to the ccr0 buffer register. when the value of the 16-bit counter matches the value of the ccr0 buffer register, a compare match interrupt request signal (inttpncc0) is generated. if topn0 pin output is ena bled at this time, the output of the topn0 pin is inverted (for details, see the descriptions of each operating mode.). when the tpnccr0 register is used as a cycle register in the interval timer mode, external event count mode, external trigger pulse output mode, one-shot pulse output mode, or pwm output mode, the value of the 16-bit counter is cleared (000 0h) if its count value matches the value of the ccr0 buffer register. (b) function as capture register when the tpnccr0 register is used as a capture register in the free- running timer mode, the count value of the 16-bit counter is stored in the tpnccr0 register if the valid ed ge of the capture trigger input pin (tipn0 pin) is detected. in the pulse-width measurement mode, the count value of the 16-bit counter is stored in the tpnccr0 register and the 16-bit counter is cleared (0000h ) if the valid edge of the capture trigger input pin (tipn0) is detected. even if the capture operation and reading the tpnccr0 register co nflict, the correct value of the tpnccr0 register can be read. the following table shows the functions of the capture/compar e register in each mode, and how to write data to the compare register. table 7-3. function of capture/co mpare register in each mode a nd how to write compare register operation mode capture/compare register how to write compare register interval timer compare register anytime write external event counter compare register anytime write external trigger pulse output compare register batch write one-shot pulse output compare register anytime write pwm output compare register batch write free-running timer capture/compare register anytime write pulse width measurement capture register ? remark for details about anytime write and batch write, see 7.4 (2) anytime write and batch write .
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 248 of 1113 sep 22, 2011 (8) tmpn capture/compare register 1 (tpnccr1) the tpnccr1 register can be used as a capture register or a com pare register depending on the mode. this register can be selected as a c apture register or a compare register only in the free-running timer mode, depending on the setting of the tpnopt0.tpnccs1 bi t. in the pulse width measurement mode, the tpnccr1 register can be used only as a capture register . in any other mode, this register can be used only as a compare register. the tpnccr1 register can be r ead or written during operation. this register can be read or written in 16-bit units. reset sets this register to 0000h. caution accessing the tpnccr1 register is prohibi ted in the following statuses. moreover, if the system is in the wait status, the only way to cancel the wait status is to execute a reset. for details, see 3.4.9 (1) accessing speci fic on-chip peripheral i/o registers. ? when the cpu operates on the subclock and main clock oscillation is stopped ? when the cpu operates on th e internal oscillator clock tpnccr1 (n = 0 to 5) 12 10 8 6 4 2 after reset: 0000h r/w address: tp0ccr1 fffff598h, tp1ccr1 fffff5a8h, tp2ccr1 fffff5b8h, tp3ccr1 fffff5c8h, tp4ccr1 fffff5d8h, tp5ccr1 fffff5e8h 14 0 13 11 9 7 5 3 15 1
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 249 of 1113 sep 22, 2011 (a) function as compare register the tpnccr1 register can be rewritten even when the tpnctl0.tpnce bit = 1. the set value of the tpnccr1 register is transferred to the ccr1 buffer register. when the value of the 16-bit counter matches the value of the ccr1 buffer register, a compare match interrupt request signal (inttpncc1) is generated. if topn1 pin output is ena bled at this time, the output of the topn1 pin is inverted (for details, see the descriptions of each operating mode.). (b) function as capture register when the tpnccr1 register is used as a capture register in the free- running timer mode, the count value of the 16-bit counter is stored in the tpnccr1 register if the valid ed ge of the capture trigger input pin (tipn1 pin) is detected. in the pulse-width measurement mode, the count value of the 16-bit counter is stored in the tpnccr1 register and the 16-bit counter is cleared (0000h ) if the valid edge of the capture trigger input pin (tipn1) is detected. even if the capture operation and reading the tpnccr1 register co nflict, the correct value of the tpnccr1 register can be read. the following table shows the functions of the capture/compar e register in each mode, and how to write data to the compare register. table 7-4. function of capture/co mpare register in each mode a nd how to write compare register operation mode capture/compare register how to write compare register interval timer compare register anytime write external event counter compare register anytime write external trigger pulse output compare register batch write one-shot pulse output compare register anytime write pwm output compare register batch write free-running timer capture/compare register anytime write pulse width measurement capture register ? remark for details about anytime write and batch write, see 7.4 (2) anytime write and batch write .
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 250 of 1113 sep 22, 2011 (9) tmpn counter read buffer register (tpncnt) the tpncnt register is a read buffer register from which the count value of the 16-bit counter can be read. if this register is read when the tpnctl0.tpnce bit = 1, the count value of the 16-bit timer can be read. this register is read-only, in 16-bit units. the value of the tpncnt register is cleared to 0000h when the tpnce bit = 0. if the tpncnt register is read at this time, the value of the 16-bit c ounter (ffffh) is not read, but 0000h is read. because the tpnce bit is cleared to 0, the value of the tpncnt register is cleared to 0000h after reset. caution accessing the tpncnt register is prohibited in the following statuses. moreover, if the system is in the wait status, the only way to cancel the wait status is to execute a reset. for details, see 3.4.9 (1) accessing speci fic on-chip peripheral i/o registers. ? when the cpu operates on the subclock and main clock oscillation is stopped ? when the cpu operates on th e internal oscillator clock tpncnt (n = 0 to 5) 12 10 8 6 4 2 after reset: 0000h r address: tp0cnt fffff59ah, tp1cnt fffff5aah, tp2cnt fffff5bah, tp3cnt fffff5cah, tp4cnt fffff5dah, tp5cnt fffff5eah 14 0 13 11 9 7 5 3 15 1
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 251 of 1113 sep 22, 2011 7.4 operations tmpn can execute the following operations: table 7-5. tmpn operating modes operating mode tpnctl1.tpnest bit (software trigger bit) tipn0 pin (external trigger input) capture/compare register setting compare register write count clock interval timer mode invalid invalid compare only anytime write internal/external external event count mode note 1 invalid invalid compare only anytime write external external trigger pulse output mode note 2 valid valid compare only batch write internal one-shot pulse output mode note 2 valid valid compare only anytime write internal pwm output mode invalid invalid compare only batch write internal/external free-running timer mode invalid invalid can be switched anytime write internal/external pulse width measurement mode note 2 invalid invalid capture only not applicable internal notes 1. when using the external event count mode, specify th at the valid edge of the tipn0 pin capture trigger input is not detected (by clearing the tpnioc 1.tpnis1 and tpnioc1.tpnis0 bits to 0). 2. when using the external trigger pulse output m ode, one-shot pulse output mode, and pulse width measurement mode, select the internal clock as t he count clock (by clearing the tpnctl1.tpneee bit to 0). remark n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 252 of 1113 sep 22, 2011 (1) basic counter operation the basic operation of the 16-bit c ounter is described below. for more details, see the descriptions of each operating mode. (a) starting counting tmpn starts counting from ffffh in all opera ting modes, and increments as follows: ffffh, 0000h, 0001h, 0002h, 0003h?. (b) clearing tmpn tmpn is cleared to 0000h when its value matches the value of the compare register or when the value of tmpn is captured upon the input of a valid capture trigger signal. note that when tmpn increments from ffffh to 000 0h immediately after it starts counting and following an overflow, it does not mean that tmpn has been cleared. consequently, the inttpncc0 and inttpncc1 interrupts are not generated in this case. (c) overflow tmpn overflows after it increments from ffffh to 0000h in free-running timer mode and pulse width measurement mode. an overflow sets the tpnopt 0.tpnovf bit to 1 and generates an interrupt request signal (inttpnov). note that inttpnov will not be generated in the following cases: ? when tmpn has just started counting. ? when the compare value at which tmpn is cleared is specified as ffffh. ? in pulse width measurement mode, when tmpn increments from ffffh to 0000h after being cleared when its value of ffffh was captured. caution after the inttpnov overflow interrupt request signal occurs, be sure to confirm that the overflow flag (tpnovf) is set to 1. (d) reading tmpn while it is incrementing tmpn can be read while it is incrementing by using the tpncnt register. specifically, the value of tmpn can be read by read ing the tpncnt register while the tpnclt0.tpnce bit is 1. note, however, that when the tpnclt0.tp nce bit is 0, the value of tmpn is always ffffh and the value of the tpncnt register is always 0000h. remark n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 253 of 1113 sep 22, 2011 /(2) anytime write and batch write the tpnccr0 and tpnccr1 registers can be written ev en while tmpn is operating (that is, while the tpnctl0.tpnce bit is 1), but the way the ccr0 and ccr1 buffer registers are written differs depending on the mode. the two writing methods ar e anytime write and batch write. (a) anytime write this writing method is used to transfer data from the tpnccr0 and tpnccr1 registers to the ccr0 and ccr1 buffer registers any time while tmpn is operating. figure 7-2. flowchart showing basic anytime write operation start inttpncc1 signal generated ? set value to tpnccra register ? enable timer (tpnce bit = 1) value of tpnccra register transferred to ccra buffer register rewrite tpnccra register new value transferred to ccra buffer register timer operation ? 16-bit counter value matches value of ccr1 buffer register note ? 16-bit counter value matches value of ccr0 buffer register ? 16-bit counter cleared and starts incrementing again inttpncc0 signal generated initial settings note the 16-bit counter is only cleared when its value matches the value of the ccr0 buffer register, not the ccr1 buffer register. remarks 1. the flowchart applies to the case when tmpn is being used as an interval timer. 2. a = 0, 1 n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 254 of 1113 sep 22, 2011 figure 7-3. anytime write timing d 01 d 01 d 01 d 01 0000h ffffh 0000h tpnce bit = 1 d 02 d 02 d 11 d 11 d 11 d 12 d 12 d 12 d 02 d 11 0000h d 12 16-bit counter tpnccr0 register tpnccr1 register inttpncc0 signal inttpncc1 signal ccr0 buffer register ccr1 buffer register remarks 1. d 01 , d 02 : set value of tpnccr0 register d 11 , d 12 : set value of tpnccr1 register 2. the flowchart applies to the case when tmp is being used as an interval timer. 3. n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 255 of 1113 sep 22, 2011 (b) batch write this writing method is used to transfer data from the tpnccr0 and tpnccr1 registers to the ccr0 and ccr1 buffer registers all at once while tmpn is opera ting. the data is transferred when the value of the 16-bit counter matches the value of the ccr0 buffer register. transfer is enabled by writing to the tpnccr1 register. whether transfer of the next data is enabled or not depends on whether the tpnccr1 register has been written. to specify the value of the rewr itten tpnccr0 and tpnccr1 register s as the 16-bit counter compare value (that is, the value to be transferred to the ccr 0 and ccr1 buffer registers), the tpnccr0 register must be rewritten before the value of the 16-bit count er matches the value of the ccr0 buffer register, and then the tpnccr1 register must be written. t he value of the tpnccr0 and tpnccr1 registers is then transferred to the ccr0 and ccr1 buffer registers when the value of the 16-bit counter matches the value of the ccr0 buffer register. note that even if you wish to rewrite only the tpnccr0 register value, you must also write the same value to the tpnccr1 r egister (that is, the same value as the value already specified for the tpnccr1 register). remark n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 256 of 1113 sep 22, 2011 figure 7-4. flowchart showin g basic batch write operation start batch write enabled ? set value to tpnccra register ? enable timer (tpnce bit = 1) value of tpnccra register transferred to ccra buffer register rewrite tpnccr0 register rewrite tpnccr1 register timer operation ? 16-bit counter value matches value of ccr1 buffer register note ? 16-bit counter value matches value of ccr0 buffer register ? 16-bit counter cleared and starts incrementing again ? tpnccra register value transferred to ccra buffer register inttpncc0 signal generated inttpncc1 signal generated initial settings note the 16-bit counter is only cleared when its value matches the value of the ccr0 buffer register, not the ccr1 buffer register. caution the process of writing to the tpnccr1 re gister includes enabling batch write. it is therefore necessary to rewrite the tpnccr 1 register after rewriting the tpnccr0 register. remarks 1. the flowchart applies to the case when tm pn is being used in the pwm output mode. 2. a = 0, 1 n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 257 of 1113 sep 22, 2011 figure 7-5. batch write timing d 01 d 01 d 02 d 03 0000h ffffh 0000h d 01 d 11 d 12 d 12 d 02 d 03 0000h d 11 d 12 d 12 tpnce bit = 1 d 02 d 02 d 03 d 11 d 12 d 12 d 12 d 12 16-bit counter tpnccr0 register tpnccr1 register inttpncc0 signal inttpncc1 signal ccr0 buffer register ccr1 buffer register topn0 pin output topn1 pin output note 1 note 1 note 1 note 1 note 2 note 3 write the same value notes 1. d 03 is not transferred because the tpn ccr1 register was not written. 2. d 12 is transferred to the ccr1 buffer register upon a match with the tpnccr0 register value (d 01 ) because the tpnccr1 register was written (d 12 ). 3. d 12 is transferred to the ccr1 buffer register upon a match with the tpnccr0 register value (d 02 ) because the tpnccr1 register was written (d 12 ). remarks 1. d 01 , d 02 , d 03 : set value of tpnccr0 register d 11 , d 12 : set value of tpnccr1 register 2. the flowchart applies to the case when tmpn is being used as in the pwm output mode. 3. n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 258 of 1113 sep 22, 2011 7.4.1 interval timer mode (t pnmd2 to tpnmd0 bits = 000) in the interval timer mode, setting the tpnctl0.tpnc e bit to 1 generates an interrupt request signal (inttpncc0) at a specified interval. setting the tpnce bi t to 1 can also start the timer, which then outputs a square wave whose half cycle is equal to the interval from the topn0 pin. usually, the tpnccr1 register is not used in the interval ti mer mode. mask interrupts from this register by setting the interrupt mask flag (tpnccmk1). remarks 1. for how to set the topn0 pin, see table 7-2 pins used by tmpn and table 4-15 settings when pins are used for alternate functions . 2. for how to enable the inttpncc0 interrupt signal, see chapter 21 interrupt servicing/ exception processing . 3. n = 0 to 5 figure 7-6. configuration of interval timer 16-bit counter output controller ccr0 buffer register tpnce bit tpnccr0 register count clock selection clear match signal topn0 pin inttpncc0 signal remark n = 0 to 5 figure 7-7. basic timing of op eration in interval timer mode ffffh 16-bit counter 0000h tpnce bit topn0 pin output inttpncc0 signal d 0 d 0 d 0 d 0 d 0 interval (d 0 + 1) interval (d 0 + 1) interval (d 0 + 1) interval (d 0 + 1) tpnccr0 register (ccr0 buffer register) remark n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 259 of 1113 sep 22, 2011 when the tpnce bit is set to 1, the value of the 16-bit counter is cleared from ffffh to 0000h in synchronization with the count clock, and the counter star ts incrementing. at this time, the output of the topn0 pin is inverted and the set value of the tpnccr0 register is transferred to the ccr0 buffer register. when the value of the 16-bit counter ma tches the value of the ccr0 buffer r egister, the 16-bit counter is cleared to 0000h, the output of the to pn0 pin is inverted, and a compare match interrupt request signal (inttpncc0) is generated. the interval can be calculated by using the following expression: interval = (set value of tpnccr0 register + 1) count clock cycle an example of the register settings when the interval timer mode is used is shown in the figure below. remark n = 0 to 5 figure 7-8. register settings in interval timer mode (1/2) (a) tmpn control register 0 (tpnctl0) 0/1 0 0 0 0 tpnctl0 these bits select the count clock. 0: stop counting 1: enable counting 0/1 0/1 0/1 tpncks2 tpncks1 tpncks0 tpnce (b) tmpn control register 1 (tpnctl1) 0 0 0/1 note 00 tpnctl1 0, 0, 0: interval timer mode 0: increment tmpn based on the count clock selected by the tpncks0 to tpncks2 bits. 1: increment tmpn based on the input of an external event count signal. 000 tpnmd2 tpnmd1 tpnmd0 tpneee tpnest note the tpneee bit can only be set to 1 when the time r output (topn1) is used. note that when setting the tpneee bit to 1, the tpnccr0 and tpn ccr1 registers must be set to the same value (that is, the same value as the value already s pecified for these registers). (for details, see 7.4.1 (2) (d) operation of tpnccr1 register. )
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 260 of 1113 sep 22, 2011 figure 7-8. register settings in interval timer mode (2/2) (c) tmpn i/o control register 0 (tpnioc0) 0 0 0 0 0/1 tpnioc0 0: disable topn0 pin output. 1: enable topn0 pin output. output level when topn0 pin is disabled: 0: low level 1: high level 0: disable topn1 pin output. 1: enable topn1 pin output. output level when topn1 pin is disabled: 0: low level 1: high level 0/1 0/1 0/1 tpnoe1 tpnol0 tpnoe0 tpnol1 (d) tmpn i/o control register 2 (tpnioc2) 0 0 0 0 0/1 note tpnioc2 these bits select the valid edge of the external event count input (tipn0 pin). 0/1 note 00 tpnees0 tpnets1 tpnets0 tpnees1 note the tpnees1 and tpnees0 bits can only be set to 1 when the timer output (topn1) is used. note that when setting these bits to 1, the tpnccr0 and tpnccr1 registers must be set to the same value (that is, the same value as the va lue already specified for these registers). (e) tmpn counter read buffer register (tpncnt) the value of the 16-bit counter can be read by reading this register. (f) tmpn capture/compare register 0 (tpnccr0) if the tpnccr0 register is set to d 0 , the interval is as follows: interval = (d 0 + 1) count clock cycle (g) tmpn capture/compare register 1 (tpnccr1) usually, the tpnccr1 register is not used in the in terval timer mode. however, because the set value of the tpnccr1 register is transferred to the ccr1 buffer register and a compare match interrupt request signal (inttpncc1) is generated when the val ue of the 16-bit counter ma tches the value of the ccr1 buffer register, interrupts from this register must be masked by setting the interrupt mask flag (tpnccmk1). remarks 1. tmpn i/o control register 1 (tpnioc1) and tmpn option register 0 (tpnopt0) are not used in the interval timer mode. 2. n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 261 of 1113 sep 22, 2011 (1) operations in interval timer mode figure 7-9. timing and processing of operations in interval timer mode ffffh 16-bit counter 0000h tpnce bit topn0 pin output inttpncc0 signal d 0 d 0 d 0 d 0 <1> <2> tpnce bit = 1 tpnce bit = 0 set up the registers tpnctl0 register (tpncks0 to tpncks2 bits) tpnctl1 register tpnioc0 register tpnccr0 register be sure to set up these registers before setting the tpnce bit to 1. counting starts. the tpncks0 to tpncks2 bits can be set here. when counting is disabled (tpnce bit = 0), the counter is reset and counting stops. start stop <1> starting counting <2> stopping counting tpnccr0 register (ccr0 buffer register) remark n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 262 of 1113 sep 22, 2011 (2) using interval timer mode (a) operation when tpnccr0 register is set to 0000h when the tpnccr0 register is set to 0000h, the inttp ncc0 signal is generated each count clock cycle from the second clock cycle, and the output of the topn0 pin is inverted. the value of the 16-bit counter is always 0000h. figure 7-10. operation of interval time r when tpnccr0 register is set to 0000h count clock 16-bit counter tpnce bit tpnccr0 register topn0 pin output inttpncc0 signal 0000h interval time count clock cycle interval time count clock cycle ffffh 0000h 0000h 0000h 0000h remark n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 263 of 1113 sep 22, 2011 (b) operation when tpnccr0 re gister is set to ffffh when the tpnccr0 register is set to ffffh, the 16-bi t counter increments up to ffffh and is reset to 0000h in synchronization with the next increment timing. the inttpncc0 signal is then generated and the output of the topn0 pin is inverted. at this time, an overflow interrupt request signal (inttpnov) is not generated, nor is the overflow fl ag (tpnopt0.tpnovf bit) set to 1. figure 7-11. operation of interval timer when tpnccr0 register is set to ffffh ffffh 16-bit counter 0000h tpnce bit topn0 pin output inttpncc0 signal ffffh interval time 10000h count clock cycle interval time 10000h count clock cycle interval time 10000h count clock cycle tpnccr0 register (ccr0 buffer register) remark n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 264 of 1113 sep 22, 2011 (c) notes on rewriting tpnccr0 register when rewriting the value of the tp nccr0 register to a smaller valu e, stop counting first and then change the set value. if the value of the tpnccr0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. figure 7-12. rewriting tpnccr0 register ffffh 16-bit counter 0000h tpnce bit tpnol0 bit topn0 pin output inttpncc0 signal d 1 d 2 d 1 d 1 d 2 d 2 d 2 l interval time (1) interval time (ng) interval time (2) tpnccr0 register (ccr0 buffer register) remarks 1. interval time (1): (d 1 + 1) count clock cycle interval time (ng): (10000h + d 2 + 1) count clock cycle interval time (2): (d 2 + 1) count clock cycle 2. n = 0 to 5 if the value of the tpnccr0 register is changed from d 1 to d 2 while the counter value is greater than d 2 but less than d 1 , the tpnccr0 register value is transferred to the ccr0 buffer register as soon as the register has been rewritten. consequently, the val ue that is compared with the 16-bit counter value is d 2 . because the counter value has already exceeded d 2 , however, the 16-bit counter counts up to ffffh, overflows, and then counts up again from 0000h. when the counter value matches d 2 , the inttpncc0 signal is generated and the output of the topn0 pin is inverted. therefore, the inttpncc0 signal may not be generated at the interval ?(d 1 + 1) count clock cycle? or ?(d 2 + 1) count clock cycle? as originally expected, but instead may be generated at an interval of ?(10000h + d 2 + 1) count clock cycle?.
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 265 of 1113 sep 22, 2011 (d) operation of tpnccr1 register the tpnccr1 register is configured as follows in the interval timer mode. figure 7-13. configuration of tpnccr1 register ccr0 buffer register tpnccr0 register tpnccr1 register ccr1 buffer register topn0 pin inttpncc0 signal topn1 pin inttpncc1 signal 16-bit counter output controller tpnce bit count clock selection clear match signal output controller match signal remark n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 266 of 1113 sep 22, 2011 if the value of the tpnccr1 register is less than or equal to the va lue of the tpnccr0 register, the inttpncc1 signal is generated once per cycle. at the same time, the output of the topn1 pin is inverted. the topn1 pin outputs a sq uare wave with the same cycle as that output by the topn0 pin but with a different phase. a chart showing the timing of operations wh en the value of the tpnccr1 register (d 11 ) is less than or equal to the value of the tpnccr0 register (d 01 ) is shown below. figure 7-14. timing of operations when d 01 d 11 ffffh 16-bit counter 0000h tpnce bit topn0 pin output inttpncc0 signal tpnccr1 register topn1 pin output inttpncc1 signal d 01 d 11 d 01 d 11 d 11 d 11 d 11 d 01 d 01 d 01 tpnccr0 register (ccr0 buffer register) remark n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 267 of 1113 sep 22, 2011 if the value of the tpnccr1 register is greater than the value of the tpnccr0 register, the value of the 16-bit counter will not match the value of the tpnccr1 register. consequently, the inttpncc1 signal is not generated, nor is the out put of the topn1 pin changed. a chart showing the timing of operations wh en the value of the tpnccr1 register (d 11 ) is greater than the value of the tpnccr0 register (d 01 ) is shown below. figure 7-15. timing of operations when d 01 < d 11 ffffh 16-bit counter 0000h tpnce bit topn0 pin output inttpncc0 signal tpnccr1 register topn1 pin output inttpncc1 signal d 01 d 11 d 01 d 01 d 01 d 01 l tpnccr0 register (ccr0 buffer register) remark n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 268 of 1113 sep 22, 2011 (3) operation of interval timer b ased on input of external event count (a) operation when the 16-bit counter is incrementi ng based on the valid edge of the external count input (tipn0 pin) in the interval timer mode, one external event count va lid edge must be input immediately after the tpnce bit changes from 0 to 1 to start t he counter incrementing afte r the 16-bit counter is cleared from ffffh to 0000h. once the tpnccr0 and tpnccr1 registers are set to 0001h (that is, the same value as was previously set), the topn1 pin output is inverted every two counts of the 16-bit counter. note that the tpnctl1.tpneee bit can only be set to 1 when timer output (topn1) is used based on the input of an external event count. figure 7-16. operation of interval timer b ased on input of external event count (tipn0) tpnce bit tpnccr0 register tpnccr1 register topn1 pin output 16-bit counter ffffh 0000h 0001h 0001h 0001h 0001h 0001h 0001h 0001h 0001h 0001h 3 external event counts 2 external event counts 2 external event counts 2-count width 2-count width 2-count width external event count input (tipn0 pin input) remark n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 269 of 1113 sep 22, 2011 7.4.2 external event count mode (tpnmd2 to tpnmd0 bits = 001) in the external event count mode, the valid edge of the external event count input is counted when the tpnctl0.tpnce bit is set to 1, and an interrupt request signal (inttpncc0) is generated each time the specified number of edges have been counted. the timer output pins (topn0 and topn1) cannot be used. to use the topn1 pin in the external event count mode, first set the tpnctl1.tpneee bit to 1 in the interval timer mode (see 7.4.1 (3) operation of interval timer based on input of external event count ). usually, the tpnccr1 register is not us ed in the external event count mode. remarks 1. for how to set the tipn0 pin, see table 7-2 pins used by tmpn and table 4-15 settings when pins are used for alternate functions . 2. for how to enable the inttpncc0 interrupt signal, see chapter 21 interrupt servicing/ exception processing . figure 7-17. configuration of interval timer in external event count mode 16-bit counter ccr0 buffer register tpnce bit tpnccr0 register edge detector clear match signal inttpncc0 signal tipn0 pin (external event count input) remark n = 0 to 5 when the tpnce bit is set to 1, the value of the 16-bi t counter is cleared from ffffh to 0000h. the counter increments each time the valid edge of the external event count input is detected, a nd the value of the tpnccr0 register is transferred to the ccr0 buffer register. when the value of the 16-bit counter ma tches the value of the ccr0 buffer r egister, the 16-bit counter is cleared to 0000h, and a compare match interrupt request signal (inttpncc0) is generated. the inttpncc0 signal is generated each time the valid ed ge of the external event c ount input has been detected the specified number of times (that is, the value of the tpnccr0 register + 1).
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 270 of 1113 sep 22, 2011 figure 7-18. basic timing of operati ons in external event count mode ffffh 16-bit counter 0000h tpnce bit inttpncc0 signal d 0 d 0 d 0 d 0 16-bit counter inttpncc0 signal external event count input (tipn0 pin input) d 0 external event count interval (d 0 + 1) d 0 ? 1d 0 0000 0001 external event count interval (d 0 + 1) external event count interval (d 0 + 1) tpnccr0 register (ccr0 buffer register) tpnccr0 register (ccr0 buffer register) remarks 1. this figure shows the basic timing when the ri sing edge is specified as the valid edge of the external event count input. 2. n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 271 of 1113 sep 22, 2011 an example of the register settings when the external ev ent count mode is used is shown in the figure below. figure 7-19. register settings in external event count mode (1/2) (a) tmpn control register 0 (tpnctl0) 0/1 0 0 0 0 tpnctl0 0: stop counting 1: enable counting 000 tpncks2 tpncks1 tpncks0 tpnce (b) tmpn control register 1 (tpnctl1) 00000 tpnctl1 0, 0, 1: external event count mode 001 tpnmd2 tpnmd1 tpnmd0 tpneee tpnest (c) tmpn i/o control register 0 (tpnioc0) 00000 tpnioc0 0: disable topn0 pin output 0: disable topn1 pin output 000 tpnoe1 tpnol0 tpnoe0 tpnol1 (d) tmpn i/o control register 2 (tpnioc2) 0 0 0 0 0/1 tpnioc2 these bits select the valid edge of the external event count input. 0/1 0 0 tpnees0 tpnets1 tpnets0 tpnees1 remark n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 272 of 1113 sep 22, 2011 figure 7-19. register settings in external event count mode (2/2) (e) tmpn counter read buffer register (tpncnt) the value of the 16-bit counter can be read by reading this register. (f) tmpn capture/compare register 0 (tpnccr0) when the tpnccr0 register is set to d 0 , the counter is cleared and a compare match interrupt request signal (inttpncc0) is generated when the number of external events reaches (d 0 + 1). (g) tmpn capture/compare register 1 (tpnccr1) the tpnccr1 register is not usually used in the ex ternal event count mode. however, because the set value of the tpnccr1 register is transferred to the ccr1 buffer register and a compare match interrupt request signal (inttpncc1) is generated when the value of the 16-bit counter matches the value of the ccr1 buffer register, interrupts from th is register must be masked by setting the interrupt mask flag (tpnccmk1). cautions 1. do not set the tpnccr0 regist er to 0000h in the external event count mode. 2. timer output cannot be used in the external event count mode. when using the timer output based on the input of an ext ernal event count, first set the operating mode to interval mode, an d then specify ?operation enabled? for the external event count input (by setting the tpnctl1.tpnm d2 to tpnmd0 bits to 0, 0, 0 and setting the tpnctl1.tpneee bit to 1). for details, see 7.4.1 (3) operation of interval timer based on i nput of external event count. remarks 1. tmpn i/o control register 1 (tpnioc1) and tmpn option register 0 (tpnopt0) are not used in the external event count mode. 2. n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 273 of 1113 sep 22, 2011 (1) operations in external event count mode figure 7-20. timing and processing of oper ations in external event count mode ffffh 16-bit counter 0000h tpnce bit inttpncc0 signal d 0 d 0 d 0 d 0 <1> <2> tpnce bit = 1 tpnce bit = 0 set up the registers tpnctl0 register (tpncks0 to tpncks2 bits) tpnctl1 register tpnioc0 register tpnioc2 register tpnccr0 register be sure to set up these registers before setting the tpnce bit to 1. counting starts. the tpncks0 to tpncks2 bits can be set here. when counting is disabled (tpnce bit = 0), the counter is reset and counting stops. start stop <1> starting counting <2> stopping counting tpnccr0 register (ccr0 buffer register) remark n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 274 of 1113 sep 22, 2011 (2) using external event count mode (a) operation when tpnccr0 re gister is set to ffffh when the tpnccr0 register is set to ffffh, the 16 -bit counter increments up to ffffh upon detection of the valid edge of the external event count signal and is reset to 0000h in synchronization with the next increment timing. the inttpncc0 signal is then gene rated. at this time, the tpnopt0.tpnovf bit is not set to 1. figure 7-21. operation when tpn ccr0 register is set to ffffh ffffh 16-bit counter 0000h tpnce bit inttpncc0 signal ffffh external event count signal interval external event count signal interval external event count signal interval tpnccr0 register (ccr0 buffer register) remark n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 275 of 1113 sep 22, 2011 (b) notes on rewriting tpnccr0 register when rewriting the value of the tp nccr0 register to a smaller valu e, stop counting first and then change the set value. if the value of the tpnccr0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. figure 7-22. rewriting tpnccr0 register ffffh 16-bit counter 0000h tpnce bit inttpncc0 signal d 1 d 2 d 1 d 1 d 2 d 2 d 2 external event count signal interval (1) (d 1 + 1) external event count signal interval (ng) (10000h + d 2 + 1) external event count signal interval (2) (d 2 + 1) tpnccr0 register (ccr0 buffer register) remark n = 0 to 5 if the value of the tpnccr0 register is changed from d 1 to d 2 while the counter value is greater than d 2 but less than d 1 , the tpnccr0 register value is transferred to the ccr0 buffer register as soon as the register has been rewritten. consequently, the val ue that is compared with the 16-bit counter value is d 2 . because the counter value has already exceeded d 2 , however, the 16-bit counter increments up to ffffh, overflows, and then increment s up again from 0000 h. when the counter value matches d 2 , the inttpncc0 signal is generated. therefore, the inttpncc0 signal may not be generate d at the valid edge of the external event count signal when the external event count is ?(d 1 + 1)? or ?(d 2 + 1)? as originally expected, but instead may be generated at the valid edge of the external event count signal when the external event count is ?(10000h + d 2 + 1)?.
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 276 of 1113 sep 22, 2011 (c) operation of tpnccr1 register the tpnccr1 register is configured as fo llows in the external event count mode. figure 7-23. configuration of tpnccr1 register ccr0 buffer register tpnce bit tpnccr0 register 16-bit counter tpnccr1 register ccr1 buffer register clear match signal match signal inttpncc0 signal inttpncc1 signal edge detector tipn0 pin remark n = 0 to 5 if the value of the tpnccr1 register is less than or equal to the va lue of the tpnccr0 register, the inttpncc1 signal is generated once per cycle. a chart showing the timing of operations wh en the value of the tpnccr1 register (d 11 ) is less than or equal to the value of the tpnccr0 register (d 01 ) is shown below. figure 7-24. timing of operations when d 01 d 11 ffffh 16-bit counter 0000h tpnce bit inttpncc0 signal tpnccr1 register inttpncc1 signal d 01 d 11 d 01 d 11 d 11 d 11 d 11 d 01 d 01 d 01 tpnccr0 register (ccr0 buffer register) remark n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 277 of 1113 sep 22, 2011 if the value of the tpnccr1 register is greater than the value of the tpnccr0 register, the value of the 16-bit counter will not match the value of the tpnccr1 register and the inttpncc1 signal will not be generated. a chart showing the timing of operations wh en the value of the tpnccr1 register (d 11 ) is greater than the value of the tpnccr0 register (d 01 ) is shown below. figure 7-25. timing of operations when d 01 < d 11 ffffh 16-bit counter 0000h tpnce bit inttpncc0 signal tpnccr1 register inttpncc1 signal d 01 d 11 d 01 d 01 d 01 d 01 l tpnccr0 register (ccr0 buffer register) remark n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 278 of 1113 sep 22, 2011 7.4.3 external trigger pulse output m ode (tpnmd2 to tpnmd0 bits = 010) in the external trigger pulse output mode, when the tpnct l0.tpnce bit is set to 1, tmpn waits for a trigger, which is the valid edge of the external trigger input sig nal, and starts incrementing when this trigger is detected. tmpn then outputs a pwm waveform from the topn1 pin. pulses can also be output by generating a software trigger instead of using the external trigger. when using a software trigger instead of the external trigger, a square wave that has one cycle of the pwm waveform as half its cycle can also be output from the topn0 pin. remarks 1. for how to set the tipn0, topn0, and topn1 pins, see table 7-2 pins used by tmpn and table 4-15 settings when pins ar e used for alternate functions . 2. for how to enable the inttpncc0 and inttpncc1 interrupt signals, see chapter 21 interrupt servicing/exception processing . figure 7-26. configuration of tmp in external trigger pulse output mode s r ccr0 buffer register tpnce bit tpnccr0 register 16-bit counter tpnccr1 register ccr1 buffer register clear match signal match signal inttpncc0 signal output controller (rs-ff) output controller (toggle) topn1 pin inttpncc1 signal topn0 pin count clock selection count start control edge detector software trigger generation tipn0 pin transfer transfer remark n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 279 of 1113 sep 22, 2011 figure 7-27. basic timing of operations in external trigger pulse output mode d 1 d 0 d 0 d 1 d 1 d 1 d 1 d 0 d 0 ffffh 16-bit counter 0000h tpnce bit inttpncc0 signal topn0 pin output note inttpncc1 signal topn1 pin output external trigger input (tipn0 pin input) wait for trigger active level width (d 1 ) cycle (d 0 + 1) cycle (d 0 + 1) cycle (d 0 + 1) active level width (d 1 ) active level width (d 1 ) tpnccr0 register (ccr0 buffer register) tpnccr1 register (ccr1 buffer register) note the output from the topn0 pin c an also be used as the input to the tipn0 pin. when using the output from the topn0 pin as the input to the tipn0 pin, use a so ftware trigger instead of an external trigger. when the tpnce bit is set to 1, tmpn waits for a trigger. when the trigger is generat ed, the 16-bit counter is cleared from ffffh to 0000h, starts in crementing, and outputs a pw m waveform from the topn1 pin. if the trigger is generated again while the counter is incrementing, the counter is cleared to 0000h and restarts incrementing, and the output of the topn0 pin is inve rted. (the topn1 pin outputs a high le vel signal regardless of the status (high/low) when a trigger occurs.) the active level width, cycle, and duty factor of the pwm waveform can be calculated as follows. active level width = (set value of tpnccr1 register) count clock cycle cycle = (set value of tpnccr0 register + 1) count clock cycle duty factor = (set value of tpnccr1 regist er)/(set value of tpnccr0 register + 1) the inttpncc0 compare match interrupt request signal is generated when the 16-bit counter increments next time after its value matches the value of the ccr0 buffer register, and the 16-bit counter is cleared to 0000h. the inttpncc1 compare match interrupt request signal is gener ated when the value of the 16-bit counter matches the value of the ccr1 buffer register. either the valid edge of the external trigger input signal or setting the software trigger (tpnctl1.tpnest bit) to 1 is used as the trigger. remark n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 280 of 1113 sep 22, 2011 figure 7-28. register settings in exte rnal trigger pulse output mode (1/2) (a) tmpn control register 0 (tpnctl0) 0/1 0 0 0 0 tpnctl0 these bits select the count clock. 0: stop counting 1: enable counting. 0/1 0/1 0/1 tpncks2 tpncks1 tpncks0 tpnce (b) tmpn control register 1 (tpnctl1) 0 0/1 0 0 0 tpnctl1 writing 1 generates a software trigger. 010 tpnmd2 tpnmd1 tpnmd0 tpneee tpnest 0, 1, 0: external trigger pulse output mode (c) tmpn i/o control register 0 (tpnioc0) 0 0 0 0 0/1 tpnioc0 0: disable topn0 pin output 1: enable topn0 pin output output level when topn0 pin is disabled: 0: low level 1: high level 0: disable topn1 pin output. 1: enable topn1 pin output. active level of topn1 pin output: 0: high level 1: low level 0/1 0/1 note 0/1 note tpnoe1 tpnol0 tpnoe0 tpnol1 topn1 pin output 16-bit counter ? when tpnol1 bit is 0: topn1 pin output 16-bit counter ? when tpnol1 bit is 1: note set this bit to 0 when not using the topn0 pin in external trigger pulse output mode. remark n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 281 of 1113 sep 22, 2011 figure 7-28. register settings in exte rnal trigger pulse output mode (2/2) (d) tmpn i/o control register 2 (tpnioc2) 00000 tpnioc2 these bits select the valid edge of the external trigger input. 0 0/1 0/1 tpnees0 tpnets1 tpnets0 tpnees1 (e) tmpn counter read buffer register (tpncnt) the value of the 16-bit counter can be read by reading this register. (f) tmpn capture/compare register s 0 and 1 (tpnccr0 and tpnccr1) if the tpnccr0 register is set to d 0 and the tpnccr1 register is set to d 1 , the pwm waveform is as follows: pwm waveform cycle = (d 0 + 1) count clock cycle pwm waveform active level width = d 1 count clock cycle remarks 1. tmpn i/o control register 1 (tpnioc1) and tmpn option register 0 (tpnopt0) are not used in the external trigger pulse output mode. 2. n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 282 of 1113 sep 22, 2011 (1) operations in external trigger pulse output mode figure 7-29. timing and processing of operations in external trigger pulse output mode (1/2) ffffh 16-bit counter 0000h tpnce bit tpnccr0 register ccr0 buffer register inttpncc0 signal tpnccr1 register ccr1 buffer register inttpncc1 signal topn1 pin output external trigger input (tipn0 pin input) topn0 pin output (only when software trigger is used) d 10 d 00 d 00 d 01 d 00 d 00 d 10 d 10 d 11 d 10 d 10 d 10 d 11 d 10 d 01 d 00 d 10 d 10 d 00 d 10 d 00 d 11 d 11 d 01 d 01 d 01 <1> <2> <3> <4> <5> remark n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 283 of 1113 sep 22, 2011 figure 7-29. timing and processing of operations in external trigger pulse output mode (2/2) tpnce bit = 1 set the tpnccr0 register set up the registers tpnctl0 register (tpncks0 to tpncks2 bits) tpnctl1 register tpnioc0 register tpnioc2 register tpnccr0 register tpnccr1 register be sure to set up these registers before setting the tpnce bit to 1. counting starts. the tpncks0 to tpncks2 bits can be set here. waiting for trigger after setting these registers, their values are transferred to the ccra buffer registers when the counter is cleared. start set the tpnccr1 register <1> starting counting <2> changing the cycle the tpnccr1 register must be written even when only changing the cycle setting. set the tpnccr0 register after setting these registers, their values are transferred to the ccra buffer registers when the counter is cleared. set the tpnccr1 register <4> changing both the cycle and the duty when changing both the cycle and the duty, do so in the order of cycle setting then duty setting. after setting this register, the values of the tpnccra registers are transferred to the ccra buffer registers when the counter is cleared. set the tpnccr1 register <3> changing the duty only the tpnccr1 register has to be written when only changing the duty setting. tpnce bit = 0 disables counting. stop <5> stopping counting remark a = 0, 1 n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 284 of 1113 sep 22, 2011 (2) using external trigger pulse output mode how to change the pwm waveform in the external trigger pulse output mode is described below. (a) changing the pwm waveform wh ile the counter is incrementing to change the pwm waveform while the counter is in crementing, write to the tpnccr1 register after changing the waveform setting. when rewriting t he tpnccra register after writing to the tpnccr1 register, do so after the inttpncc0 signal has been detected. figure 7-30. changing pwm wavefo rm while counter is incrementing d 10 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 11 d 01 d 10 d 10 d 00 d 00 d 11 d 11 d 01 d 01 rewrite the tpnccr1 register after rewriting the tpnccr0 register. ffffh 16-bit counter 0000h tpnce bit tpnccr0 register ccr0 buffer register inttpncc0 signal topn0 pin output note tpnccr1 register ccr1 buffer register inttpncc1 signal topn1 pin output external trigger input (tipn0 pin input) note the output from the topn0 pin c an also be used as the input to the tipn0 pin. when using the output from the topn0 pin as the input to the tipn0 pin, use a software trigger instead of an external trigger. remark a = 0, 1 n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 285 of 1113 sep 22, 2011 in order to transfer data from the tpnccra register to the ccra buffer register, the tpnccr1 register must be written. after data is written to the tpnccr1 register, the val ue written to the tpnccra register is transferred to the ccra buffer register in synchronization with cleari ng of the 16-bit counter, and is used as the value to be compared with the 16-bit counter value. <1> to change both the cycle and active level width of the pwm waveform, first set the cycle to the tpnccr0 register and then set the active level width to the tpnccr1 register. <2> to change only the cycle of the pwm waveform, first set the cycle to the tpnccr0 register, and then write the same value to the tpnccr1 register (that is, the same value as the value already specified for the tpnccr1 register). <3> to change only the active level width (duty factor) of the pwm waveform, only the tpnccr1 register has to be set. caution to rewrite the tpnccr0 or tpnccr1 regi ster after writing the tpnccr1 register, do so after the inttpncc0 signal has been generated; otherw ise, the value of the ccra buffer register may become undefined becau se the timing of transferring data from the tpnccra register to the ccra buffer register conflicts with writing the tpnccra register. remark a = 0, 1 n = 0-5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 286 of 1113 sep 22, 2011 (b) outputting a 0% or 100% pwm waveform to output a 0% waveform, clear the tpnccr1 register to 0000h. if the set value of the tpnccr0 register is ffffh, the inttpncc1 signal is gener ated periodically. figure 7-31. outputting 0% pwm waveform count clock 16-bit counter tpnce bit trigger input tpnccr0 register tpnccr1 register inttpncc0 signal inttpncc1 signal topn1 pin output d 0 0000h d 0 0000h d 0 0000h d 0 ? 1d 0 0000 ffff 0000 d 0 ? 1d 0 0000 0001 remark n = 0 to 5 to output a 100% waveform, set the value of tpnccr0 register + 1 to the tpnccr1 register. if the value of the tpnccr0 register is ffffh, a 100% waveform cannot be output. figure 7-32. outputting 100% pwm waveform count clock 16-bit counter tpnce bit trigger input tpnccr0 register tpnccr1 register inttpncc0 signal inttpncc1 signal topn1 pin output d 0 d 0 + 1 d 0 d 0 + 1 d 0 d 0 + 1 d 0 ? 1d 0 0000 ffff 0000 d 0 ? 1d 0 0000 0001 remark n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 287 of 1113 sep 22, 2011 (c) detection of trigger immediately before or after in ttpncc1 generation if the trigger is detected immediately after the inttp ncc1 signal is generated, the 16-bit counter is immediately cleared to 0000h, the output signal of t he topn1 pin is set to the active level, and the counter continues incrementing. co nsequently, the inactive period of the pwm waveform is shortened. figure 7-33. detection of trigger immediat ely after inttpncc1 signal was generated 16-bit counter tpnccr1 register inttpncc1 signal topn1 pin output external trigger input (tipn0 pin input) d 1 d 1 ? 1 0000 ffff 0000 shortened remark n = 0 to 5 if the trigger is detected immediately before the inttp ncc1 signal is generated, the inttpncc1 signal is not generated, and the 16-bit c ounter is cleared to 0000h and cont inues incrementing. the output signal of the topn1 pin remains active. consequ ently, the active period of the pwm waveform is extended. figure 7-34. detection of trigger immediat ely before inttpncc1 signal is generated 16-bit counter tpnccr1 register inttpncc1 signal topn1 pin output external trigger input (tipn0 pin input) d 1 d 1 ? 2d 1 ? 1d 1 0000 ffff 0000 0001 extended remark n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 288 of 1113 sep 22, 2011 (d) detection of trigger immediately before or after in ttpncc0 generation if the trigger is detected immediately after the inttp ncc0 signal is generated, the 16-bit counter is cleared to 0000h and continues incrementing. t herefore, the active period of the topn1 pin is extended by the amount of time between the generation of the inttpncc0 signal and the detection of the trigger. figure 7-35. detection of trigger immediat ely after inttpncc0 signal was generated 16-bit counter tpnccr0 register inttpncc0 signal topn1 pin output external trigger input (tipn0 pin input) d 0 d 0 ? 1d 0 0000 ffff 0000 0000 extended remark n = 0 to 5 if the trigger is detected immediately before the inttp ncc0 signal is generated, the inttpncc0 signal is not generated. the 16-bit counter is cleared to 0000h, the topn1 pin is set to the active level, and the counter continues incrementing. co nsequently, the inactive period of the pwm waveform is shortened. figure 7-36. detection of trigger immediat ely before inttpncc0 signal is generated 16-bit counter tpnccr0 register inttpncc0 signal topn1 pin output external trigger input (tipn0 pin input) d 0 d 0 ? 1d 0 0000 ffff 0000 0001 shortened remark n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 289 of 1113 sep 22, 2011 (e) timing of generating the compare ma tch interrupt request signal (inttpncc1) in the external trigger pulse output mode, the in ttpncc1 signal is generated when the value of the 16-bit counter matches the value of the tpnccr1 register. figure 7-37. timing of generating comp are match interrupt signal (inttpncc1) count clock 16-bit counter tpnccr1 register topn1 pin output inttpncc1 signal d 1 d 1 ? 2d 1 ? 1d 1 d 1 + 1 d 1 + 2 remark n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 290 of 1113 sep 22, 2011 7.4.4 one-shot pulse output mode (tpnmd2 to tpnmd0 bits = 011) in the one-shot pulse output mode, when the tpnctl0.tpnce bi t is set to 1, tmpn waits for a trigger, which is the valid edge of the external trigger input, and starts incremen ting when this trigger is detected. tmpn then outputs a one-shot pulse from the topn1 pin. instead of the external trigger, a software trigger can al so be generated to output the pulse. when the software trigger is used, the topn0 pin outputs the active level signal while the 16-bi t counter is increment ing, and the inactive level signal when the counter is stopped (waiting for a trigger). remarks 1. for how to set the tipn0, topn0, and topn1 pins, see table 7-2 pins used by tmpn and table 4-15 settings when pins ar e used for alternate functions . 2. for how to enable the inttpncc0 and inttpncc1 interrupt signals, see chapter 21 interrupt servcing/exception processing . 3. n = 0 to 5 figure 7-38. configuration of tmpn in one-shot pulse output mode ccr0 buffer register tpnce bit tpnccr0 register tpnccr1 register ccr1 buffer register clear match signal match signal inttpncc0 signal output controller (rs-ff) topn1 pin inttpncc1 signal topn0 pin count clock selection count start control edge detector software trigger generation tipn0 pin transfer transfer s r output controller (rs-ff) s r 16-bit counter
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 291 of 1113 sep 22, 2011 figure 7-39. basic timing of operations in one-shot pulse output mode ffffh 16-bit counter 0000h tpnce bit tpnccr0 register inttpncc0 signal topn0 pin output note tpnccr1 register inttpncc1 signal topn1 pin output external trigger input (tipn0 pin input) d 1 d 0 d 0 d 1 d 1 d 1 d 0 d 0 delay (d 1 ) active level width (d 0 ? d 1 + 1) delay (d 1 ) active level width (d 0 ? d 1 + 1) delay (d 1 ) active level width (d 0 ? d 1 + 1) wait for trigger note the output from the topn0 pin can also be used as the input to the tipn0 pin. when using the output from the topn0 pin as the input to the tipn0 pin, use a so ftware trigger instead of an external trigger. when the tpnce bit is set to 1, tmpn waits for a trigger. when the trigger is generat ed, the 16-bit counter is cleared from ffffh to 0000h, starts in crementing, and outputs a one-shot pulse from the topn1 pin. after the one-shot pulse is output, the 16-bit counter is set to 0000h, st ops incrementing, and waits for a trigger. if a trigger is generated again while the one-shot pul se is being output, it is ignored. the output delay period and active level width of the one-shot pulse can be calculated as follows: output delay period = (set value of tpnccr1 register) count clock cycle active level width = (set value of tpnccr0 register ? set value of tpnccr1 register + 1) count clock cycle the inttpncc0 compare match interrupt request signal is generated when the 16-bit counter increments next time after its value matches the value of the ccr0 buff er register. the inttpncc1 compare match interrupt request signal is generated when the value of the 16-bit co unter matches the value of the ccr1 buffer register. either the valid edge of the external trigger input signal or setting the software trigger (tpnctl1.tpnest bit) to 1 is used as the trigger. remark n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 292 of 1113 sep 22, 2011 figure 7-40. register settings in one-shot pulse output mode (1/2) (a) tmpn control register 0 (tpnctl0) 0/1 0 0 0 0 tpnctl0 these bits select the count clock. 0: stop counting 1: enable counting 0/1 0/1 0/1 tpncks2 tpncks1 tpncks0 tpnce (b) tmpn control register 1 (tpnctl1) 0 0/1 0 0 0 tpnctl1 writing 1 generates a software trigger. 011 tpnmd2 tpnmd1 tpnmd0 tpneee tpnest 0, 1, 1: one-shot pulse output mode (c) tmpn i/o control register 0 (tpnioc0) 0 0 0 0 0/1 tpnioc0 0: disable topn0 pin output. 1: enable topn0 pin output. output level when topn0 pin is disabled: 0: low level 1: high level 0: disable topn1 pin output 1: enable topn1 pin output active level of topn1 pin output: 0: high level 1: low level 0/1 0/1 note 0/1 note tpnoe1 tpnol0 tpnoe0 tpnol1 topn1 pin output 16-bit counter ? when tpnol1 bit is 0: topn1 pin output 16-bit counter ? when tpnol1 bit is 1: note set this bit to 0 when not using the topn0 pin in the one-shot pulse output mode. remark n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 293 of 1113 sep 22, 2011 figure 7-40. register settings in one-shot pulse output mode (2/2) (d) tmpn i/o control register 2 (tpnioc2) 00000 tpnioc2 these bits select the valid edge of the external trigger input. 0 0/1 0/1 tpnees0 tpnets1 tpnets0 tpnees1 (e) tmpn counter read buffer register (tpncnt) the value of the 16-bit counter can be read by reading this register. (f) tmpn capture/compare register s 0 and 1 (tpnccr0 and tpnccr1) if the tpnccr0 register is set to d 0 and the tpnccr1 register is set to d 1 , the one-shot pulse is as follows: one-shot pulse active level width = (d 0 ? d 1 + 1) count clock cycle one-shot pulse output delay period = d 1 count clock cycle caution one-shot pulses are not output from th e topn1 pin in the one-shot pulse output mode if the value of the tpnccr1 register is great er than the value of the tpnccr0 register. remarks 1. tmpn i/o control register 1 (tpnioc1) and tmpn option register 0 (tpnopt0) are not used in the one-shot pulse output mode. 2. n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 294 of 1113 sep 22, 2011 (1) operations in one-shot pulse output mode figure 7-41. timing and processing of operat ions in one-shot pu lse output mode ffffh 16-bit counter 0000h tpnce bit tpnccr0 register inttpncc0 signal tpnccr1 register inttpncc1 signal topn1 pin output external trigger input (tipn0 pin input) <1> <3> tpnce bit = 1 set up the registers tpnctl0 register (tpncks0 to tpncks2 bits) tpnctl1 register tpnioc0 register tpnioc2 register tpnccr0 register tpnccr1 register be sure to set up these registers before setting the tpnce bit to 1. counting starts. the tpncks0 to tpncks2 bits can be set here. waiting for trigger. start <1> starting counting tpnce bit = 0 disables counting. stop <3> stopping counting d 10 d 00 d 11 d 01 d 00 d 10 d 11 <2> d 01 set the tpnccr0 and tpnccr1 registers because the tpnccra register value will be transferred to the ccra buffer register as soon as the tpnccra register is rewritten, it is recommended to rewrite the tpnccra register immediately after the inttpnccr0 signal is generated. <2> changing the tpnccr0 and tpnccr1 register settings remark a = 0, 1 n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 295 of 1113 sep 22, 2011 (2) using one-shot pulse mode (a) rewriting the tpnccra register when rewriting the value of the tp nccra register to a smaller valu e, stop counting first and then change the set value. when changing the value of t he tpnccr0 register from d 00 to d 01 and the value of the tpnccr1 register from d 10 to d 11 , if the registers are rewritten under an y of the following conditions, a one-shot pulse will not be output as expected. condition 1 when rewriting the tpnccr0 register, if: d 00 > d 01 or, d 00 < 16-bit counter value < d 01 in the case of condition 1, the 16-bit counter will no t be cleared and will overflow in the cycle in which the new value is being written. the counter will be cl eared for the first time at the newly written value (d 01 ). condition 2 when rewriting the tpnccr1 register, if: d 10 > d 11 or, d 10 < 16-bit counter value < d 11 in the case of condition 2, the to pn1 pin output cannot be inverted to the active level in the cycle in which the new value is being written. an example of what happens when condition 1 and condit ion 2 are satisfied in the same cycle is shown in figure 7-42. the 16-bit counter increments up to ffffh, overflow s, and starts increment ing again from 0000h. when the 16-bit counter value matches d 11 , the inttpncc1 signal is generated and the topn1 pin output is set to the active level. subseq uently, when the 16-bit counter value matches d 01 , the inttpncc0 signal is generated, the topn1 pin output is set to the inactive level, and the counter stops incrementing. remark n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 296 of 1113 sep 22, 2011 figure 7-42. rewriting tpnccra register d 10 d 11 d 00 d 01 d 00 d 10 d 10 d 10 d 01 d 11 d 00 d 00 ffffh 16-bit counter 0000h tpnce bit inttpncc0 signal topn0 pin output note inttpncc1 signal topn1 pin output external trigger input (tipn0 pin input) delay (d 10 ) active level width (d 00 ? d 10 + 1) delay (d 10 ) active level width (d 00 ? d 10 + 1) delay (10000h + d 11 ) active level width (d 01 ? d 11 + 1) tpnccr0 register (ccr0 buffer register) tpnccr1 register (ccr1 buffer register) note the output from the topn0 pin can also be used as the input to the ti pn0 pin. when using the output from the topn0 pin as the input to the tipn0 pin, use a software trigger instead of an external trigger. remark a = 0, 1 n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 297 of 1113 sep 22, 2011 (b) timing of generating the compare ma tch interrupt request signal (inttpncc1) in the one-shot pulse output mode, the inttpncc1 signal is generated when t he value of the 16-bit counter matches the value of the tpnccr1 register. figure 7-43. timing of generating comp are match interrupt signal (inttpncc1) count clock 16-bit counter tpnccr1 register topn1 pin output inttpncc1 signal d 1 d 1 ? 2d 1 ? 1d 1 d 1 + 1 d 1 + 2 remark n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 298 of 1113 sep 22, 2011 7.4.5 pwm output mode (tpnmd 2 to tpnmd0 bits = 100) in the pwm output mode, when the tpnctl0.tpnce bit is set to 1, tmpn outputs a pwm waveform from the topn1 pin. a pulse that has one cycle of the pwm waveform as hal f its cycle can also be output from the topn0 pin. remarks 1. for how to set the tipn0, topn0, and topn1 pins, see table 7-2 pins used by tmpn and table 4-15 settings when pins ar e used for alternate functions . 2. for how to enable the inttpncc0 and inttpncc1 interrupt signals, see chapter 21 interrupt servicing/exception processing . figure 7-44. configuration of tmpn in pwm output mode s r ccr0 buffer register tpnce bit tpnccr0 register 16-bit counter tpnccr1 register ccr1 buffer register clear match signal match signal inttpncc0 signal output controller (rs-ff) output controller topn1 pin inttpncc1 signal topn0 pin count clock selection transfer transfer remark n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 299 of 1113 sep 22, 2011 figure 7-45. basic timing of operations in pwm output mode ffffh 16-bit counter 0000h tpnce bit tpnccr0 register ccr0 buffer register nttpncc0 signal topn0 pin output tpnccr1 register ccr1 buffer register inttpncc1 signal topn1 pin output d 10 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 11 d 01 d 10 d 10 d 00 d 00 d 11 d 11 d 01 d 01 active period (d 10 ) cycle (d 00 + 1) inactive period (d 00 ? d 10 + 1) when the tpnce bit is set to 1, the 16-bit counter is cleared from ffffh to 0000h, starts incrementing, and outputs a pwm waveform from the topn1 pin. the active level width, cycle, and duty factor of the pwm waveform can be calculated as follows: active level width = (set value of tpnccr1 register) count clock cycle cycle = (set value of tpnccr0 register + 1) count clock cycle duty factor = (set value of tpnccr1 regist er)/(set value of tpnccr0 register + 1) the pwm waveform can be changed by rewriting the tpnccra register while the counter is incrementing. the newly written value is reflected when the value of the 16- bit counter matches the value of the ccr0 buffer register and the 16-bit counter is cleared to 0000h. the inttpncc0 compare match interrupt request signal is generated when the 16-bit counter increments next time after its count value matches the value of the ccr0 buff er register, and the 16-bit counter is cleared to 0000h. the inttpncc1 compare match interrupt request signal is generated when the value of the 16-bit counter matches the value of the ccr1 buffer register. remark a = 0, 1 n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 300 of 1113 sep 22, 2011 figure 7-46. register settings in pwm output mode (1/2) (a) tmpn control register 0 (tpnctl0) 0/1 0 0 0 0 tpnctl0 these bits select the count clock note 1 . 0: stop counting. 1: enable counting. 0/1 0/1 0/1 tpncks2 tpncks1 tpncks0 tpnce (b) tmpn control register 1 (tpnctl1) 0 0 0/1 0 0 tpnctl1 100 tpnmd2 tpnmd1 tpnmd0 tpneee tpnest 1, 0, 0: pwm output mode 0: operate tmpn on count clock selected by using tpncks0 to tpncks2 bits. 1: increment tmpn based on external event count input signal. (c) tmpn i/o control register 0 (tpnioc0) 0 0 0 0 0/1 tpnioc0 0: disable topn0 pin output. 1: enable topn0 pin output. output level when topn0 pin is disabled: 0: low level 1: high level 0: disable topn1 pin output. 1: enable topn1 pin output. active level of topn1 pin output: 0: high level 1: low level 0/1 0/1 note 2 0/1 note 2 tpnoe1 tpnol0 tpnoe0 tpnol1 topn1 pin output 16-bit counter ? when tpnol1 bit is 0: topn1 pin output 16-bit counter ? when tpnol1 bit is 1: notes 1. the setting of these bits is invalid when the tpnctl1.tpneee bit is 1. 2. set this bit to 0 when not using the topn0 pin in the pwm output mode. remark n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 301 of 1113 sep 22, 2011 figure 7-46. register settings in pwm output mode (2/2) (d) tmpn i/o control register 2 (tpnioc2) 0 0 0 0 0/1 tpnioc2 these bits select the valid edge of the external trigger input. 0/1 0 0 tpnees0 tpnets1 tpnets0 tpnees1 (e) tmpn counter read buffer register (tpncnt) the value of the 16-bit counter can be read by reading this register. (f) tmpn capture/compare register s 0 and 1 (tpnccr0 and tpnccr1) if the tpnccr0 register is set to d 0 and the tpnccr1 register is set to d 1 , the pwm waveform is as follows: pwm waveform cycle = (d 0 + 1) count clock cycle pwm waveform active level width = d 1 count clock cycle remarks 1. tmpn i/o control register 1 (tpnioc1) and tmpn option register 0 (tpnopt0) are not used in the pwm output mode. 2. n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 302 of 1113 sep 22, 2011 (1) operations in pwm output mode figure 7-47. timing and processing of op erations in pwm ou tput mode (1/2) ffffh 16-bit counter 0000h tpnce bit tpnccr0 register ccr0 buffer register inttpncc0 signal topn0 pin output tpnccr1 register ccr1 buffer register inttpncc1 signal topn1 pin output d 10 d 00 d 00 d 01 d 00 d 00 d 10 d 10 d 11 d 10 d 10 d 10 d 11 d 10 d 01 d 00 d 10 d 10 d 00 d 10 d 00 d 11 d 11 d 01 d 01 d 01 <2> <3> <4> <5> <1> remark n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 303 of 1113 sep 22, 2011 figure 7-47. timing and processing of op erations in pwm ou tput mode (2/2) tpnce bit = 1 set the tpnccr0 register set up the registers tpnctl0 register (tpncks0 to tpncks2 bits) tpnctl1 register tpnioc0 register tpnioc2 register tpnccr0 register tpnccr1 register be sure to set up these registers before setting the tpnce bit to 1. counting starts. the tpncks0 to tpncks2 bits can be set here. after setting these registers, their values are transferred to the ccra buffer registers when the counter is cleared. start set the tpnccr1 register <1> starting counting <2> changing the cycle the tpnccr1 register must be written even when only changing the cycle setting. set the tpnccr0 register after setting these registers, their values are transferred to the ccra buffer registers when the counter is cleared. set the tpnccr1 register <4> changing both the cycle and the duty when changing both the cycle and the duty, do so in the order of cycle setting then duty setting. after setting this register, the values of the tpnccra registers are transferred to the ccra buffer registers when the counter is cleared. set the tpnccr1 register <3> changing the duty only the tpnccr1 register has to be written when only changing the duty setting. tpnce bit = 0 disables counting. stop <5> stopping counting remark a = 0, 1 n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 304 of 1113 sep 22, 2011 (2) using pwm output mode (a) changing the pwm waveform wh ile the counter is incrementing to change the pwm waveform while the counter is in crementing, write to the tpnccr1 register after changing the waveform setting. when rewriting t he tpnccra register after writing to the tpnccr1 register, do so after the inttpncc0 signal has been detected. figure 7-48. changing pwm wavefo rm while counter is incrementing ffffh 16-bit counter 0000h tpnce bit tpnccr0 register ccr0 buffer register tpnccr1 register ccr1 buffer register topn1 pin output inttpncc0 signal d 10 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 11 d 01 d 10 d 10 d 00 d 00 d 11 d 11 d 01 d 01 in order to transfer data from the tpnccra register to the ccra buffer register, the tpnccr1 register must be written. after data is written to the tpnccr1 register, the val ue written to the tpnccra register is transferred to the ccra buffer register in synchronization with cleari ng of the 16-bit counter, and is used as the value to be compared with the 16-bit counter value. <1> to change both the cycle and active level width of the pwm waveform, first set the cycle to the tpnccr0 register and then set the active level width to the tpnccr1 register. <2> to change only the cycle of the pwm waveform, first set the cycle to th e tpnccr0 register, and then write the same value to the tpnccr1 register (that is, the same value as the value already specified for the tpnccr1 register). <3> to change only the active level width (dut y factor) of the pwm waveform, only the tpnccr1 register has to be set.
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 305 of 1113 sep 22, 2011 caution to rewrite the tpnccr0 or tpnccr1 regist er after writing the tpnccr1 register, do so after the inttpncc0 signal has been generate d; otherwise, the value of the ccra buffer register may become undefine d because the timing of tr ansferring data from the tpnccra register to the ccra buffer regist er conflicts with writing the tpnccra register. remark a = 0, 1 n = 0 to 5 (b) outputting a 0% or 100% pwm waveform to output a 0% waveform, clear the tpnccr1 register to 0000h. figure 7-49. outputting 0% pwm waveform count clock 16-bit counter tpnce bit tpnccr0 register tpnccr1 register inttpncc0 signal inttpncc1 signal topn1 pin output d 00 0000h d 00 0000h d 00 0000h d 00 ? 1d 00 0000 ffff 0000 d 00 ? 1d 00 0000 0001 remark n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 306 of 1113 sep 22, 2011 to output a 100% waveform, set the value of tpnccr0 register + 1 to the tpnccr1 register. if the value of the tpnccr0 register is ffffh, a 100% waveform cannot be output. figure 7-50. outputting 100% pwm waveform count clock 16-bit counter tpnce bit tpnccr0 register tpnccr1 register inttpncc0 signal inttpncc1 signal topn1 pin output d 00 d 00 + 1 d 00 d 00 + 1 d 00 d 00 + 1 d 00 ? 1d 00 0000 ffff 0000 d 00 ? 1d 00 0000 0001 remark n = 0 to 5 (c) timing of generating the compare ma tch interrupt request signal (inttpncc1) in the pwm output mode, the inttpncc1 signal is generated when the value of the 16-bit counter matches the value of the tpnccr1 register. figure 7-51. timing of generating comp are match interrupt signal (inttpncc1) count clock 16-bit counter tpnccr1 register topn1 pin output inttpncc1 signal d 1 d 1 ? 2d 1 ? 1d 1 d 1 + 1 d 1 + 2 remark n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 307 of 1113 sep 22, 2011 7.4.6 free-running timer mode (t pnmd2 to tpnmd0 bits = 101) in the free-running timer mode, tmpn starts incrementing when the tpnctl0.tpnce bit is set to 1. at this time, the tpnccra register can be used as a compare register or a capture register, according to the setting of the tpnopt0.tpnccs0 and tpnopt0.tpnccs1 bits. remarks 1. for how to set the tipn0, ti pn1, topn0, and topn1 pins, see table 7-2 pins used by tmpn and table 4-15 settings when pins are used for alternate functions . 2. for how to enable the inttpncc0 and inttpncc1 interrupt signals, see chapter 21 interrupt servicing/exception processing . 3. a = 0, 1 n = 0 to 5 figure 7-52. configuration of tmpn in free-running timer mode tpnccr0 register (capture) tpnce bit tpnccr1 register (capture) 16-bit counter tpnccr1 register (compare) tpnccr0 register (compare) output controller tpnccs0, tpnccs1 bits (capture/compare selection) topn0 note 1 pin output output controller topn1 note 2 pin output edge detector count clock selection edge detector edge detector tipn0 note 1 pin (external event count input/ capture trigger input) tipn1 note 2 pin (capture trigger input) internal count clock 0 1 0 1 inttpnov signal inttpncc1 signal inttpncc0 signal notes 1. the external event count input/capture trigger input pin (tipn0) can also be used as the timer output pin (topn0); however, only one of these functions can be used at a time. 2. the capture trigger input pin (tipn1) can al so be used as the timer output pin (topn1); however, only one of these func tions can be used at a time. remark a = 0, 1 n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 308 of 1113 sep 22, 2011 ? compare operation when the tpnce bit is set to 1, tmpn starts increm enting, and the output signals of the topn0 and topn1 pins are inverted. when the value of the 16-bit counter later matches the set value of the tpnccra register, a compare match interrupt request signal (inttpncca) is generated, and the output signal of the topna pin is inverted. the 16-bit counter continues incrementing in synchronizati on with the count clock. once the counter reaches ffffh, it generates an overflow interrupt request signal (inttpnov) at the next cl ock, is cleared to 0000h, and continues incrementing. at this time, the overflow fl ag (the tpnopt0.tpnovf bit) is also set to 1. the overflow flag must be cleared to 0 by executing a clr1 software instruction. the tpnccra register can be rewritten while the counter is incrementing. if it is rewritten, the new value is immediately applied, and compar ed with the count value. remark a = 0, 1 n = 0 to 5 figure 7-53. basic timing of operations in free-running timer mode (compare function) ffffh 16-bit counter 0000h tpnce bit tpnccr0 register inttpncc0 signal topn0 pin output tpnccr1 register inttpncc1 signal topn1 pin output inttpnov signal tpnovf bit d 00 d 01 d 10 d 11 d 00 d 10 d 10 d 11 d 11 d 11 d 00 d 01 d 01 cleared to 0 by clr1 instruction cleared to 0 by clr1 instruction cleared to 0 by clr1 instruction cleared to 0 by clr1 instruction
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 309 of 1113 sep 22, 2011 ? capture operation when the tpnce bit is set to 1, the 16-bit counter starts incrementing. when it is detected that a valid edge as been input to the tipna pin, the va lue of the 16-bit counter is stored in the tpnccra register, and a capture interrupt request signal (inttpncca) is generated. the 16-bit counter continues incrementing in synchroniza tion with the count clock. when the counter reaches ffffh, it generates an overflow interrupt request signal (inttpnov) at the next cl ock, is cleared to 0000h, and continues incrementing. at this time, the overflow fl ag (the tpnopt0.tpnovf bit) is also set to 1. the overflow flag must be cleared to 0 by executing a clr1 software instruction. remark a = 0, 1 n = 0 to 5 figure 7-54. basic timing of operations in free-running timer mode (capture function) ffffh 16-bit counter 0000h tpnce bit tipn0 pin input tpnccr0 register inttpncc0 signal tipn1 pin input tpnccr1 register inttpncc1 signal inttpnov signal tpnovf bit d 00 d 01 d 02 d 03 d 10 d 00 d 01 d 02 d 03 d 11 d 12 d 13 d 10 d 11 d 12 d 13 cleared to 0 by clr1 instruction cleared to 0 by clr1 instruction cleared to 0 by clr1 instruction remark the valid edge is the rising edge.
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 310 of 1113 sep 22, 2011 figure 7-55. register settings in free-running timer mode (1/2) (a) tmpn control register 0 (tpnctl0) 0/1 0 0 0 0 tpnctl0 these bits select the count clock note . 0: stop counting. 1: enable counting. 0/1 0/1 0/1 tpncks2 tpncks1 tpncks0 tpnce note the setting of these bits is invalid when the tpnctl1.tpneee bit is 1. (b) tmpn control register 1 (tpnctl1) 0 0 0/1 note 00 tpnctl1 101 tpnmd2 tpnmd1 tpnmd0 tpneee tpnest 1, 0, 1: free-running timer mode 0: operate tmpn on count clock selected by using tpncks0 to tpncks2 bits. 1: increment tmpn based on external event count input signal. note the capture function of the tipn0 pin cannot be used if t he tpnctl1.tpneee bit is 1. (c) tmpn i/o control register 0 (tpnioc0) 0 0 0 0 0/1 note 1 tpnioc0 0: disable topn0 pin output. 1: enable topn0 pin output. output level when topn0 pin is disabled: 0: low level 1: high level 0: disable topn1 pin output. 1: enable topn1 pin output. output level when topn1 pin is disabled: 0: low level 1: high level 0/1 note 1 0/1 note 2 0/1 note 2 tpnoe1 tpnol0 tpnoe0 tpnol1 notes 1. the topn1 pin cannot be used w hen the tipn1 pin is being used. 2. the topn0 pin cannot be used w hen the tipn0 pin is being used.
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 311 of 1113 sep 22, 2011 figure 7-55. register settings in free-running timer mode (2/2) (d) tmpn i/o control register 1 (tpnioc1) 0 0 0 0 0/1 tpnioc1 these bits select the valid edge of the tipn0 pin input. these bits select the valid edge of the tipn1 pin input. 0/1 0/1 0/1 tpnis2 tpnis1 tpnis0 tpnis3 (e) tmpn i/o control register 2 (tpnioc2) 0 0 0 0 0/1 tpnioc2 these bits select the valid edge of the external event count input. 0/1 0 0 tpnees0 tpnets1 tpnets0 tpnees1 (f) tmpn option register 0 (tpnopt0) 0 0 0/1 0/1 0 tpnopt0 overflow flag specifies whether tpnccr0 register is used for capture or compare. specifies whether tpnccr1 register is used for capture or compare. 0 0 0/1 tpnccs0 tpnovf tpnccs1 (g) tmpn counter read buffer register (tpncnt) the value of the 16-bit counter can be read by reading this register. (h) tmpn capture/compare regist ers 0 and 1 (tpnccr0 and tpnccr1) these registers function as capture registers or compare regist ers according to the setting of the tpnopt0.tpnccsa bit. when the registers function as captur e registers, they store the value of the 16-bit counter when it is detected that a valid edge has been input to the tipna pin, after which the inttpncca signal is generated. when the registers function as com pare registers and when the tpnccra register is set to da, the inttpncca signal is generated the when the counter reaches (d a + 1), and the output signal of the topna pin is inverted. remark a = 0, 1 n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 312 of 1113 sep 22, 2011 (1) operations in fr ee-running timer mode the following two operations occur in the free-running timer mode: ? capture operations ? compare operations (a) using a capture/compare register as a compare register figure 7-56. timing and processing of operations in free-running timer mode (compare function) (1/2) d 00 d 01 d 10 d 11 d 00 d 10 d 10 d 11 d 11 d 11 d 00 d 01 d 01 ffffh 16-bit counter 0000h tpnce bit inttpncc0 signal topn0 pin output inttpncc1 signal topn1 pin output inttpnov signal tpnovf bit cleared to 0 by clr1 instruction cleared to 0 by clr1 instruction cleared to 0 by clr1 instruction <1> <2> <2> <2> <3> tpnccr0 register (ccr0 buffer register) tpnccr1 register (ccr1 buffer register) remark n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 313 of 1113 sep 22, 2011 figure 7-56. timing and processing of operations in free-running timer mode (compare function) (2/2) tpnce bit = 1 read tpnopt0 register (check overflow flag) set up the registers tpnctl0 register (tpncks0 to tpncks2 bits) tpnctl1 register tpnioc0 register tpnioc2 register tpnopt0 register tpnccr0 register tpnccr1 register be sure to set up these registers before setting the tpnce bit to 1. counting starts. the tpncks0 to tpncks2 bits can be set here. start execute instruction to clear tpnovf bit (clr1 tpnovf) <1> starting counting <2> clearing overflow flag tpnce bit = 0 when counting is disabled (tpnce bit = 0), the counter is reset and counting stops. stop <3> stopping counting tpnovf bit = 1 no yes
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 314 of 1113 sep 22, 2011 (b) using a capture/compare register as a capture register figure 7-57. timing and processing of operations in free-running timer mode (capture function) (1/2) ffffh 16-bit counter 0000h tpnce bit tipn0 pin input inttpncc0 signal tipn1 pin input inttpncc1 signal inttpnov signal tpnovf bit d 00 0000 0000 d 01 d 02 d 03 d 10 d 00 d 01 d 02 d 03 d 11 d 12 d 10 0000 d 11 d 12 0000 cleared to 0 by clr1 instruction cleared to 0 by clr1 instruction <3> <1> <2> <2> tpnccr0 register (ccr0 buffer register) tpnccr1 register (ccr1 buffer register) remark n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 315 of 1113 sep 22, 2011 figure 7-57. timing and processing of operations in free-running timer mode (capture function) (2/2) tpnce bit = 1 read tpnopt0 register (check overflow flag) set up the registers tpnctl0 register (tpncks0 to tpncks2 bits) tpnctl1 register tpnioc1 register tpnopt0 register be sure to set up these registers before setting the tpnce bit to 1. counting starts. the tpncks0 to tpncks2 bits can be set here. start execute instruction to clear tpnovf bit (clr1 tpnovf) <1> starting counting <2> clearing overflow flag tpnce bit = 0 when counting is disabled (tpnce bit = 0), the counter is reset and counting stops. stop <3> stopping counting tpnovf bit = 1 no yes remark n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 316 of 1113 sep 22, 2011 (2) using free-running timer mode (a) interval operation using the tpn ccra register as a compare register when tmpn is used as an interval timer with the tp nccra register used as a compare register, the comparison value at which the next interrupt reques t signal is generated each time the inttpncca signal has been detected must be set by software. figure 7-58. interval operation of tmpn in free-running timer mode ffffh 16-bit counter 0000h tpnce bit inttpncc0 signal topn pin output inttpncc1 signal topn1 pin output d 00 d 01 d 02 d 03 d 04 d 05 d 10 d 00 d 11 d 01 d 12 d 04 d 13 d 02 d 03 d 11 d 10 d 12 d 13 d 14 interval period (d 10 + 1) interval period (10000h + d 11 ? d 10 ) interval period (10000h + d 12 ? d 11 ) interval period (10000h + d 13 ? d 12 ) interval period (d 00 + 1) interval period (10000h + d 01 ? d 00 ) interval period (d 02 ? d 01 ) interval period (10000h + d 03 ? d 02 ) interval period (10000h + d 04 ? d 03 ) tpnccr0 register (ccr0 buffer register) tpnccr1 register (ccr1 buffer register) when performing an interval operation in the free-running timer mode, two intervals can be set for one channel. to perform the interval operation, the value of the corresponding tpnccra register must be set again in the interrupt servicing that is executed when the inttpncca signal is detected. the value to be set in this case can be calculated by the following expression, where ?d a ? is the interval period. compare register default value: d a ? 1 value set to compare register second and subsequent time: previous set value + d a (if the calculation result is greate r than ffffh, subtract 10000h from t he result and set the register to this value.) remark a = 0, 1 n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 317 of 1113 sep 22, 2011 (b) pulse width measurement using the tp nccra register as a capture register when pulse width measurement is performed with the tpnccra register used as a capture register, each time the inttpncca signal has been detected, t he capture register must be read and the interval must be calculated by software. figure 7-59. pulse width measurement by tmpn in free-running timer mode ffffh 16-bit counter 0000h tpnce bit tipn0 pin input inttpncc0 signal tipn1 pin input inttpncc1 signal inttpnov signal tpnovf bit 0000h d 00 d 01 d 02 d 03 d 04 d 10 d 00 d 11 d 01 d 12 d 04 d 13 d 02 d 03 d 10 0000h d 11 d 12 d 13 pulse interval (d 00 ) pulse interval (10000h + d 01 ? d 00 ) pulse interval (d 02 ? d 01 ) pulse interval (10000h + d 03 ? d 02 ) pulse interval (10000h + d 04 ? d 03 ) pulse interval (d 10 ) pulse interval (10000h + d 11 ? d 10 ) pulse interval (10000h + d 12 ? d 11 ) pulse interval (10000h + d 13 ? d 12 ) cleared to 0 by clr1 instruction cleared to 0 by clr1 instruction cleared to 0 by clr1 instruction tpnccr0 register (ccr0 buffer register) tpnccr1 register (ccr1 buffer register) when executing pulse width measurement in the free-running timer mode, two pulse widths can be measured for one channel. when measuring a pulse width, the pulse width can be calculated by reading the value of the tpnccra register in synchronization with the inttpncca signa l, and calculating the diff erence between that value and the previously read value. remark a = 0, 1 n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 318 of 1113 sep 22, 2011 (c) processing an overflow when two capture registers are used care must be exercised in processing the overflow flag when two capture registers are used. first, an example of incorrect processing is shown below. figure 7-60. example of incorrect proce ssing when two capture registers are used ffffh 16-bit counter 0000h tpnce bit tipn0 pin input tpnccr0 register tipn1 pin input tpnccr1 register inttpnov signal tpnovf bit d 00 d 01 d 10 d 11 d 10 <1> <2> <3> <4> d 00 d 11 d 01 the following problem may occur when two pulse widt hs are measured in the free-running timer mode. <1> the tpnccr0 register is read (the default value of the tipn0 pin input is set). <2> the tpnccr1 register is read (the default value of the tipn1 pin input is set). <3> the tpnccr0 register is read. the tpnovf bit is read. if the tpnovf bit is 1, it is cleared to 0. because the tpnovf bit is 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <4> the tpnccr1 register is read. the tpnovf bit is read. because the bit was cleared in <3>, 0 is read. because the tpnovf bit is 0, t he pulse width can be calculated by (d 11 ? d 10 ) (incorrect). when two capture registers are used, and if the overfl ow flag is cleared to 0 by one capture register, the other capture register may not obtain the correct pulse width. this problem can be resolved by using software, as shown in the example below. remark n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 319 of 1113 sep 22, 2011 figure 7-61. example of resolving problem when tw o capture registers are used by using overflow interrupt ffffh 16-bit counter 0000h tpnce bit inttpnov signal tpnovf bit tpnovf0 flag note tipn0 pin input tpnccr0 register tpnovf1 flag note tipn1 pin input tpnccr1 register d 10 d 11 d 00 d 01 d 10 <1> <2> <5> <6> <3> <4> d 00 d 11 d 01 note the tpnovf0 and tpnovf1 flags are set on the internal ram by software. <1> the tpnccr0 register is read (the default value of the tipn0 pin input is set). <2> the tpnccr1 register is read (the default value of the tipn1 pin input is set). <3> an overflow occurs. the tpnovf0 and tpnovf1 flags are set to 1 in the overflow interrupt servicing, and the tpnovf bit is cleared to 0. <4> the tpnccr0 register is read. the tpnovf0 flag is read. the tpnovf0 flag is 1, so it is cleared to 0. because the tpnovf0 flag was 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <5> the tpnccr1 register is read. the tpnovf1 flag is read. the tpnovf1 flag is 1, so it is cleared to 0 (the tpnovf0 flag was cleared in <4>; the tpnovf1 flag remained 1). because the tpnovf1 flag is 1, the pulse width can be calculated by (10000h + d 11 ? d 10 ) (correct). <6> same as <3>. remark n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 320 of 1113 sep 22, 2011 figure 7-62. example of resolving problem when two capture registers are used without using overflow interrupt ffffh 16-bit counter 0000h tpnce bit inttpnov signal tpnovf bit tpnovf0 flag note tipn0 pin input tpnccr0 register tpnovf1 flag note tipn1 pin input tpnccr1 register d 10 d 11 d 00 d 01 d 10 <1> <2> <5> <6> <3> <4> d 00 d 11 d 01 note the tpnovf0 and tpnovf1 flags are set on the internal ram by software. <1> the tpnccr0 register is read (the default value of the tipn0 pin input is set). <2> the tpnccr1 register is read (the default value of the tipn1 pin input is set). <3> an overflow occurs. there is no software processing. <4> the tpnccr0 register is read. the tpnovf bit is read. the tpnovf bit is 1, so only the tpnovf1 flag is set (to 1); the tpnovf bit is cleared to 0. because the tpnovf bit is 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <5> the tpnccr1 register is read. the tpnovf bit is read. the tpnovf bit was cleared to 0 in <4>, so 0 is read. the tpnovf1 flag is read. the tpnovf1 fl ag is 1, so it is cleared to 0. because the tpnovf1 flag was 1, the pulse width can be calculated by (10000h + d 11 ? d 10 ) (correct). <6> same as <3>. remark n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 321 of 1113 sep 22, 2011 (d) processing of overflow if cap ture trigger interval is long if the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an overflow may occur more than once between the first capture trigger and the next. first, an example of incorrect processing is shown below. figure 7-63. example of incorrect processing when ca pture trigger interval is long (when using tipn0) ffffh 16-bit counter 0000h tpnce bit tipn0 pin input tpnccr0 register inttpnov signal tpnovf bit d m0 d m1 d m0 d m1 <1> <2> <3> <4> 1 cycle of 16-bit counter pulse width the following problem may occur when long pulse width is measured in the free-running timer mode. <1> the tpnccr0 register is read (the default value of the tipn0 pin input is set). <2> an overflow occurs. there is no software processing. <3> an overflow occurs a second time. there is no software processing. <4> the tpnccr0 register is read. the tpnovf bit is read. the tpnovf bit is 1, so it is cleared to 0. because the tpnovf bit was 1, the puls e width can be calculated by (10000h + d a1 ? d a0 ) (incorrect). actually, the pulse width should be (20000h + d a1 ? d a0 ) because an overflow occurred twice. if an overflow occurs twice or more when the capture tr igger interval is long, the correct pulse width may not be obtained. if the capture trigger interval is long, slow the count clock to lengthen one cycle of the 16-bit counter, or use software to resolve the problem. an example of how to use software to resolve the problem is shown below.
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 322 of 1113 sep 22, 2011 figure 7-64. example of using software processing to resolve problem when capture trigger interval is long (when using tipn0) ffffh 16-bit counter 0000h tpnce bit tipn0 pin input tpnccr0 register inttpnov signal tpnovf bit overflow counter note d m0 d m1 1h 0h 2h 0h d m0 d m1 <1> <2> <3> <4> 1 cycle of 16-bit counter pulse width note the overflow counter is set on the internal ram by software. <1> the tpnccr0 register is read (the default value of the tipn0 pin input is set). <2> an overflow occurs. the overflow counter is incremented and the tpnovf bit is cleared to 0 in the overflow interrupt servicing. <3> an overflow occurs a second time. the overfl ow counter is incremented and the tpnovf bit is cleared to 0 in the overflow interrupt servicing. <4> the tpnccr0 register is read. the overflow counter is read. if the overflow counter is n, the pulse width can be calculated by (n 10000h + d a1 ? d a0 ). in this example, because an overflow occu rred twice, the pulse wi dth is calculated as (20000h + d a1 ? d a0 ). the overflow counter is cleared to 0h. remark n = 0 to 5 (e) clearing the overflow flag (tpnovf) the overflow flag (tpnovf) can be cleared to 0 by r eading the tpnovf bit and, if its value is 1, either clearing the bit to 0 by using the clr1 instruction or by writing 8-bit data (with bi t 0 as 0) to the tpnopt0 register.
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 323 of 1113 sep 22, 2011 7.4.7 pulse width measurement mode (tpnmd2 to tpnmd0 bits = 110) in the pulse width measurement mode, tmpn starts incr ementing when the tpnctl0.tpnce bit is set to 1. each time it is detected that a valid edge has been input to the tipna pin, the value of th e 16-bit counter is stored in the tpnccra register, and the 16-bit counter is cleared to 0000h. the interval of the valid edge can be measured by reading the tpnccra register after a capture interrupt request signal (inttpncca) occurs. select either the tipn0 or tipn1 pin as the capture trigger input pin. s pecify ?no edge detected? by using the tpnioc1 register for the unused pins. remarks 1. for how to set the tipn0 and tipn1 pins, see table 7-2 pins used by tmpn and table 4-15 settings when pins are used for alternate functions . 2. for how to enable the inttpncc0 and inttpncc1 interrupt signals, see chapter 21 interrupt servicing/exception processing . 3. a = 0, 1 n = 0 to 5 figure 7-65. configuration of tmpn in pulse width measurement mode tpnccr0 register (capture) tpnce bit tpnccr1 register (capture) count clock selection edge detector edge detector tipn0 pin (capture trigger input) tipn1 pin (capture trigger input) clear inttpnov signal inttpncc0 signal inttpncc1 signal 16-bit counter
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 324 of 1113 sep 22, 2011 figure 7-66. basic timing of operati ons in pulse width measurement mode ffffh 16-bit counter 0000h tpnce bit tipna pin input tpnccra register inttpncca signal inttpnov signal tpnovf bit d 0 0000h d 1 d 2 d 3 cleared to 0 by clr1 instruction when the tpnce bit is set to 1, the 16-bit counter starts incrementing. when it is subsequently det ected that a valid edge has been input to the tipna pin, the value of the 16-bit counter is stored in the tpnccra register, the 16-bit counter is cleared to 0000h, and a capture interrupt request signal (inttpncca) is generated. the pulse width is calculated as follows. pulse width = captured value count clock cycle if a valid edge has not been input to the tipna pin by the time the 16-bi t counter has incremented up to ffffh, an overflow interrupt request signal (inttpnov) is generated at the next count clock, an d the counter is cleared to 0000h and continues incrementing. at this time, the overfl ow flag (tpnopt0.tpnovf bit) is also set to 1. clear the overflow flag to 0 by executing the software instruction clr1. if the overflow flag is set to 1, the pu lse width can be calculated as follows. pulse width = (10000h number of times the tpnovf bit was set (1) + captured value) count clock cycle remark a = 0, 1 n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 325 of 1113 sep 22, 2011 figure 7-67. register settings in pulse width measurement mode (a) tmpn control register 0 (tpnctl0) 0/1 0 0 0 0 tpnctl0 these bits select the count clock. 0: stop counting. 1: enable counting. 0/1 0/1 0/1 tpncks2 tpncks1 tpncks0 tpnce (b) tmpn control register 1 (tpnctl1) 00000 tpnctl1 110 tpnmd2 tpnmd1 tpnmd0 tpneee tpnest 1, 1, 0: pulse width measurement mode (c) tmpn i/o control register 1 (tpnioc1) 0 0 0 0 0/1 tpnioc1 these bits select the valid edge of the tipn0 pin input. these bits select the valid edge of the tipn1 pin input. 0/1 0/1 0/1 tpnis2 tpnis1 tpnis0 tpnis3 (d) tmpn option register 0 (tpnopt0) 00000 tpnopt0 overflow flag 0 0 0/1 tpnccs0 tpnovf tpnccs1 (e) tmpn counter read buffer register (tpncnt) the value of the 16-bit counter can be read by reading this register. (f) tmpn capture/compare register s 0 and 1 (tpnccr0 and tpnccr1) these registers store the 16-bit counter value upo n detection of the input of a valid edge to the tipn0/tipn1 pin. remarks 1 . tmpn i/o control register 0 (tpnioc0) and tmpn i/o control register 2 (tpnioc2) are not used in the pulse width measurement mode. 2. n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 326 of 1113 sep 22, 2011 (1) operations in pulse width measurement mode figure 7-68. timing and processing of operat ions in pulse width measurement mode <1> <2> set up the tpnctl0 register (tpnce bit = 1) tpnce bit = 0 set up the registers tpnctl0 register (tpncks0 to tpncks2 bits) tpnctl1 register tpnioc1 register tpnopt0 register be sure to set up these registers before setting the tpnce bit to 1. counting starts. the tpncks0 to tpncks2 bits can be set here. when counting is disabled (tpnce bit = 0), the counter is reset and counting stops. start stop <1> starting counting <2> stopping counting ffffh 16-bit counter 0000h tpnce bit tipn0 pin input tpnccr0 register inttpncc0 signal d 0 0000h 0000h d 1 d 2 remark n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 327 of 1113 sep 22, 2011 (2) using pulse width measurement mode (a) clearing the overflow flag (tpnovf) the overflow flag (tpnovf) can be cleared to 0 by r eading the tpnovf bit and, if its value is 1, either clearing the bit to 0 by using the clr1 instruction or by writing 8-bit data (with bi t 0 as 0) to the tpnopt0 register. 7.4.8 timer output operations the following table shows the operations and out put levels of the topn0 and topn1 pins. table 7-6. timer output control in each mode operation mode topn1 pin topn0 pin interval timer mode square wave output external event count mode ? external trigger pulse output mode external trigger pulse output one-shot pulse output mode one-shot pulse output pwm output mode pwm output square wave output free-running timer mode square wave output (only when compare function is used) pulse width measurement mode ? table 7-7. truth table of topn0 and topn1 pins under control of timer output control bits tpnioc0.tpnola bit tpnioc0.tpnoea bit tpnctl0.tpnce bit level of topna pin 0 low-level output 0 low-level output 0 1 1 low level immediately before counting, high level after counting is started 0 high-level output 0 high-level output 1 1 1 high level immediately before counting, low level after counting is started remark a = 0, 1 n = 0 to 5
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 328 of 1113 sep 22, 2011 7.5 selector in the v850es/jg3-l, the selector can be used to specify the capture trigger input for tmp as either a signal input to a port/timer alternate-function pin or peripheral i/o (tmp/uarta) signal. by using the selector, the following is possible: ? the tip10 and tip11 input signals of tmp1 can be selected as eit her the port/timer alternate-function pins (tip10 and tip11 pins) or the uarta reception al ternate-function pins (rxda0 and rxda1). when the rxda0 or rxda1 signal of uart0 or uart1 is selected, the baud rate error in lin reception transfer of uarta can be calculated. cautions 1. when using the selector , set the capture trigger input of tmp before connecting the timer. 2. when setting the selector, first disable the peripheral i/o to be connected (tmp or uarta). the capture input for the selector is specified by the following register. (1) selector operation control register 0 (selcnt0) the selcnt0 register is an 8-bit register that selects the capture trigger for tmp1. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 selcnt0 0 0 isel4 isel3 0 0 0 tip11 pin input rxda1 pin input isel4 0 1 selection of tip11 input signal (tmp1) tip10 pin input rxda0 pin input isel3 0 1 selection of tip10 input signal (tmp1) after reset: 00h r/w address: fffff308h < > < > cautions 1. when setting the isel3 and isel4 bits to 1, set the corresponding pin to the capture input mode. 2. be sure to clear bits 7 to 5 and 2 to 0 to ?0?.
v850es/jg3-l chapter 7 16-bit timer/event counter p (tmp) r01uh0165ej0700 rev.7.00 page 329 of 1113 sep 22, 2011 7.6 cautions (1) capture operation when the capture operation is used and f xx /8, f xx /16, f xx /32, f xx /64, f xx /128, f xx /256, or f xx /512 is selected as the count clock, ffffh, not 0000h, may be captured in the tpnccr0 and tpnccr 1 registers, or the capture operation may not be performed at all (the capture interrupt does not occur) if the capture trigger is input immediately after the tpnce bit is set to 1. this also occurs during the period in which no exter nal event counts are input while the capture operation is being used and an external event count input is being used as the count clock. (a) free-running timer mode count clock 0000h ffffh tpnce bit tpnccr0 register ffffh 0001h 0000h tipn0 pin input capture trigger input 16-bit counter sampling clock (f xx ) capture trigger input (b) pulse width measurement mode 0000h ffffh ffffh 0002h 0000h count clock tpnce bit tpnccr0 register tipn0 pin input capture trigger input 16-bit counter sampling clock (f xx ) capture trigger input
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 330 of 1113 sep 22, 2011 chapter 8 16-bit time r/event counter q (tmq) timer q (tmq) is a 16-bit timer/event counter. the v850es/jg3-l incorporates one tmq timer/counter, tmq0. 8.1 functions tmq0 has the following features: (1) interval timer tmq0 generates an interrupt at a preset interval and can output a square wave. (2) external event counter tmq0 counts the number of externally input signal pulses. (3) external trigger pulse output tmq0 starts counting and outputs a pulse w hen the specified external signal is input. (4) one-shot pulse output tmq0 outputs a one-shot pulse with an output width that can be freely specified. (5) pwm output tmq0 outputs a pulse with a constant cycle whose active width can be changed. the pulse duty can also be changed freely even while the timer is operating. (6) free-running timer the 16-bit counter increments fr om 0000h to ffffh and then resets. (7) pulse width measurement tmq0 can be used to measure the pulses of a signal input externally.
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 331 of 1113 sep 22, 2011 8.2 configuration tmq0 includes the following hardware. table 8-1. configuration of tmq0 item configuration registers 16-bit counter tmq0 capture/compare registers 0 to 3 (tq0ccr0 to tq0ccr3) tmq0 counter read buffer register (tq0cnt) ccr0 to ccr3 buffer registers tmq0 control registers 0, 1 (tq0ctl0, tq0ctl1) tmq0 i/o control registers 0 to 2 (tq0ioc0 to tq0ioc2) tmq0 option register 0 (tq0opt0) timer inputs 4 (tiq00 to tiq03 pins) timer outputs 4 (toq00 to toq03 pins) figure 8-1. block diagram of tmq0 tq0cnt tq0ccr0 tq0ccr1 tq0ccr2 toq00 inttq0ov ccr2 buffer register tq0ccr3 ccr3 buffer register toq01 toq02 toq03 inttq0cc0 inttq0cc1 inttq0cc2 inttq0cc3 f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 tiq00 tiq01 tiq02 tiq03 selector internal bus internal bus selector edge detector ccr0 buffer register ccr1 buffer register 16-bit counter output controller clear remark f xx : main clock frequency
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 332 of 1113 sep 22, 2011 (1) 16-bit counter this is a 16-bit counter that counts internal clocks and external events. this counter can be read by using the tq0cnt register. when the tq0ctl0.tq0ce bit is 0 and the counter is st opped, the counter value is ffffh. if the tq0cnt register is read at this time, 0000h is read. reset sets the tq0ce bit to 0, stopping th e counter, and setting its value to ffffh. (2) ccr0 buffer register this is a 16-bit compare register that co mpares the value of the 16-bit counter. when the tq0ccr0 register is used as a compare regist er, the value written to the tq0ccr0 register is transferred to the ccr0 buffer register. if the value of the 16-bit counter matches the value of the ccr0 buffer register, a compare match interrupt request signal (inttq0cc0) is generated. the ccr0 buffer register cannot be read or written directly. the ccr0 buffer register is cleared to 0000h after re set because the tq0ccr0 register is cleared to 0000h. (3) ccr1 buffer register this is a 16-bit compare register that co mpares the value of the 16-bit counter. when the tq0ccr1 register is used as a compare regist er, the value written to the tq0ccr1 register is transferred to the ccr1 buffer register. if the count value of the 16-bit counter matches the value of the ccr1 buffer register, a compare match interrupt request signal (inttq0cc1) is generated. the ccr1 buffer register cannot be read or written directly. the ccr1 buffer register is cleared to 0000h after re set because the tq0ccr1 register is cleared to 0000h. (4) ccr2 buffer register this is a 16-bit compare register that co mpares the value of the 16-bit counter. when the tq0ccr2 register is used as a compare regist er, the value written to the tq0ccr2 register is transferred to the ccr2 buffer register. if the count value of the 16-bit counter matches the value of the ccr2 buffer register, a compare match interrupt request signal (inttq0cc2) is generated. the ccr2 buffer register cannot be read or written directly. the ccr2 buffer register is cleared to 0000h after re set because the tq0ccr2 register is cleared to 0000h. (5) ccr3 buffer register this is a 16-bit compare register that co mpares the value of the 16-bit counter. when the tq0ccr3 register is used as a compare regist er, the value written to the tq0ccr3 register is transferred to the ccr3 buffer register. if the count value of the 16-bit counter matches the value of the ccr3 buffer register, a compare match interrupt request signal (inttq0cc3) is generated. the ccr3 buffer register cannot be read or written directly. the ccr3 buffer register is cleared to 0000h after re set because the tq0ccr3 register is cleared to 0000h. (6) edge detector this circuit detects the valid edges in put to the tiq00 to tiq03 pins. no edge, rising edge, falling edge, or both the rising and falling edges can be selected as the valid edge by using the tq0ioc1 and tq0ioc2 registers.
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 333 of 1113 sep 22, 2011 (7) output controller this circuit controls the output of the toq00 to toq 03 pins. the output controll er is controlled by the tq0ioc0 register. (8) selector the selector selects the count clock for the 16-bit counter . one of eight internal clocks or the input of an external event can be selected as the count clock. 8.2.1 pins used by tmq0 the input and output pins used by tmq0 are shown in table 8-2 below. when using these pins for tmq0, first set them to port mode. for details, see table 4-15 settings when pins are used for alternate functions . table 8-2. pins used by tmq0 pin no. gf gc f1 port tmq0 input tmq0 output alternate function 42 40 l8 p53 tiq00 note toq00 sib2/kr3/rtp03/ddo 39 37 l7 p50 tiq01 toq01 kr0/rtp00 40 38 k7 p51 tiq02 toq02 kr1/rtp01 41 39 j7 p52 tiq03 toq03 kr2/rtp02/ddi note the tiq00 pin functions as a c apture trigger input, as an external event input, and as an external trigger input. 8.2.2 interrupts the following five types of interrupt signals are used by tmq0: (1) inttq0cc0 this signal is generated when the value of the 16-bit count er matches the value of the ccr0 buffer register, or when a capture signal is input from the tiq00 pin. (2) inttq0cc1 this signal is generated when the value of the 16-bit count er matches the value of the ccr1 buffer register, or when a capture signal is input from the tiq01 pin. (3) inttq0cc2 this signal is generated when the value of the 16-bit count er matches the value of the ccr2 buffer register, or when a capture signal is input from the tiq02 pin. (4) inttq0cc3 this signal is generated when the value of the 16-bit count er matches the value of the ccr3 buffer register, or when a capture signal is input from the tiq03 pin. (5) inttq0ov this signal is generated when the 16-bit coun ter overflows after incr ementing up to ffffh.
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 334 of 1113 sep 22, 2011 8.3 registers the registers that control tmq0 are as follows: ? tmq0 control register 0 (tq0ctl0) ? tmq0 control register 1 (tq0ctl1) ? tmq0 i/o control register 0 (tq0ioc0) ? tmq0 i/o control register 1 (tq0ioc1) ? tmq0 i/o control register 2 (tq0ioc2) ? tmq0 option register 0 (tq0opt0) ? tmq0 capture/compare register 0 (tq0ccr0) ? tmq0 capture/compare register 1 (tq0ccr1) ? tmq0 capture/compare register 2 (tq0ccr2) ? tmq0 capture/compare register 3 (tq0ccr3) ? tmq0 counter read buffer register (tq0cnt) remark when using the functions of the tiq00 to tiq03 and toq00 to toq03 pins, see table 4-15 settings when pins are used for alternate functions .
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 335 of 1113 sep 22, 2011 (1) tmq0 control register 0 (tq0ctl0) the tq0ctl0 register is an 8-bit register that controls the operation of tmq0. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. the same value can always be written to the tq0ctl0 register by software. tq0ce tmq0 operation disabled (tmq0 reset asynchronously note ). tmq0 operation enabled. tmq0 operation started. tq0ce 0 1 tmq0 operation control tq0ctl0 0 0 0 0 tq0cks2 tq0cks1 tq0cks0 654321 after reset: 00h r/w address: fffff540h <7> 0 f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 tq0cks2 0 0 0 0 1 1 1 1 internal count clock selection tq0cks1 0 0 1 1 0 0 1 1 tq0cks0 0 1 0 1 0 1 0 1 note tq0opt0.tq0ovf bit, 16-bit counter, timer output (toq00 to toq03 pins) cautions 1. set the tq0cks2 to tq0cks 0 bits when the tq0ce bit = 0. the tq0cks2 to tq0cks0 bits can be set at the same time as changing the value of the tq0ce bit from 0 to 1. 2. be sure to clear bits 3 to 6 to ?0?. remark f xx : main clock frequency
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 336 of 1113 sep 22, 2011 (2) tmq0 control register 1 (tq0ctl1) the tq0ctl1 register is an 8-bit register that controls the operation of tmq0. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 tq0est 0 1 software trigger control tq0ctl1 tq0est tq0eee 0 0 tq0md2 tq0md1 tq0md0 <6> <5> 4 3 2 1 after reset: 00h r/w address: fffff541h generate a valid signal for external trigger input. ? in one-shot pulse output mode: a one-shot pulse is output with writing 1 to the tq0est bit as the trigger. ? in external trigger pulse output mode: a pwm waveform is output with writing 1 to the tq0est bit as the trigger. disable operation with external event count input. (perform counting using the internal count clock selected by the tq0clt0.tq0ck0 to tq0ck2 bits.) tq0eee 0 1 count clock selection 7 0 interval timer mode external event count mode external trigger pulse output mode one-shot pulse output mode pwm output mode free-running timer mode pulse width measurement mode setting prohibited tq0md2 0 0 0 0 1 1 1 1 timer mode selection tq0md1 0 0 1 1 0 0 1 1 tq0md0 0 1 0 1 0 1 0 1 enable operation with external event count input. (perform counting at the valid edge of the external event count input signal.) ? cautions 1. the tq0est bit is valid on ly in the external trigger pulse output mode or one-shot pulse output mo de. in any other mode, writing 1 to this bit is ignored. 2. external event count input is selected in the external event count mode regardless of the value of the tq0eee bit. 3. set the tq0eee and tq0md2 to tq0md0 bits after stopping the timer (by setting the tq0ctl0.tq0ce bit to 0). (however, if the same value is being written, this can be done while the tq0ce bit is 1.) the operation is not guarante ed if the tq0eee and tq0md2 to tq0md0 bits are rewritten while the tq0ce bit is 1. if the tq0eee and tq0md2 to tq0md0 bits were mistakenly rewritten while the tq0ce bit was 1, clear the tq0ce bi t to 0 and then write the bits again. 4. be sure to clear bits 3, 4, and 7 to ?0?.
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 337 of 1113 sep 22, 2011 (3) tmq0 i/o control register 0 (tq0ioc0) the tq0ioc0 register is an 8-bit register that controls the timer output (toq00 to toq03 pins). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. tq0ol3 tq0olm 0 1 toq0m pin output level setting (m = 0 to 3) note toq0m pin starts output at high level toq0m pin starts output at low level tq0ioc0 tq0oe3 tq0ol2 tq0oe2 tq0ol1 tq0oe1 tq0ol0 tq0oe0 <6> 5 <4> 3 <2> 1 after reset: 00h r/w address: fffff542h tq0oem 0 1 toq0m pin output setting (m = 0 to 3) timer output disabled ? when tq0olm bit = 0: low level is output from the toq0m pin ? when tq0olm bit = 1: high level is output from the toq0m pin 7 <0> timer output enabled (a pulse is output from the toq0m pin) note the output level of the timer out put pin (toq0m) specified by the tq0olm bit is shown below. tq0ce bit toq0m output pin 16-bit counter ? when tq0olm bit = 0 tq0ce bit toq0m output pin 16-bit counter ? when tq0olm bit = 1 cautions 1. rewrite the tq0olm and tq0oem bits when the tq0ctl0.tq0ce bit = 0. (the same value can be written when the tq0ce bit = 1.) if rewriting was mistakenly performed, clear the tq0ce bit to 0 and then set the bits again. 2. even if the tq0olm bit is manipulated when the tq0ce and tq0oem bits are 0, the t oq0m pin output level varies. remark m = 0 to 3
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 338 of 1113 sep 22, 2011 (4) tmq0 i/o control register 1 (tq0ioc1) the tq0ioc1 register is an 8-bit regist er that controls the specification of the valid edge of the capture trigger input signals (tiq00 to tiq03 pins). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. tq0is7 tq0is7 0 0 1 1 tq0is6 0 1 0 1 capture trigger input signal (tiq03 pin) valid edge setting no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges tq0ioc1 tq0is6 tq0is5 tq0is4 tq0is3 tq0is2 tq0is1 tq0is0 654321 after reset: 00h r/w address: fffff543h tq0is5 0 0 1 1 tq0is4 0 1 0 1 capture trigger input signal (tiq02 pin) valid edge detection no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges 7 0 tq0is3 0 0 1 1 tq0is2 0 1 0 1 capture trigger input signal (tiq01 pin) valid edge setting no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges tq0is1 0 0 1 1 tq0is0 0 1 0 1 capture trigger input signal (tiq00 pin) valid edge setting no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges cautions 1. rewrite the tq0is7 to tq0is0 bits when the tq0ctl0.tq0ce bit = 0. (the same value can be written when the tq0ce bit = 1.) if rewriting was mistakenly performed, clear the tq0ce bit to 0 and then set the bits again. 2. the tq0is7 to tq0is0 bits are valid only in the free-running timer mode and the pulse width measurement mode. in all other modes, a capture operation is not possible.
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 339 of 1113 sep 22, 2011 (5) tmq0 i/o control register 2 (tq0ioc2) the tq0ioc2 register is an 8-bit register that controls the specification of the vali d edge of the external event count input signal (tiq00 pin) and exter nal trigger input signal (tiq00 pin). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 tq0ees1 0 0 1 1 tq0ees0 0 1 0 1 external event count input signal (tiq00 pin) valid edge setting no edge detection (external event count invalid) detection of rising edge detection of falling edge detection of both edges tq0ioc2 0 0 0 tq0ees1 tq0ees0 tq0ets1 tq0ets0 654321 after reset: 00h r/w address: fffff544h tq0ets1 0 0 1 1 tq0ets0 0 1 0 1 external trigger input signal (tiq00 pin) valid edge setting no edge detection (external trigger invalid) detection of rising edge detection of falling edge detection of both edges 7 0 cautions 1. rewrite the tq0ees1 , tq0ees0, tq0ets1, and tq0ets0 bits when the tq0ctl0.tq0ce bit = 0. (the same value can be written when the tq0ce bit = 1.) if rewriting was mistakenly performed, clear the tq0ce bit to 0 and then set the bits again. 2. the tq0ees1 and tq0ees0 bi ts are valid only when the tq0ctl1.tq0eee bit = 1 or when the external event count mode (tq0ctl1.tq0md 2 to tq0ctl1.tq0md0 bits = 001) has been set. 3. the tq0ets1 and tq0ets0 bi ts are valid only when the external trigger pulse output mode (tq0ctl1.tq0md2 to tq0ctl1.tq0md0 bits = 010) or the one-shot pulse output mode (tq0ctl1.tq0 md2 to tq0ctl1.tq0md0 = 011) is set.
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 340 of 1113 sep 22, 2011 (6) tmq0 option register 0 (tq0opt0) the tq0opt0 register is an 8-bit re gister that specifies the capture/ compare operation and indicates the detection of an overflow. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. tq0ccs3 tq0ccsm 0 1 tq0ccrm register capture/compare selection the tq0ccsm bit setting is valid only in the free-running timer mode. compare register selected capture register selected tq0opt0 tq0ccs2 tq0ccs1 tq0ccs0 0 0 0 tq0ovf 654321 after reset: 00h r/w address: fffff545h tq0ovf set (1) reset (0) tmq0 overflow detection ? the tq0ovf bit is set when the 16-bit counter count value overflows from ffffh to 0000h in the free-running timer mode or the pulse width measurement mode. ? an interrupt request signal (inttq0ov) is generated at the same time that the tq0ovf bit is set to 1. the inttq0ov signal is not generated in modes other than the free-running timer mode and the pulse width measurement mode. ? the tq0ovf bit is not cleared even when the tq0ovf bit or the tq0opt0 register are read when the tq0ovf bit = 1. ? the tq0ovf bit can be both read and written, but the tq0ovf bit cannot be set to 1 by software. writing 1 has no influence on the operation of tmq0. overflow occurred tq0ovf bit 0 written or tq0ctl0.tq0ce bit = 0 7 <0> cautions 1. rewrite the tq0ccs 3 to tq0ccs0 bits when the tq0ctl0.tq0ce bit = 0. (the same value can be written when the tq0ce bit = 1.) if rewriting was mistakenly performed, clear the tq0ce bit to 0 and then set the bits again. 2. be sure to clear bits 1 to 3 to ?0?. remark m = 0 to 3
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 341 of 1113 sep 22, 2011 (7) tmq0 capture/compare register 0 (tq0ccr0) the tq0ccr0 register can be used as a capture register or a com pare register depending on the mode. this register can be selected as a c apture register or a compare register only in the free-running timer mode, according to the setting of the tq0opt 0.tq0ccs0 bit. in any other mode , this register can be used only as a compare register. the tq0ccr0 register can be r ead or written during operation. this register can be read or written in 16-bit units. reset sets this register to 0000h. caution accessing the tq0ccr0 register is prohibite d in the following statuses. moreover, if the system is in the wait status, the only way to cancel the wait status is to execute a reset. for details, see 3.4.9 (1) accessing speci fic on-chip peripheral i/o registers. ? when the cpu operates on the subclock a nd main clock oscillation is stopped ? when the cpu operates on th e internal oscillator clock tq0ccr0 12 10 8 6 4 2 after reset: 0000h r/w address: fffff546h 14 0 13 11 9 7 5 3 15 1 (a) function as compare register the tq0ccr0 register can be rewritten even when the tq0ctl0.tq0ce bit = 1. the set value of the tq0ccr0 register is transferred to the ccr0 buffer register . when the value of the 16-bit counter matches the value of the ccr0 buffer register, a compare match interrupt request signal (inttq0cc0) is generated. if toq00 pin output is ena bled at this time, the output of the toq00 pin is inverted (for details, see the descriptions of each operating mode.). when the tq0ccr0 register is used as a cycle register in the interval timer mode, external event count mode, external trigger pulse output mode, one-shot pulse output mode, or pwm output mode, the value of the 16-bit counter is cleared (000 0h) if its count value matches the value of the ccr0 buffer register. (b) function as capture register when the tq0ccr0 register is used as a capture regi ster in the free-running timer mode, the count value of the 16-bit counter is stored in the tq0ccr0 register if the valid edg e of the capture trigger input pin (tiq00 pin) is detected. in the pulse-width measurement mode, the count value of the 16-bit counter is stored in the tq0ccr0 register and t he 16-bit counter is cleared (0000h) if the valid edge of the capture trigger input pin (tiq00 pin) is detected. even if the capture operation and reading the tq0ccr0 register co nflict, the correct value of the tq0ccr0 register can be read.
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 342 of 1113 sep 22, 2011 the following table shows the functions of the captur e/compare register in each operation mode, and how to write data to the compare register. table 8-3. function of capture/co mpare register in each mode a nd how to write compare register operation mode capture/compare register how to write compare register interval timer compare register anytime write external event counter compare register anytime write external trigger pulse output compare register batch write one-shot pulse output compare register anytime write pwm output compare register batch write free-running timer capture/compare register anytime write pulse width measurement capture register ? remark for details about anytime write and batch write, see 8.4 (2) anytime write and batch write .
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 343 of 1113 sep 22, 2011 (8) tmq0 capture/compare register 1 (tq0ccr1) the tq0ccr1 register can be used as a capture register or a com pare register depending on the mode. this register can be selected as a c apture register or a compare register only in the free-running timer mode, according to the setting of the tq 0opt0.tq0ccs1 bit. in the pul se width measurement mode, the tq0ccr1 register can be used only as a capture register. in any other mo de, this register can be used only as a compare register. the tq0ccr1 register can be r ead or written during operation. this register can be read or written in 16-bit units. reset sets this register to 0000h. caution accessing the tq0ccr1 register is prohibite d in the following statuses. moreover, if the system is in the wait status, the only way to cancel the wait status is to execute a reset. for details, see 3.4.9 (1) accessing speci fic on-chip peripheral i/o registers. ? when the cpu operates on the subclock a nd main clock oscillation is stopped ? when the cpu operates on th e internal oscillator clock tq0ccr1 12 10 8 6 4 2 after reset: 0000h r/w address: fffff548h 14 0 13 11 9 7 5 3 15 1 (a) function as compare register the tq0ccr1 register can be rewritten even when the tq0ctl0.tq0ce bit = 1. the set value of the tq0ccr1 register is transferred to the ccr1 buffer register . when the value of the 16-bit counter matches the value of the ccr1 buffer register, a compare match interrupt request signal (inttq0cc1) is generated. if toq01 pin output is ena bled at this time, the output of the toq01 pin is inverted (for details, see the descriptions of each operating mode.). (b) function as capture register when the tq0ccr1 register is used as a capture regi ster in the free-running timer mode, the count value of the 16-bit counter is stored in the tq0ccr1 register if the valid edg e of the capture trigger input pin (tiq01 pin) is detected. in the pulse-width measurement mode, the count value of the 16-bit counter is stored in the tq0ccr1 register and t he 16-bit counter is cleared (0000h) if the valid edge of the capture trigger input pin (tiq01 pin) is detected. even if the capture operation and reading the tq0ccr1 register co nflict, the correct value of the tq0ccr1 register can be read.
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 344 of 1113 sep 22, 2011 the following table shows the functions of the captur e/compare register in each operation mode, and how to write data to the compare register. table 8-4. function of capture/co mpare register in each mode a nd how to write compare register operation mode capture/compare register how to write compare register interval timer compare register anytime write external event counter compare register anytime write external trigger pulse output compare register batch write one-shot pulse output compare register anytime write pwm output compare register batch write free-running timer capture/compare register anytime write pulse width measurement capture register ? remark for details about anytime write and batch write, see 8.4 (2) anytime write and batch write .
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 345 of 1113 sep 22, 2011 (9) tmq0 capture/compare register 2 (tq0ccr2) the tq0ccr2 register can be used as a capture register or a com pare register depending on the mode. this register can be selected as a c apture register or a compare register only in the free-running timer mode, according to the setting of the tq 0opt0.tq0ccs2 bit. in the pul se width measurement mode, the tq0ccr2 register can be used only as a capture register. in any other mo de, this register can be used only as a compare register. the tq0ccr2 register can be r ead or written during operation. this register can be read or written in 16-bit units. reset sets this register to 0000h. caution accessing the tq0ccr2 register is prohibite d in the following statuses. moreover, if the system is in the wait status, the only way to cancel the wait status is to execute a reset. for details, see 3.4.9 (1) accessing speci fic on-chip peripheral i/o registers. ? when the cpu operates on the subclock and main clock oscillation is stopped ? when the cpu operates on th e internal oscillator clock tq0ccr2 12 10 8 6 4 2 after reset: 0000h r/w address: fffff54ah 14 0 13 11 9 7 5 3 15 1 (a) function as compare register the tq0ccr2 register can be rewritten even when the tq0ctl0.tq0ce bit = 1. the set value of the tq0ccr2 register is transferred to the ccr2 buffer register . when the value of the 16-bit counter matches the value of the ccr2 buffer register, a compare match interrupt request signal (inttq0cc2) is generated. if toq02 pin output is ena bled at this time, the output of the toq02 pin is inverted (for details, see the descriptions of each operating mode.). (b) function as capture register when the tq0ccr2 register is used as a capture regi ster in the free-running timer mode, the count value of the 16-bit counter is stored in the tq0ccr2 register if the valid edg e of the capture trigger input pin (tiq02 pin) is detected. in the pulse-width measurement mode, the count value of the 16-bit counter is stored in the tq0ccr2 register and t he 16-bit counter is cleared (0000h) if the valid edge of the capture trigger input pin (tiq02 pin) is detected. even if the capture operation and reading the tq0ccr2 register co nflict, the correct value of the tq0ccr2 register can be read.
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 346 of 1113 sep 22, 2011 the following table shows the functions of the captur e/compare register in each operation mode, and how to write data to the compare register. table 8-5. function of capture/co mpare register in each mode a nd how to write compare register operation mode capture/compare register how to write compare register interval timer compare register anytime write external event counter compare register anytime write external trigger pulse output compare register batch write one-shot pulse output compare register anytime write pwm output compare register batch write free-running timer capture/compare register anytime write pulse width measurement capture register ? remark for details about anytime write and batch write, see 8.4 (2) anytime write and batch write .
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 347 of 1113 sep 22, 2011 (10) tmq0 capture/compare register 3 (tq0ccr3) the tq0ccr3 register can be used as a capture register or a com pare register depending on the mode. this register can be selected as a c apture register or a compare register only in the free-running timer mode, according to the setting of the tq 0opt0.tq0ccs3 bit. in the pul se width measurement mode, the tq0ccr3 register can be used only as a capture register. in any other mo de, this register can be used only as a compare register. the tq0ccr3 register can be r ead or written during operation. this register can be read or written in 16-bit units. reset sets this register to 0000h. caution accessing the tq0ccr3 register is prohibite d in the following statuses. moreover, if the system is in the wait status, the only way to cancel the wait status is to execute a reset. for details, see 3.4.9 (1) accessing speci fic on-chip peripheral i/o registers. ? when the cpu operates on the subclock and main clock oscillation is stopped ? when the cpu operates on th e internal oscillator clock tq0ccr3 12 10 8 6 4 2 after reset: 0000h r/w address: fffff54ch 14 0 13 11 9 7 5 3 15 1 (a) function as compare register the tq0ccr3 register can be rewritten even when the tq0ctl0.tq0ce bit = 1. the set value of the tq0ccr3 register is transferred to the ccr3 buffer register . when the value of the 16-bit counter matches the value of the ccr3 buffer register, a compare match interrupt request signal (inttq0cc3) is generated. if toq03 pin output is ena bled at this time, the output of the toq03 pin is inverted (for details, see the descriptions of each operating mode.). (b) function as capture register when the tq0ccr3 register is used as a capture regi ster in the free-running timer mode, the count value of the 16-bit counter is stored in the tq0ccr3 register if the valid edg e of the capture trigger input pin (tiq03 pin) is detected. in the pulse-width measurement mode, the count value of the 16-bit counter is stored in the tq0ccr3 register and t he 16-bit counter is cleared (0000h) if the valid edge of the capture trigger input pin (tiq03 pin) is detected. even if the capture operation and reading the tq0ccr3 register co nflict, the correct value of the tq0ccr3 register can be read.
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 348 of 1113 sep 22, 2011 the following table shows the functions of the captur e/compare register in each operation mode, and how to write data to the compare register. table 8-6. function of capture/co mpare register in each mode a nd how to write compare register operation mode capture/compare register how to write compare register interval timer compare register anytime write external event counter compare register anytime write external trigger pulse output compare register batch write one-shot pulse output compare register anytime write pwm output compare register batch write free-running timer capture/compare register anytime write pulse width measurement capture register ? remark for details about anytime write and batch write, see 8.4 (2) anytime write and batch write . (11) tmq0 counter read buffer register (tq0cnt) the tq0cnt register is a read buffer register from which the value of the 16-bit counter can be read. if this register is read when the tq0ctl0.tq0ce bit = 1, the count value of the 16-bit timer can be read. this register is read-only, in 16-bit units. the value of the tq0cnt register is cleared to 0000h when the tq0ce bit = 0. if the tq0cnt register is read at this time, the value of the 16-bit c ounter (ffffh) is not read, but 0000h is read. because the tq0ce bit is cleared to 0, the value of t he tq0cnt register is cleared to 0000h after reset. caution accessing the tq0cnt register is prohibited in the following statuses. moreover, if the system is in the wait status, the only way to cancel the wait status is to execute a reset. for details, see 3.4.9 (1) accessing speci fic on-chip peripheral i/o registers. ? when the cpu is operating on the subclo ck and main clock oscillation is stopped ? when the cpu is operating on the internal clock tq0cnt 12 10 8 6 4 2 after reset: 0000h r address: fffff54eh 14 0 13 11 9 7 5 3 15 1
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 349 of 1113 sep 22, 2011 8.4 operations tmq0 can execute the following operations: table 8-7. tmq0 operating modes operating mode tq0ctl1.tq0est bit (software trigger bit) tiq00 pin (external trigger input) capture/compare register setting compare register write count clock interval timer mode invalid invalid compare only anytime write internal/external external event count mode note 1 invalid invalid compare only anytime write external external trigger pulse output mode note 2 valid valid compare only batch write internal one-shot pulse output mode note 2 valid valid compare only anytime write internal pwm output mode invalid invalid compare only batch write internal/external free-running timer mode invalid invalid can be switched anytime write internal/external pulse width measurement mode note 2 invalid invalid capture only not applicable internal notes 1. when using the external event count mode, specify th at the valid edge of the tiq00 pin capture trigger input is not detected (by clearing the tq0ioc 1.tq0is1 and tq0ioc1.tq0is0 bits to 0). 2. when using the external trigger pulse output m ode, one-shot pulse output mode, and pulse width measurement mode, select the internal clock as t he count clock (by clearing the tq0ctl1.tq0eee bit to 0).
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 350 of 1113 sep 22, 2011 (1) basic counter operation the basic operation of the 16-bit c ounter is described below. for more details, see the descriptions of each operating mode. (a) starting counting tmq0 starts counting from ffffh in all operat ing modes, and increments as follows: ffffh, 0000h, 0001h, 0002h, 0003h?. (b) clearing tmq0 tmq0 is cleared to 0000h when its value matches the value of the compare register or when the value of tmq0 is captured upon the input of a valid capture trigger signal. note that when tmq0 increments from ffffh to 0000 h after it starts counting and immediately following an overflow, it does not mean that tmq0 has been cl eared. consequently, the inttq0ccm interrupt is not generated in this case (m = 0 to 3). (c) overflow tmq0 overflows after it increments from ffffh to 0000h in free-running timer mode and pulse width measurement mode. an overflow sets the tq0o pt0.tq0ovf bit to 1 and generates an interrupt request signal (inttq0ov). note that inttq0o v will not be generated in the following cases: ? when tmq0 has just started counting. ? when the compare value at which tmq0 is cleared is specified as ffffh. ? in pulse width measurement mode, when tmq0 in crements from ffffh to 0000h after being cleared when its value of ffffh was captured. caution after the inttq0ov overflow interrupt request signal occurs, be sure to confirm that the overflow flag (tq0ovf) is set to 1. (d) reading tmq0 while it is incrementing tmq0 can be read while it is increment ing by using the tq0cnt register. specifically, the value of tmq0 can be read by readi ng the tq0cnt register while the tq0clt0.tq0ce bit is 1. note, however, that when the tq0clt0.tq0c e bit is 0, the value of tmq0 is always ffffh and the value of the tq0cnt register is always 0000h.
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 351 of 1113 sep 22, 2011 (2) anytime write and batch write the tq0ccr0 to tq0ccr3 registers can be written ev en while tmq0 is operating (that is, while the tq0ctl0.tq0ce bit is 1), but the way the ccr0 to ccr3 buffer registers are written differs depending on the mode. the two writing methods ar e anytime write and batch write. (a) anytime write this writing method is used to transfer data from the tq0ccr0 to tq0ccr3 registers to the ccr0 to ccr3 buffer registers any time while tmq0 is operating. figure 8-2. flowchart showing basic anytime write operation start inttq0cck signal generated ? set value to tq0ccrm register ? enable timer (tq0ce bit = 1) value of tq0ccrm register transferred to ccrm buffer register rewrite tq0ccrm register new value transferred to ccrm buffer register timer operation ? 16-bit counter value matches value of ccrk buffer register note ? 16-bit counter value matches value of ccr0 buffer register ? 16-bit counter cleared and starts incrementing again inttq0cc0 signal generated initial settings note the 16-bit counter is only cleared when its value matches the value of the ccr0 buffer register, not the ccrk buffer register. remarks 1. the flowchart applies to the case when tmq0 is being used as an interval timer. 2. k = 1 to 3 m = 0 to 3
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 352 of 1113 sep 22, 2011 figure 8-3. anytime write timing tq0ce bit = 1 16-bit counter 0000h tq0ccr0 register ffffh tq0ccr1 register tq0ccr2 register tq0ccr3 register inttq0cc0 signal inttq0cc1 signal inttq0cc2 signal inttq0cc3 signal ccr0 buffer register ccr1 buffer register ccr2 buffer register ccr3 buffer register 0000h d 11 d 11 d 12 d 11 d 11 d 12 d 12 d 21 d 21 d 21 d 01 d 01 d 02 d 02 d 01 d 12 d 21 0000h d 01 d 02 0000h d 21 d 31 0000h d 31 d 31 d 31 d 31 d 31 remarks 1. d 01 , d 02 : set value of tq0ccr0 register d 11 , d 12 : set value of tq0ccr1 register d 21 : set value of tq0ccr2 register d 31 : set value of tq0ccr3 register 2. the flowchart applies to the case when tmq0 is being used as an interval timer.
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 353 of 1113 sep 22, 2011 (b) batch write this writing method is used to transfer data from the tq0ccr0 to tq0ccr3 registers to the ccr0 to ccr3 buffer registers all at once while tmq0 is opera ting. the data is transferred when the value of the 16-bit counter matches the value of the ccr0 buffer register. transfer is enabled by writing to the tq0ccr1 register. whether transfer of the ne xt data is enabled or not depends on whether the tq0ccr1 register has been written. to specify the value of the rewritten tq0ccr0 to tq0ccr3 registers as the 16-bit counter compare value (that is, the value to be transferred to the ccr0 to ccr3 buffer registers), the tq0ccr0 register must be rewritten before the value of the 16-bit count er matches the value of the ccr0 buffer register, and then the tq0ccr1 register must be written. t he value of the tq0ccr0 to tq0ccr3 registers is then transferred to the ccr0 to ccr3 buffer register s when the value of the 16-bit counter matches the value of the ccr0 buffer register. note that even if you wish to rewrite one of the tq0ccr0, tq0ccr2 and tq0ccr3 register values, you must also write t he same value to the tq0ccr1 register (that is, the same value as the value already s pecified for the tq0ccr1 register).
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 354 of 1113 sep 22, 2011 figure 8-4. flowchart showin g basic batch write operation start batch write enabled ? set value to tq0ccrm register ? enable timer (tq0ce bit = 1) value of tq0ccrm register transferred to ccrm buffer register rewrite tq0ccr0, tq0ccr2, and tq0ccr3 registers rewrite tq0ccr1 register timer operation ? 16-bit counter value matches value of ccrk buffer register note ? 16-bit counter value matches value of ccr0 buffer register ? 16-bit counter cleared and starts incrementing again ? tq0ccrk register value transferred to ccrk buffer register inttq0cc0 signal generated inttq0cck signal generated initial settings note the 16-bit counter is only cleared when its value matches the value of the ccr0 buffer register, not the ccrk buffer register. caution the process of writing to the tq0ccr1 re gister includes enabling batch write. it is therefore necessary to rewrite the tq0ccr1 register after rewriting the tq0ccr0, tq0ccr2, and tq0ccr3 registers. remarks 1. the flowchart applies to the case when tmq0 is being used in pwm output mode. 2. k = 1 to 3 m = 0 to 3
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 355 of 1113 sep 22, 2011 figure 8-5. batch write timing tq0ce bit = 1 16-bit counter tq0ccr0 register 0000h ffffh tq0ccr1 register tq0ccr2 register tq0ccr3 register inttq0cc0 signal inttq0cc1 signal inttq0cc2 signal inttq0cc3 signal ccr0 buffer register ccr1 buffer register ccr2 buffer register ccr3 buffer register 0000h d 01 d 02 d 03 0000h d 11 0000h d 21 d 12 d 21 d 12 d 21 d 21 0000h d 31 d 32 d 33 d 31 d 32 d 33 d 01 d 02 d 03 d 11 d 12 d 12 d 21 d 31 d 11 d 01 d 21 d 21 d 12 d 12 d 12 d 12 d 32 d 32 d 32 d 02 d 02 d 03 toq00 pin output toq01 pin output toq02 pin output toq03 pin output d 21 d 21 note 1 note 2 note 3 note 1 note 1 note 1 note 1 note 1 note 1 note 1 write the same value notes 1. d 02 is not transferred because the tq0ccr1 register was not written. 2. d 12 is transferred to the ccr1 buffer register upon a match with the tq0ccr0 register value (d 01 ) because the tq0ccr1 register was written (d 12 ). 3. d 12 is transferred to the ccr1 buffer register upon a match with the tq0ccr0 register value (d 12 ) because the tq0ccr1 register was written (d 12 ). remarks 1. d 01 , d 02 , d 03 : set value of tq0ccr0 register d 11 , d 12 : set value of tq0ccr1 register d 21 : set value of tq0ccr2 register d 31 , d 32 , d 33 : set value of tq0ccr3 register 2. the flowchart applies to the case when tm q0 is being used in the pwm output mode.
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 356 of 1113 sep 22, 2011 8.4.1 interval timer mode (t q0md2 to tq0md0 bits = 000) in the interval timer mode, setting the tq0ctl0.tq0ce bit to 1 generates an interrupt request signal (inttq0cc0) at a specified interval. setting the tq0ce bi t to 1 can also start the timer, which then outputs a square wave whose half cycle is equal to the interval from the toq00 pin. usually, the tq0ccr1 to tq0ccr3 registers are not used in the interval timer mode. mask interrupts from these registers by setting the interrupt mask flags (tq0ccmk1 to tq0ccmk3). remarks 1. for how to set the toq00 pin, see table 8-2 pins used by tmq0 and table 4-15 settings when pins are used for alternate functions . 2. for how to enable the inttq0cc0 interrupt signal, see chapter 21 interrupt servicing/ exception processing . figure 8-6. configuration of interval timer 16-bit counter output controller ccr0 buffer register tq0ce bit tq0ccr0 register count clock selection clear match signal toq00 pin inttq0cc0 signal figure 8-7. basic timing of op eration in interval timer mode ffffh 16-bit counter 0000h tq0ce bit toq00 pin output inttq0cc0 signal d 0 d 0 d 0 d 0 d 0 interval (d 0 + 1) interval (d 0 + 1) interval (d 0 + 1) interval (d 0 + 1) tq0ccr0 register (ccr0 buffer register)
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 357 of 1113 sep 22, 2011 when the tq0ce bit is set to 1, the va lue of the 16-bit counter is cleared fr om ffffh to 0000h in synchronization with the count clock, and the c ounter starts incrementing. at this time, the output of the toq00 pin is inverted and the set value of the tq0ccr0 register is transferred to the ccr0 buffer register. when the value of the 16-bit counter ma tches the value of the ccr0 buffer r egister, the 16-bit counter is cleared to 0000h, the output of the toq00 pin is inverted, and a compare match interrupt request signal (inttq0cc0) is generated. the interval can be calculated by using the following expression: interval = (set value of tq0ccr0 register + 1) count clock cycle an example of the register settings when the interval timer mode is used is shown in the figure below. figure 8-8. register settings in interval timer mode (1/3) (a) tmq0 control register 0 (tq0ctl0) 0/1 0 0 0 0 tq0ctl0 these bits select the count clock. 0: stop counting 1: enable counting 0/1 0/1 0/1 tq0cks2 tq0cks1 tq0cks0 tq0ce (b) tmq0 control register 1 (tq0ctl1) 0 0 0/1 note 00 tq0ctl1 0, 0, 0: interval timer mode 000 tq0md2 tq0md1 tq0md0 tq0eee tq0est 0: increment based on the count clock selected by the tq0cks0 to tq0cks2 bits. 1: increment based on the input of an external event count signal. note the tq0eee bit can only be set to 1 when the timer output (toq0k) is used. note that when setting the tq0eee bit to 1, the tq0ccr0 and tq 0ccrk registers must be set to the same value (that is, the same value as the value alread y specified for these registers). (for details, see 8.4.1 (2) (d) operation of tq 0ccr1 to tq0ccr1 registers .) (k = 1 to 3.)
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 358 of 1113 sep 22, 2011 figure 8-8. register settings in interval timer mode (2/3) (c) tmq0 i/o control register 0 (tq0ioc0) 0/1 0/1 0/1 0/1 0/1 tq0ioc0 0: disable toq00 pin output. 1: enable toq00 pin output. output level when toq00 pin is disabled: 0: low level 1: high level 0: disable toq01 pin output. 1: enable toq01 pin output. output level when toq01 pin is disabled: 0: low level 1: high level 0/1 0/1 0/1 tq0oe1 tq0ol0 tq0oe0 tq0ol1 0: disable toq02 pin output. 1: enable toq02 pin output. output level when toq02 pin is disabled: 0: low level 1: high level 0: disable toq03 pin output. 1: enable toq03 pin output. output level when toq03 pin is disabled: 0: low level 1: high level tq0oe3 tq0ol2 tq0oe2 tq0ol3 (d) tmq0 i/o control register 2 (tq0ioc2) 0 0 0 0 0/1 note tq0ioc2 these bits select the valid edge of the external event count input (tiq00 pin). 0/1 note 00 tq0ees0 tq0ets1 tq0ets0 tq0ees1 note the tq0ees1 and tq0ees0 bits can only be se t to 1 when the timer output (toq01 to toq03) is used. note that when setting these bits to 1, the tq0ccr0 to tq0ccr3 registers must be set to the same value (that is, the same value as the value already specified for these registers). (e) tmq0 counter read buffer register (tq0cnt) the value of the 16-bit counter can be read by reading this register. (f) tmq0 capture/compare register 0 (tq0ccr0) i f the tq0ccr0 register is set to d 0 , the interval is as follows: interval = (d 0 + 1) count clock cycle
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 359 of 1113 sep 22, 2011 figure 8-8. register settings in interval timer mode (3/3) (g) tmq0 capture/compare regist ers 1 to 3 (tq0ccr1 to tq0ccr3) usually, the tq0ccr1 to tq0ccr3 registers are not used in the interval timer mode. however, because the set values of the tq0ccr1 to tq0ccr 3 registers are transferred to the ccr1 to ccr3 buffer registers and a compare match interrupt request signal (inttq0cc1 to inttq0cc3) is generated when the value of the 16-bit counter ma tches the value of the ccr1 to ccr3 buffer registers, interrupts from these registers must be masked by setting the interrupt mask flags (tq0ccmk1 to tq0ccmk3). remark tmq0 i/o control register 1 (tq0ioc1) and tmq0 option register 0 (tq0opt0) are not used in the interval timer mode.
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 360 of 1113 sep 22, 2011 (1) operations in interval timer mode figure 8-9. timing and processing of operations in interval timer mode ffffh 16-bit counter 0000h tq0ce bit toq00 pin output inttq0cc0 signal d 0 d 0 d 0 d 0 <1> <2> tq0ce bit = 1 tq0ce bit = 0 set up the registers tq0ctl0 register (tq0cks0 to tq0cks2 bits) tq0ctl1 register tq0ioc0 register tq0ioc2 register tq0ccr0 register be sure to set up these registers before setting the tq0ce bit to 1. counting starts (tq0ce bit = 1). the tq0cks0 to tq0cks2 bits can be set here. when counting is disabled (tq0ce bit = 0), the counter is reset and counting stops. start stop <1> starting counting <2> stopping counting tq0ccr0 register (ccr0 buffer register)
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 361 of 1113 sep 22, 2011 (2) using interval timer mode (a) operation when tq0ccr0 register is set to 0000h when the tq0ccr0 register is set to 0000h, the inttq 0cc0 signal is generated each count clock cycle from the second clock cycle, and the output of the toq00 pin is inverted. the value of the 16-bit counter is always 0000h. figure 8-10. operation of interval time r when tq0ccr0 register is set to 0000h count clock 16-bit counter tq0ce bit tq0ccr0 register toq00 pin output inttq0cc0 signal 0000h interval time count clock cycle ffffh 0000h 0000h 0000h 0000h interval time count clock cycle
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 362 of 1113 sep 22, 2011 (b) operation when tq0ccr0 re gister is set to ffffh when the tq0ccr0 regist er is set to ffffh, the 16-bit counter increments up to ffffh and is reset to 0000h in synchronization with the next increment ti ming. the inttq0cc0 signal is then generated and the output of the toq00 pin is invert ed. at this time, an overflow interrupt request signal (inttq0ov) is not generated, nor is the overflow fl ag (tq0opt0.tq0ovf bit) set to 1. figure 8-11. operation of interval timer when tq0ccr0 register is set to ffffh ffffh 16-bit counter 0000h tq0ce bit toq00 pin output inttq0cc0 signal ffffh interval time 10000h count clock cycle interval time 10000h count clock cycle interval time 10000h count clock cycle tq0ccr0 register (ccr0 buffer register)
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 363 of 1113 sep 22, 2011 (c) notes on rewriting tq0ccr0 register when rewriting the value of the tq0ccr0 register to a smaller value, stop counting first and then change the set value. if the value of the tq0ccr0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. figure 8-12. rewriting tq0ccr0 register ffffh 16-bit counter 0000h tq0ce bit tq0ol0 bit toq00 pin output inttq0cc0 signal d 1 d 2 d 1 d 1 d 2 d 2 d 2 l interval time (1) interval time (ng) interval time (2) tq0ccr0 register (ccr0 buffer register) remark interval time (1): (d 1 + 1) count clock cycle interval time (ng): (10000h + d 2 + 1) count clock cycle interval time (2): (d 2 + 1) count clock cycle if the value of the tq0ccr0 register is changed from d 1 to d 2 while the counter value is greater than d 2 but less than d 1 , the tq0ccr0 register value is transferred to the ccr0 buffer register as soon as the register has been rewritten. consequently, the val ue that is compared with the 16-bit counter value is d 2 . because the counter value has already exceeded d 2 , however, the 16-bit counter increments to ffffh, overflows, and then increments again from 0000h. when the counter value matches d 2 , the inttq0cc0 signal is generated and the out put of the toq00 pin is inverted. therefore, the inttq0cc0 signal may not be generated at the interval ?(d 1 + 1) count clock cycle? or ?(d 2 + 1) count clock cycle? as originally expected, but instead may be generated at an interval of ?(10000h + d 2 + 1) count clock cycle?.
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 364 of 1113 sep 22, 2011 (d) operation of tq0ccr1 to tq0ccr3 registers the tq0ccr1 to tq0ccr3 registers are configur ed as follows in the interval timer mode. figure 8-13. configuration of tq0ccr1 to tq0ccr3 registers ccr0 buffer register tq0ce bit tq0ccr0 register clear match signal inttq0cc0 signal toq03 pin inttq0cc3 signal toq00 pin tq0ccr1 register ccr1 buffer register match signal toq01 pin inttq0cc1 signal tq0ccr3 register ccr3 buffer register match signal toq02 pin inttq0cc2 signal tq0ccr2 register ccr2 buffer register match signal output controller count clock selection output controller output controller output controller 16-bit counter
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 365 of 1113 sep 22, 2011 if the value of the tq0ccrk register is less than or equal to the va lue of the tq0ccr0 register, the inttq0cck signal is generated once per cycle. at the same time, the output of the toq0k pin is inverted. the toq0k pin outputs a square wave with the same cycle as that out put by the toq00 pin but with a different phase. a chart showing the timing of operations wh en the value of the tq0ccrk register (d k1 ) is less than or equal to the value of the tq0ccr0 register (d 01 ) is shown below. remark k = 1 to 3 figure 8-14. timing of operations when d 01 d k1 d 01 d 11 d 21 d 31 d 21 d 11 d 31 d 01 d 01 d 21 d 11 d 31 d 01 d 21 d 11 d 31 d 01 d 21 d 11 d 31 ffffh 16-bit counter 0000h tq0ce bit toq00 pin output inttq0cc0 signal tq0ccr1 register toq01 pin output inttq0cc1 signal tq0ccr2 register toq02 pin output inttq0cc2 signal tq0ccr3 register toq03 pin output inttq0cc3 signal tq0ccr0 register (ccr0 buffer register)
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 366 of 1113 sep 22, 2011 if the value of the tq0ccrk register is greater than the value of the tq0ccr0 register, the value of the 16-bit counter will not match the value of the tq0 ccrk register. consequently, the inttq0cck signal is not generated, nor is the ou tput of the toq0k pin changed. a chart showing the timing of operations w hen the value of the tq0ccrk register (d k1 ) is greater than the value of the tq0ccr0 register (d 01 ) is shown below. remark k = 1 to 3 figure 8-15. timing of operations when d 01 < d k1 d 01 d 11 d 21 l l l d 31 d 01 d 01 d 01 d 01 ffffh 16-bit counter 0000h tq0ce bit tq0ccr0 register toq00 pin output inttq0cc0 signal tq0ccr1 register toq01 pin output inttq0cc1 signal tq0ccr2 register toq02 pin output inttq0cc2 signal tq0ccr3 register toq03 pin output inttq0cc3 signal
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 367 of 1113 sep 22, 2011 (3) operation of interval timer b ased on input of external event count (a) operation when the 16-bit counter is increment ing based on the valid edge of the external event count input (tiq00 pin) in the interval timer mode, one external event count valid edge must be input immediately after the tq0ce bit changes from 0 to 1 to start the counter incrementing after the 16-bit counter is cleared from ffffh to 0000h. once the tq0ccr0 and tq0ccrk registers are set to 0001h (that is, the same value as was previously set), the toq0k pin output is inverted every tw o counts of the 16-bit counter (k = 1 to 3). note that the tq0ctl1.tq0eee bit can only be set to 1 when timer output (toq0k) is used based on the input of an external event count. figure 8-16. operation of interval time r based on input of external event count tq0ce bit 16-bit counter tq0ccr0 register toq01 pin output tq0ccr1 register toq02 pin output tq0ccr2 register toq03 pin output tq0ccr3 register ffffh 0000h 0001h 0001h 0001h 0001h 0001h 0001h 0001h 0001h 0001h 0001h 0001h 0001h 0001h 0001h 0001h 3 external event counts 2 external event counts 2 external event counts 2-count width 2-count width 2-count width external event count input (tiq00 pin input)
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 368 of 1113 sep 22, 2011 8.4.2 external event count mode (tq0md2 to tq0md0 bits = 001) in the external event count mode, the valid edge of the external event count input is counted when the tq0ctl0.tq0ce bit is set to 1, and an interrupt request signal (inttq0cc0) is generated each time the specified number of edges have been counted. the timer output pins (toq00 to toq03) can not be used. to use the toq01 to toq03 pins in the external event count mode, be sure to set the tq0ctl1.tq0 eee bit to 1 in the interval timer mode first. (for details, see 8.4.1 (3) operation of interval timer based on input of external event count .) usually, the tq0ccr1 to tq0ccr3 registers are not used in the external event count mode. remarks 1. for how to set the tiq00 pin, see table 8-2 pins used by tmq0 and table 4-15 settings when pins are used for alternate functions . 2. for how to enable the inttq0cc0 interrupt signal, see chapter 21 interrupt servicing/ exception processing . figure 8-17. configuration of interval timer in external event count mode 16-bit counter ccr0 buffer register tq0ce bit tq0ccr0 register edge detector clear match signal inttq0cc0 signal tiq00 pin (external event count input)
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 369 of 1113 sep 22, 2011 when the tq0ce bit is set to 1, the value of the 16-bit counter is clear ed from ffffh to 0000h. the counter increments each time the valid edge of the external even t count input is detected, a nd the value of the tq0ccr0 register is transferred to the ccr0 buffer register. when the value of the 16-bit counter ma tches the value of the ccr0 buffer r egister, the 16-bit counter is cleared to 0000h, and a compare match interrupt request signal (inttq0cc0) is generated. the inttq0cc0 signal is generated each time the valid ed ge of the external event c ount input has been detected the specified number of times (that is, the value of the tq0ccr0 register + 1). figure 8-18. basic timing of operati ons in external event count mode ffffh 16-bit counter 0000h tq0ce bit inttq0cc0 signal d 0 d 0 d 0 d 0 16-bit counter nttq0cc0 signal external event count input (tiq00 pin input) d 0 external event count interval (d 0 + 1) d 0 ? 1d 0 0000 0001 external event count interval (d 0 + 1) external event count interval (d 0 + 1) tq0ccr0 register (ccr0 buffer register) tq0ccr0 register (ccr0 buffer register) remark this figure shows the basic timing when the rising edge is specified as the valid edge of the external event count input.
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 370 of 1113 sep 22, 2011 an example of the register settings when the external ev ent count mode is used is shown in the figure below. figure 8-19. register settings in external event count mode (1/2) (a) tmq0 control register 0 (tq0ctl0) 0/1 0 0 0 0 tq0ctl0 0: stop counting 1: enable counting 000 tq0cks2 tq0cks1 tq0cks0 tq0ce (b) tmq0 control register 1 (tq0ctl1) 00000 tq0ctl1 0, 0, 1: external event count mode 001 tq0md2 tq0md1 tq0md0 tq0eee tq0est (c) tmq0 i/o control register 0 (tq0ioc0) 00000 tq0ioc0 0: disable toq00 pin output 0: disable toq01 pin output 000 tq0oe1 tq0ol0 tq0oe0 tq0ol1 tq0oe3 tq0ol2 tq0oe2 tq0ol3 0: disable toq02 pin output 0: disable toq03 pin output (d) tmq0 i/o control register 2 (tq0ioc2) 0 0 0 0 0/1 tq0ioc2 select valid edge of external event count input. 0/1 0 0 tq0ees0 tq0ets1 tq0ets0 tq0ees1 (e) tmq0 counter read buffer register (tq0cnt) the value of the 16-bit counter can be read by reading this register.
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 371 of 1113 sep 22, 2011 figure 8-19. register settings in external event count mode (2/2) (f) tmq0 capture/compare register 0 (tq0ccr0) when the tq0ccr0 register is set to d 0 , the counter is cleared and a compare match interrupt request signal (inttq0cc0) is generated when the number of external events reaches (d 0 + 1). (g) tmq0 capture/compare regist ers 1 to 3 (tq0ccr1 to tq0ccr3) the tq0ccr1 to tq0ccr3 register s are not usually used in the external event count mode. however, because the set values of the tq0ccr1 to tq0ccr3 registers are transferred to the ccr1 to ccr3 buffer registers and a compare match inte rrupt request signal (inttq0cc1 to inttq0cc3) is generated when the value of the 16-bit counter matches the value of the ccr1 to ccr3 buffer registers, interrupts from these registers must be masked by setting the interrupt mask flags (tq0ccmk1 to tq0ccmk3). cautions 1. do not set the tq0ccr0 regist er to 0000h in the external event count mode. 2. timer output cannot be used in the external event count mode. when using the timer output based on the input of an ext ernal event count, first set the operating mode to interval mode, an d then specify ?operation enabled? for the external event count input (by setting the tq0ctl1.tq 0md2 to tq0md0 bits to 0, 0, 0 and setting the tq0ctl1.tq0eee bit to 1). ( for details, see 8.4.1 (3) operation of interval timer based on inpu t of external event count.) 3. when an external clock is used as the count clock, th e external clock can be input only from the tiq00 pin. at this time, set the tq0ioc1.tq0is1 and tq0ioc1.tq0is0 bits to 0, 0 (capture trig ger input (tiq00 pin): no edge detection). remark tmq0 i/o control register 1 (tq0ioc1) and tmq0 option register 0 (tq0opt0) are not used in the external event count mode.
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 372 of 1113 sep 22, 2011 (1) operations in external event count mode figure 8-20. timing and processing of oper ations in external event count mode ffffh 16-bit counter 0000h tq0ce bit inttq0cc0 signal d 0 d 0 d 0 d 0 <1> <2> tq0ce bit = 1 tq0ce bit = 0 set up the registers tq0ctl0 register (tq0cks0 to tq0cks2 bits) tq0ctl1 register tq0ioc0 register tq0ioc2 register tq0ccr0 register be sure to set up these registers before setting the tq0ce bit to 1. counting starts (tq0ce bit = 1). the tq0cks0 to tq0cks2 bits can be set here. when counting is disabled (tq0ce bit = 0), the counter is reset and counting stops. start stop <1> starting counting <2> stopping counting tq0ccr0 register (ccr0 buffer register)
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 373 of 1113 sep 22, 2011 (2) using external event count mode (a) operation when tq0ccr0 re gister is set to ffffh when the tq0ccr0 register is set to ffffh, the 16-bit counter increments up to ffffh upon detection of the valid edge of the external event count signal and is reset to 0000h in synchronization with the next increment timing. the inttq0cc0 signal is then gene rated. at this time, the tq0opt0.tq0ovf bit is not set to 1. figure 8-21. operation when tq0 ccr0 register is set to ffffh ffffh 16-bit counter 0000h tq0ce bit tq0ccr0 register inttq0cc0 signal ffffh external event count signal interval external event count signal interval external event count signal interval
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 374 of 1113 sep 22, 2011 (b) notes on rewriting tq0ccr0 register when rewriting the value of the tq0ccr0 register to a smaller value, stop counting first and then change the set value. if the value of the tq0ccr0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. figure 8-22. rewriting tq0ccr0 register ffffh 16-bit counter 0000h tq0ce bit inttq0cc0 signal d 1 d 2 d 1 d 1 d 2 d 2 d 2 external event count signal interval (1) (d 1 + 1) external event count signal interval (ng) (10000h + d 2 + 1) external event count signal interval (2) (d 2 + 1) tq0ccr0 register (ccr0 buffer register) if the value of the tq0ccr0 register is changed from d 1 to d 2 while the counter value is greater than d 2 but less than d 1 , the tq0ccr0 register value is transferred to the ccr0 buffer register as soon as the register has been rewritten. consequently, the val ue that is compared with the 16-bit counter value is d 2 . because the counter value has already exceeded d 2 , however, the 16-bit counter increments up to ffffh, overflows, and then increment s up again from 0000 h. when the counter value matches d 2 , the inttq0cc0 signal is generated. therefore, the inttq0cc0 signal may not be generat ed at the valid edge of the external event count signal when the external event count is ?(d 1 + 1)? or ?(d 2 + 1)? as originally expected, but instead may be generated at the valid edge of the external event count signal when the external event count is ?(10000h + d 2 + 1)?.
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 375 of 1113 sep 22, 2011 (c) operation of tq0ccr1 to tq0ccr3 registers the tq0ccr1 to tq0ccr3 registers are configured as follows in the external event count mode. figure 8-23. configuration of tq0ccr1 to tq0ccr3 registers ccr0 buffer register tq0ce bit tq0ccr0 register clear match signal inttq0cc0 signal inttq0cc3 signal tiq00 pin tq0ccr1 register ccr1 buffer register match signal inttq0cc1 signal tq0ccr3 register ccr3 buffer register match signal inttq0cc2 signal tq0ccr2 register ccr2 buffer register match signal 16-bit counter edge detector
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 376 of 1113 sep 22, 2011 if the value of the tq0ccrk register is less than or equal to the va lue of the tq0ccr0 register, the inttq0cck signal is generated once per cycle. a chart showing the timing of operations wh en the value of the tq0ccrk register (d k1 ) is less than or equal to the value of the tq0ccr0 register (d 01 ) is shown below. remark k = 1 to 3 figure 8-24. timing of operations when d 01 d k1 d 01 d 11 d 21 d 31 d 21 d 11 d 31 d 01 d 01 d 21 d 11 d 31 d 01 d 21 d 11 d 31 d 01 d 21 d 11 d 31 ffffh 16-bit counter 0000h tq0ce bit inttq0cc0 signal tq0ccr1 register inttq0cc1 signal tq0ccr2 register inttq0cc2 signal tq0ccr3 register inttq0cc3 signal tq0ccr0 register (ccr0 buffer register)
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 377 of 1113 sep 22, 2011 if the value of the tq0ccrk register is greater than the value of the tq0ccr0 register, the value of the 16-bit counter will not match the valu e of the tq0ccrk register and the inttq0cck signal will not be generated. a chart showing the timing of operations w hen the value of the tq0ccrk register (d k1 ) is greater than the value of the tq0ccr0 register (d 01 ) is shown below. remark k = 1 to 3 figure 8-25. timing of operations when d 01 < d k1 d 01 d 11 d 21 l l l d 31 d 01 d 01 d 01 d 01 ffffh 16-bit counter 0000h tq0ce bit inttq0cc0 signal tq0ccr1 register inttq0cc1 signal tq0ccr2 register inttq0cc2 signal tq0ccr3 register inttq0cc3 signal tq0ccr0 register (ccr0 buffer register)
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 378 of 1113 sep 22, 2011 8.4.3 external trigger pulse output m ode (tq0md2 to tq0md0 bits = 010) in the external trigger pulse output mode, when the tq0ct l0.tq0ce bit is set to 1, tmq0 waits for a trigger, which is the valid edge of the external trigger input sig nal, and starts incrementing when this trigger is detected. tmq0 then outputs a pwm waveform from the toq01 to toq03 pins. pulses can also be output by generating a software trigger instead of using the external trigger. when using a software trigger instead of the external trigger, a square wave that has one cycle of the pwm waveform as half its cycle can also be output from the toq00 pin. remarks 1. for how to set the tiq00 and toq00 to toq03 pins, see table 8-2 pins used by tmq0 and table 4-15 settings when pins are used for alternate functions . 2. for how to enable the inttq0cc0 to inttq0cc3 interrupt signals, see chapter 21 interrupt servicing/exception processing . figure 8-26. configuration of tmq0 in external trigger pulse output mode tiq00 pin s r s r s r ccr0 buffer register tq0ce bit tq0ccr0 register clear match signal inttq0cc0 signal toq03 pin toq00 pin transfer tq0ccr1 register ccr1 buffer register match signal toq01 pin inttq0cc1 signal transfer transfer tq0ccr3 register ccr3 buffer register match signal transfer toq02 pin inttq0cc2 signal tq0ccr2 register ccr2 buffer register match signal 16-bit counter count clock selection count start control edge detector software trigger generation output controller (rs-ff) output controller (rs-ff) output controller (toggle) output controller (rs-ff) inttq0cc3 signal
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 379 of 1113 sep 22, 2011 figure 8-27. basic timing of operations in external trigger pulse output mode d 1 d 2 d 3 d 1 d 2 d 3 d 1 d 2 d 1 d 1 d 2 d 3 d 0 d 1 d 3 d 2 d 0 d 0 d 0 ffffh 16-bit counter 0000h tq0ce bit external trigger input (tiq00 pin input) inttq0cc0 signal toq00 pin output note inttq0cc1 signal toq01 pin output inttq0cc2 signal toq02 pin output inttq0cc3 signal toq03 pin output tq0ccr0 register (ccr0 buffer register) tq0ccr1 register (ccr1 buffer register) tq0ccr2 register (ccr2 buffer register) tq0ccr3 register (ccr3 buffer register) active level width (d 1 ) active level width (d 1 ) active level width (d 1 ) active level width (d 1 ) active level width (d 1 ) active level width (d 2 ) active level width (d 2 ) active level width (d 2 ) active level width (d 3 ) active level width (d 3 ) cycle (d 0 + 1) cycle (d 0 + 1) wait for trigger note the output from the toq00 pin can also be used as the input to the tiq 00 pin. when using the output from the toq00 pin as the in put to the tiq00 pin, use a softwa re trigger instead of an external trigger.
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 380 of 1113 sep 22, 2011 when the tq0ce bit is set to 1, tmq0 waits for a trigger . when the trigger is generated, the 16-bit counter is cleared from ffffh to 0000h, starts incrementing, and outputs a pwm waveform from the toq0k pin. if the trigger is generated again while the counter is incr ementing, the counter is cl eared to 0000h and restarts incrementing, and the output of the toq 00 pin is inverted. (the toq0k pin outputs a high level signal regardless of the status (high/low) when a trigger occurs.) the active level width, cycle, and duty factor of the pwm waveform can be calculated as follows. active level width = (set value of tq0ccrk register) count clock cycle cycle = (set value of tq0ccr0 register + 1) count clock cycle duty factor = (set value of tq0ccrk regist er)/(set value of tq0ccr0 register + 1) the inttq0cc0 compare match interrupt request signal is generated when the 16-bit counter increments next time after its value matches the value of the ccr0 buffer register, and the 16-bit counter is cleared to 0000h. the inttq0cck compare match interrupt request signal is gene rated when the value of the 16-bit counter matches the value of the ccrk buffer register. either the valid edge of the external tr igger input signal or setting the softwar e trigger (tq0ctl1.tq0est bit) to 1 is used as the trigger. remark k = 1 to 3 figure 8-28. register settings in exte rnal trigger pulse output mode (1/3) (a) tmq0 control register 0 (tq0ctl0) 0/1 0 0 0 0 tq0ctl0 these bits select the count clock. 0: stop counting. 1: enable counting. 0/1 0/1 0/1 tq0cks2 tq0cks1 tq0cks0 tq0ce
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 381 of 1113 sep 22, 2011 figure 8-28. register settings in exte rnal trigger pulse output mode (2/3) (b) tmq0 control register 1 (tq0ctl1) 0 0/1 0 0 0 tq0ctl1 writing 1 generates a software trigger. 010 tq0md2 tq0md1 tq0md0 tq0eee tq0est 0, 1, 0: external trigger pulse output mode (c) tmq0 i/o control register 0 (tq0ioc0) 0/1 0/1 0/1 0/1 0/1 tq0ioc0 0: disable toq00 pin output. 1: enable toq00 pin output. output level when toq00 pin is disabled: 0: low level 1: high level 0: disable toq01 pin output. 1: enable toq01 pin output. active level of toq01 pin output: 0: high level 1: low level 0/1 0/1 note 0/1 note tq0oe1 tq0ol0 tq0oe0 tq0ol1 toq0k pin output 16-bit counter ? when tq0olk bit is 0: toq0k pin output 16-bit counter ? when tq0olk bit is 1: tq0oe3 tq0ol2 tq0oe2 tq0ol3 active level of toq03 pin output: 0: high level 1: low level 0: disable toq02 pin output. 1: enable toq02 pin output. active level of toq02 pin output: 0: high level 1: low level 0: disable toq03 pin output. 1: enable toq03 pin output. note set this bit to 0 when not using the toq00 pin in external trigger pulse output mode.
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 382 of 1113 sep 22, 2011 figure 8-28. register settings in exte rnal trigger pulse output mode (3/3) (d) tmq0 i/o control register 2 (tq0ioc2) 00000 tq0ioc2 these bits select the valid edge of the external trigger input. 0 0/1 0/1 tq0ees0 tq0ets1 tq0ets0 tq0ees1 (e) tmq0 counter read buffer register (tq0cnt) the value of the 16-bit counter can be read by reading this register. (f) tmq0 capture/compare regist ers 0 to 3 (tq0ccr0 to tq0ccr3) if the tq0ccr0 register is set to d 0 , the tq0ccr1 register is set to d 1 , the tq0ccr2 register is set to d 2 , and the tq0ccr3 register is set to d 3 , the pwm waveform is as follows: pwm waveform cycle = (d 0 + 1) count clock cycle active level width of pwm waveform from toq01 pin = d 1 count clock cycle active level width of pwm waveform from toq02 pin = d 2 count clock cycle active level width of pwm waveform from toq03 pin = d 3 count clock cycle remarks 1. tmq0 i/o control register 1 (tq0ioc1) and tmq0 option register 0 (tq0opt0) are not used in the external trigger pulse output mode. 2. updating tmq0 capture/compare register 2 (tq0ccr2) and tmq0 capture/compare register 3 (tq0ccr3) is enabled by writ ing to tmq0 capture/compare register 1 (tq0ccr1).
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 383 of 1113 sep 22, 2011 (1) operations in external trigger pulse output mode figure 8-29. timing and processing of operations in external trigger pulse output mode (1/2) d 10 d 10 d 10 d 20 d 30 d 00 d 11 d 21 d 01 d 31 d 11 d 21 d 00 d 31 d 20 d 30 d 00 d 21 d 00 d 31 d 11 d 21 d 00 d 31 ffffh 16-bit counter 0000h tq0ce bit external trigger input (tiq00 pin input) tq0ccr0 register ccr0 buffer register inttq0cc0 signal tq0ccr1 register ccr1 buffer register inttq0cc1 signal toq01 pin output tq0ccr2 register ccr2 buffer register inttq0cc2 signal toq02 pin output tq0ccr3 register ccr3 buffer register inttq0cc3 signal toq03 pin output d 00 d 01 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 10 d 11 d 10 d 11 d 10 d 11 d 20 d 21 d 20 d 21 d 20 d 21 d 21 d 30 d 31 d 30 d 31 d 30 d 31 d 30 d 31 <1> <2> <3> <4> <5> <6> <7> d 11 d 11 d 20 d 10 toq00 pin output (only when software trigger is used)
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 384 of 1113 sep 22, 2011 figure 8-29. timing and processing of operations in external trigger pulse output mode (2/2) start <1> starting counting tq0ce bit = 1 set up the registers tq0ctl0 register (tq0cks0 to tq0cks2 bits) tq0ctl1 register tq0ioc0 register tq0ioc2 register tq0ccr0 to tq0ccr3 registers be sure to set up these registers before setting the tq0ce bit to 1. after setting the tq0ccrm registers, their values are transferred to the ccrm buffer registers when the counter is cleared. after setting the tq0ccrm registers, their values are transferred to the ccrm buffer registers when the counter is cleared. after setting the tq0ccrm registers, their values are transferred to the ccrm buffer registers when the counter is cleared. disables counting. counting starts (tq0ce bit = 1). the tq0cks0 to tq0cks2 bits can be set here. waiting for trigger after setting the tq0ccrm registers, their values are transferred to the ccrm buffer registers when the counter is cleared. after setting the tq0ccrm registers, their values are transferred to the ccrm buffer registers when the counter is cleared. <2> changing both the cycle and the duty when changing both the cycle and the duty, be sure to write to the tq0ccr0, tq0ccr2, and tq0ccr3 registers before writing to the tq0ccr1 register. <3> changing the cycle the tq0ccr1 register must be written (the same value) even when only changing the cycle setting. <4> changing the duty when changing the duty, be sure to write to the tq0ccr2 and tq0ccr3 registers before writing to the tq0ccr1 register. <5> changing the duty of the toq02 and toq03 outputs the tq0ccr1 register must be written (the same value) even when only changing the duty of the toq02 and toq03 outputs. <6> changing the duty of the toq01 output only the tq0ccr1 register has to be written when only changing the duty of the toq01 output. <7> stopping counting tq0ce bit = 0 set the tq0ccr2 and tq0ccr3 registers set the tq0ccr1 register set the tq0ccr2 and tq0ccr3 registers set the tq0ccr1 register stop set the tq0ccr1 register set the tq0ccr0 register set the tq0ccr1 register set the tq0ccr0, tq0ccr2, and tq0ccr3 registers set the tq0ccr1 register remark m = 0 to 3
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 385 of 1113 sep 22, 2011 (2) using external trigger pulse output mode how to change the pwm waveform in the external trigger pulse output mode is described below. (a) changing the pwm waveform wh ile the counter is incrementing to change the pwm waveform while the counter is in crementing, write to the tq0ccr1 register after changing the waveform setting. when rewriting t he tq0ccrk register after writing to the tq0ccr1 register, do so after the inttq0cc0 signal has been detected.
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 386 of 1113 sep 22, 2011 figure 8-30. changing pwm wavefo rm while counter is incrementing d 30 d 00 d 01 d 30 d 30 d 20 d 20 d 20 d 21 d 11 d 00 d 00 d 31 d 01 d 01 d 21 d 11 d 31 d 10 d 10 d 10 d 00 d 11 d 10 d 11 d 10 d 21 d 20 d 21 d 20 d 31 d 30 d 31 d 30 d 00 d 01 ffffh 16-bit counter 0000h tq0ce bit external trigger input (tiq00 pin input) tq0ccr0 register ccr0 buffer register inttq0cc0 signal toq00 pin output note tq0ccr1 register ccr1 buffer register inttq0cc1 signal toq01 pin output tq0ccr2 register ccr2 buffer register inttq0cc2 signal toq02 pin output tq0ccr3 register ccr3 buffer register inttq0cc3 signal toq03 pin output rewrite the tq0ccr1 register after rewriting the tq0ccr0, tq0ccr2, and tq0ccr3 registers. note the output from the toq00 pin ca n also be used as the input to the tiq00 pin. when using the output from the toq00 pin as the input to the tiq00 pin, us e a software trigger instead of an external trigger.
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 387 of 1113 sep 22, 2011 in order to transfer data from the tq0ccrm register to the ccrm buffer register, the tq0ccr1 register must be written. after data is written to the tq0ccr1 register, the valu e written to the tq0ccrm register is transferred to the ccrm buffer register in synchron ization with clearing of the 16-bit counter, and is used as the value to be compared with the 16-bit counter value. <1> to change both the cycle and active level width of the pwm waveform, first set the cycle to the tq0ccr0 register and then set the active level width to the tq0ccr2 and tq0ccr3 registers, before setting the active level width to the tq0ccr1 register. <2> to change only the cycle of the pwm waveform, first set the cycle to th e tq0ccr0 register, and then write the same value to the tq0ccr1 register (that is, the same value as the value already specified for the tq0ccr1 register). <3> to change only the active level width (duty facto r) of the pwm waveform, first set the active level width to the tq0ccr2 and tq0ccr3 registers, and then set the active level width to the tq0ccr1 register. <4> to change only the active level width (duty facto r) of the pwm waveform output from the toq01 pin, only the tq0ccr1 register has to be set. <5> to change only the active level width (duty fa ctor) of the pwm waveform output from the toq02 and toq03 pins, first set the active level width to the tq0ccr2 and tq0ccr3 registers, and then write the same value to the tq 0ccr1 register (that is, the sa me value as the value already specified for the tq0ccr1 register). caution to rewrite the tq0ccr0 to tq0ccr3 re gisters after writing the tq0ccr1 register, do so after the inttq0cc0 signal has been generated; otherwise, the value of the ccrm buffer register may become undefine d because the timing of transferring data from the tq0ccrm register to the ccrm buffer register conflicts with writing the tq0ccrm register. remark m = 0 to 3
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 388 of 1113 sep 22, 2011 (b) outputting a 0% or 100% pwm waveform to output a 0% waveform, clear the tq0ccrk register to 0000h. note that if the set value of the tq0ccr0 register is ffffh, the inttq0cck signal is generated periodically. figure 8-31. outputting 0% pwm waveform d 0 0000h d 0 0000h d 0 0000h d 0 0000 ffff 0000 d 0 0000 0001 count clock 16-bit counter tq0ce bit trigger input tq0ccr0 register tq0ccrk register inttq0cc0 signal inttq0cck signal toq0k pin output d 0 ? 1d 0 ? 1 remark k = 1 to 3
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 389 of 1113 sep 22, 2011 to output a 100% waveform, set the value of tq 0ccr0 register + 1 to the tq0ccrk register. if the value of the tq0ccr0 register is ffffh, a 100% waveform cannot be output. figure 8-32. outputting 100% pwm waveform d 0 d 0 d 0 d 0 0000 ffff 0000 d 0 0000 0001 count clock 16-bit counter tq0ce bit trigger input tq0ccr0 register tq0ccrk register inttq0cc0 signal inttq0cck signal toq0k pin output d 0 + 1 d 0 + 1 d 0 + 1 d 0 ? 1 d 0 ? 1 remark k = 1 to 3
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 390 of 1113 sep 22, 2011 (c) detection of trigger immediately before or after in ttq0cck generation if the trigger is detected immediately after the inttq 0cck signal is generated, the 16-bit counter is immediately cleared to 0000h, the output signal of the toq0k pin is set to the active level, and the counter continues incrementing. co nsequently, the inactive period of the pwm waveform is shortened. figure 8-33. detection of trigger immediat ely after inttq0cck signal was generated 16-bit counter ccrk buffer register inttq0cck signal toq0k pin output external trigger input (tiq00 pin input) d k d k ? 1 0000 ffff 0000 shortened d k remark k = 1 to 3 if the trigger is detected immediately before the in ttq0cck signal is generated, the inttq0cck signal is not generated, and the 16-bit c ounter is cleared to 0000h and cont inues incrementing. the output signal of the toq0k pin remains active. consequ ently, the active period of the pwm waveform is extended. figure 8-34. detection of trigger immediat ely before inttq0cck signal is generated 16-bit counter ccrk buffer register inttq0cck signal toq0k pin output external trigger input (tiq00 pin input) d k d k ? 2d k ? 1d k 0000 ffff 0000 0001 extended remark k = 1 to 3
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 391 of 1113 sep 22, 2011 (d) detection of trigger immediately before or after in ttq0cc0 generation if the trigger is detected immediately after the intt q0cc0 signal is generated, the 16-bit counter is cleared to 0000h and continues incrementing. t herefore, the active period of the toq0k pin is extended by the amount of time between the genera tion of the inttq0cc0 signal and the detection of the trigger. figure 8-35. detection of trigger immediat ely after inttq0cc0 signal was generated 16-bit counter ccr0 buffer register inttq0cc0 signal toq0k pin output external trigger input (tiq00 pin input) d 0 d 0 ? 1d 0 0000 ffff 0000 0000 extended remark k = 1 to 3 if the trigger is detected immediately before the in ttq0cc0 signal is generated, the inttq0cc0 signal is not generated. the 16-bit counter is cleared to 0000h , the toq0k pin output is set to the active level, and the counter continues incrementing. consequent ly, the inactive period of the pwm waveform is shortened. figure 8-36. detection of trigger immediat ely before inttq0cc0 signal is generated 16-bit counter ccr0 buffer register inttq0cc0 signal toq0k pin output external trigger input (tiq00 pin input) d 0 d 0 ? 1d 0 0000 ffff 0000 0001 shortened remark k = 1 to 3
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 392 of 1113 sep 22, 2011 (e) timing of generating the compare ma tch interrupt request signal (inttq0cck) in the external trigger pulse output mode, the in ttq0cck signal is generated when the value of the 16-bit counter matches the val ue of the tq0ccrk register. figure 8-37. timing of generating comp are match interrupt signal (inttq0cck) count clock 16-bit counter tq0ccrk register toq0k pin output inttq0cck signal d 1 d 1 ? 2d 1 ? 1d 1 d 1 + 1 d 1 + 2 remark k = 1 to 3
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 393 of 1113 sep 22, 2011 8.4.4 one-shot pulse output mode (tq0md2 to tq0md0 bits = 011) in the one-shot pulse output mode, when the tq0ctl0.tq0ce bit is set to 1, tmq0 waits for a trigger, which is the valid edge of the external trigger input, and starts incrementing when this trigger is detected. tmq0 then outputs a one-shot pulse from the toq01 to toq03 pins. instead of the external trigger, a software trigger can al so be generated to output the pulse. when the software trigger is used, the toq00 pin outputs the active level signal while the 16-bit c ounter is incrementi ng, and the inactive level signal when the counter is stopped (waiting for a trigger). remarks 1. for how to set the tiq00 and toq00 to toq03 pins, see table 8-2 pins used by tmq0 and table 4-15 settings when pins are used for alternate functions . 2. for how to enable the inttq0cc0 to inttq0cc3 interrupt signals, see chapter 21 interrupt servicing/exception processing . figure 8-38. configuration of tmq0 in one-shot pulse output mode ccr0 buffer register tq0ce bit tq0ccr0 register clear match signal inttq0cc0 signal toq03 pin inttq0cc3 signal toq00 pin tiq00 pin transfer s r s r tq0ccr1 register ccr1 buffer register match signal toq01 pin inttq0cc1 signal transfer transfer s r tq0ccr3 register ccr3 buffer register match signal transfer toq02 pin inttq0cc2 signal s r tq0ccr2 register ccr2 buffer register match signal 16-bit counter count clock selection count start control edge detector software trigger generation output controller (rs-ff) output controller (rs-ff) output controller (rs-ff) output controller (rs-ff)
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 394 of 1113 sep 22, 2011 figure 8-39. basic timing of operations in one-shot pulse output mode d 0 d 1 d 2 d 3 d 1 d 2 d 3 d 0 d 1 d 2 d 3 d 0 d 1 d 2 d 3 d 0 delay (d 1 ) active level width (d 0 ? d 1 + 1) delay (d 1 ) active level width (d 0 ? d 1 + 1) delay (d 1 ) active level width (d 0 ? d 1 + 1) delay (d 2 ) active level width (d 0 ? d 2 + 1) delay (d 2 ) active level width (d 0 ? d 2 + 1) delay (d 2 ) active level width (d 0 ? d 2 + 1) delay (d 3 ) active level width (d 0 ? d 3 + 1) delay (d 3 ) active level width (d 0 ? d 3 + 1) delay (d 3 ) active level width (d 0 ? d 3 + 1) ffffh 16-bit counter 0000h tq0ce bit external trigger input (tiq00 pin input) tq0ccr0 register inttq0cc0 signal toq00 pin output note tq0ccr1 register inttq0cc1 signal toq01 pin output tq0ccr2 register inttq0cc2 signal toq02 pin output tq0ccr3 register inttq0cc3 signal toq03 pin output wait for trigger note the output from the toq00 pin ca n also be used as the input to the tiq00 pin. when using the output from the toq00 pin as the input to the tiq00 pin, us e a software trigger instead of an external trigger.
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 395 of 1113 sep 22, 2011 when the tq0ce bit is set to 1, tmq0 waits for a trigger . when the trigger is generated, the 16-bit counter is cleared from ffffh to 0000h, starts incrementing, and out puts a one-shot pulse from the toq0k pin. after the one-shot pulse is output, the 16-bit counter is set to 0000h, st ops incrementing, and waits for a trigger. if a trigger is generated again while the one-shot pul se is being output, it is ignored. the output delay period and active level width of the one-shot pulse can be calculated as follows: output delay period = (set value of tq0ccrk register) count clock cycle active level width = (set value of tq0ccr0 register ? set value of tq0ccrk register + 1) count clock cycle the inttq0cc0 compare match interrupt request signal is generated when the 16-bit counter increments next time after its value matches the value of the ccr0 bu ffer register. the inttq0cck compare match interrupt request signal is generated when the value of the 16-bit co unter matches the value of the ccrk buffer register. either the valid edge of the external tr igger input signal or setting the softwar e trigger (tq0ctl1.tq0est bit) to 1 is used as the trigger. remark k = 1 to 3 figure 8-40. register settings in one-shot pulse output mode (1/3) (a) tmq0 control register 0 (tq0ctl0) 0/1 0 0 0 0 tq0ctl0 these bits select the count clock. 0: stop counting. 1: enable counting. 0/1 0/1 0/1 tq0cks2 tq0cks1 tq0cks0 tq0ce (b) tmq0 control register 1 (tq0ctl1) 0 0/1 0 0 0 tq0ctl1 writing 1 generates a software trigger. 011 tq0md2 tq0md1 tq0md0 tq0eee tq0est 0, 1, 1: one-shot pulse output mode
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 396 of 1113 sep 22, 2011 figure 8-40. register settings in one-shot pulse output mode (2/3) (c) tmq0 i/o control register 0 (tq0ioc0) toq0k pin output 16-bit counter ? when tq0olk bit is 0: toq0k pin output 16-bit counter ? when tq0olk bit is 1: 0/1 0/1 0/1 0/1 0/1 tq0ioc0 0: disable toq00 pin output. 1: enable toq00 pin output. output level when toq00 pin is disabled: 0: low level 1: high level 0: disable toq01 pin output. 1: enable toq01 pin output. active level of toq01 pin output: 0: high level 1: low level 0/1 0/1 note 0/1 note tq0oe1 tq0ol0 tq0oe0 tq0ol1 tq0oe3 tq0ol2 tq0oe2 tq0ol3 active level of toq03 pin output: 0: high level 1: low level 0: disable toq02 pin output. 1: enable toq02 pin output. active level of toq02 pin output: 0: high level 1: low level 0: disable toq03 pin output. 1: enable toq03 pin output. (d) tmq0 i/o control register 2 (tq0ioc2) 00000 tq0ioc2 these bits select the valid edge of the external trigger input. 0 0/1 0/1 tq0ees0 tq0ets1 tq0ets0 tq0ees1 (e) tmq0 counter read buffer register (tq0cnt) the value of the 16-bit counter can be read by reading this register. note clear this bit to 0 when the toq00 pin is not used in the one-shot pulse output mode.
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 397 of 1113 sep 22, 2011 figure 8-40. register settings in one-shot pulse output mode (3/3) (f) tmq0 capture/compare register s 0 to 3 (tq0ccr0 to tq0ccr3) if the tq0ccr0 register is set to d 0 and the tq0ccrk register is set to d k , the one-shot pulse is as follows: one-shot pulse active level width = (d 0 ? d k + 1) count clock cycle one-shot pulse output delay period = d k count clock cycle caution one-shot pulses are not output from the toq0k pin in the one-shot pulse output mode if the value of the tq0ccrk re gister is greater than the value of the tq0ccr0 register. remarks 1. tmq0 i/o control register 1 (tq0ioc1) and tmq0 option register 0 (tq0opt0) are not used in the one-shot pulse output mode. 2. k = 1 to 3
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 398 of 1113 sep 22, 2011 (1) operations in one-shot pulse output mode figure 8-41. timing and processing of operati ons in one-shot pul se output mode (1/2) ffffh 16-bit counter 0000h tq0ce bit external trigger input (tiq00 pin input) tq0ccr0 register inttq0cc0 signal tq0ccr1 register inttq0cc1 signal toq01 pin output tq0ccr2 register inttq0cc2 signal toq02 pin output tq0ccr3 register inttq0cc3 signal toq03 pin output d 00 d 01 d 11 d 10 d 21 d 20 d 31 d 30 d 10 d 20 d 30 d 11 d 21 d 31 d 00 d 01 <3> <1> <2> toq00 pin output (only when software trigger is used)
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 399 of 1113 sep 22, 2011 figure 8-41. timing and processing of operati ons in one-shot pul se output mode (2/2) tq0ce bit = 1 set up the registers tq0ctl0 register (tq0cks0 to tq0cks2 bits) tq0ctl1 register tq0ioc0 register tq0ioc2 register tq0ccr0 to tq0ccr3 registers be sure to set up these registers before setting the tq0ce bit to 1. counting is enabled (tq0ce bit = 1). the tq0cks0 to tq0cks2 bits can be set here. waiting for trigger start <1> starting counting tq0ce bit = 0 disables counting. stop <3> stopping counting set the tq0ccr0 to tq0ccr3 registers because the tq0ccrm register value will be transferred to the ccrm buffer register as soon as the tq0ccrm register is rewritten, it is recommended to rewrite the tq0ccrm register immediately after the inttq0ccr0 signal is generated. <2> changing the tq0ccr0 to tq0ccr3 register settings remark m = 0 to 3
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 400 of 1113 sep 22, 2011 (2) using one-shot pulse mode (a) rewriting the tq0ccrm register when rewriting the value of the tq0ccrm register to a smaller value, stop counting first and then change the set value. when changing the value of t he tq0ccr0 register from d 00 to d 01 and the value of the tq0ccrk register from d k0 to d k1 , if the registers are rewr itten under any of the following conditions, a one-shot pulse will not be output as expected. condition 1 when rewriting the tq0ccr0 register, if: d 00 > d 01 or, d 00 < 16-bit counter value < d 01 in the case of condition 1, the 16-bit counter will not be cleared and will overflow in the cycle in which the new value is being written. the counter will be clea red for the first time at the newly written value (d 01 ). condition 2 when rewriting the tq0ccrk register, if: d k0 > d k1 or, d k0 < 16-bit counter value < d k1 in the case of condition 2, the toq0k pin output cannot be inverted to the active level in the cycle in which the new value is being written. an example of what happens when condition 1 and condit ion 2 are satisfied in the same cycle is shown in figure 8-42. the 16-bit counter increments up to ffffh, overflow s, and starts increment ing again from 0000h. when the 16-bit counter value matches d k1 , the inttq0cck signal is generated and the toq0k pin output is set to the active level. subseq uently, when the 16-bit counter value matches d 01 , the inttq0cc0 signal is generated, the toq0k pin output is set to the inactive level, and the counter stops incrementing. remark m = 0 to 3 k = 1 to 3
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 401 of 1113 sep 22, 2011 figure 8-42. rewriting tq0ccrm register d k0 d k1 d 01 d 01 d 00 d k1 d 01 d k0 d k0 d k1 d 00 d 00 ffffh 16-bit counter 0000h tq0ce bit inttq0cc0 signal toq00 pin output note inttq0cck signal toq0k pin output delay (d k0 ) active level width (d 0 ? d k0 + 1) active level width (d 01 ? d k1 + 1) active level width (d 01 ? d k1 + 1) delay (d k1 ) delay (10000h + d k1 ) tq0ccr0 register (ccr0 buffer register) tq0ccrk register (ccrk buffer register) external trigger input (tiq00 pin input) note the output from the toq00 pin ca n also be used as the input to the tiq00 pin. when using the output from the toq00 pin as the input to the tiq00 pin, us e a software trigger instead of an external trigger. remark m = 0 to 3 k = 1 to 3
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 402 of 1113 sep 22, 2011 (b) timing of generating the compare ma tch interrupt request signal (inttq0cck) in the one-shot pulse output mode, the inttq0cck signal is generated when the value of the 16-bit counter matches the value of the tq0ccrk register. figure 8-43. timing of generating comp are match interrupt signal (inttq0cck) count clock 16-bit counter tq0ccrk register toq0k pin output inttq0cck signal d k d k ? 2d k ? 1d k d k + 1 d k + 2 remark k = 1 to 3
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 403 of 1113 sep 22, 2011 8.4.5 pwm output mode (tq0md 2 to tq0md0 bits = 100) in the pwm output mode, when the tq0c tl0.tq0ce bit is set to 1, tmq0 outputs a pwm waveform from the toq01 to toq03 pins. a pulse that has one cycle of the pwm waveform as hal f its cycle can also be output from the toq00 pin. remarks 1. for how to set the tiq00 and toq00 to toq03 pins, see table 8-2 pins used by tmq0 and table 4-15 settings when pins are used for alternate functions . 2. for how to enable the inttq0cc0 to inttq0cc3 interrupt signals, see chapter 21 interrupt servicing/exception processing . figure 8-44. configuration of tmq0 in pwm output mode ccr0 buffer register tq0ce bit tq0ccr0 register clear match signal inttq0cc0 signal toq03 pin inttq0cc3 signal toq00 pin transfer s r tq0ccr1 register ccr1 buffer register match signal toq01 pin inttq0cc1 signal transfer transfer s r tq0ccr3 register ccr3 buffer register match signal transfer toq02 pin inttq0cc2 signal s r tq0ccr2 register ccr2 buffer register match signal 16-bit counter count clock selection output controller (rs-ff) output controller output controller (rs-ff) output controller (rs-ff)
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 404 of 1113 sep 22, 2011 figure 8-45. basic timing of operations in pwm output mode d 0 d 1 d 2 d 3 d 1 d 2 d 3 d 0 d 0 d 1 d 2 d 3 d 0 d 1 d 2 d 3 d 0 d 1 d 2 d 3 ffffh 16-bit counter 0000h tq0ce bit tq0ccr0 register inttq0cc0 signal toq00 pin output tq0ccr1 register inttq0cc1 signal toq01 pin output active level width (d 3 ) cycle (d 0 + 1) cycle (d 0 + 1) cycle (d 0 + 1) cycle (d 0 + 1) active level width (d 3 ) active level width (d 3 ) active level width (d 3 ) active level width (d 1 ) active level width (d 1 ) active level width (d 1 ) active level width (d 1 ) active level width (d 2 ) active level width (d 2 ) active level width (d 2 ) active level width (d 2 ) tq0ccr2 register inttq0cc2 signal toq02 pin output tq0ccr3 register inttq0cc3 signal toq03 pin output
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 405 of 1113 sep 22, 2011 when the tq0ce bit is set to 1, t he 16-bit counter is cleared from ffffh to 0000h, starts incrementing, and outputs a pwm waveform from the toq0k pin. the active level width, cycle, and duty factor of the pwm waveform can be calculated as follows: active level width = (set value of tq0ccrk register) count clock cycle cycle = (set value of tq0ccr0 register + 1) count clock cycle duty factor = (set value of tq0ccrk regist er)/(set value of tq0ccr0 register + 1) the pwm waveform can be changed by rewriting the tq0ccrm register while the counter is incrementing. the newly written value is reflected when the value of the 16- bit counter matches the value of the ccr0 buffer register and the 16-bit counter is cleared to 0000h. the inttq0cc0 compare match interrupt request signal is generated when the 16-bit counter increments next time after its count value matches the value of the ccr0 buff er register, and the 16-bit counter is cleared to 0000h. the inttq0cck compare match interrupt request signal is generated when the value of the 16-bit counter matches the value of the ccrk buffer register. remark k = 1 to 3 m = 0 to 3 figure 8-46. register settings in pwm output mode (1/3) (a) tmq0 control register 0 (tq0ctl0) 0/1 0 0 0 0 tq0ctl0 these bits select the count clock note . 0: stop counting. 1: enable counting. 0/1 0/1 0/1 tq0cks2 tq0cks1 tq0cks0 tq0ce (b) tmq0 control register 1 (tq0ctl1) 0 0 0/1 0 0 tq0ctl1 100 tq0md2 tq0md1 tq0md0 tq0eee tq0est 1, 0, 0: pwm output mode 0: operate on count clock selected by using tq0cks0 to tq0cks2 bits. 1: increment based on external event count input signal. note the setting of these bits is invalid when the tq0ctl1.tq0eee bit is 1.
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 406 of 1113 sep 22, 2011 figure 8-46. register settings in pwm output mode (2/3) (c) tmq0 i/o control register 0 (tq0ioc0) toq0k pin output 16-bit counter ? when tq0olk bit is 0: toq0k pin output 16-bit counter ? when tq0olk bit is 1: 0/1 0/1 0/1 0/1 0/1 tq0ioc0 0: disable toq00 pin output. 1: enable toq00 pin output. output level when toq00 pin is disabled: 0: low level 1: high level 0: disable toq01 pin output. 1: enable toq01 pin output. active level of toq01 pin output: 0: high level 1: low level 0/1 0/1 note 0/1 note tq0oe1 tq0ol0 tq0oe0 tq0ol1 tq0oe3 tq0ol2 tq0oe2 tq0ol3 active level of toq03 pin output: 0: high level 1: low level 0: disable toq02 pin output. 1: enable toq02 pin output. active level of toq02 pin output: 0: high level 1: low level 0: disable toq03 pin output. 1: enable toq03 pin output. (d) tmq0 i/o control register 2 (tq0ioc2) 0 0 0 0 0/1 tq0ioc2 these bits select the valid edge of the external trigger input. 0/1 0 0 tq0ees0 tq0ets1 tq0ets0 tq0ees1 (e) tmq0 counter read buffer register (tq0cnt) the value of the 16-bit counter can be read by reading this register. note set this bit to 0 when not using the toq00 pin in the pwm output mode.
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 407 of 1113 sep 22, 2011 figure 8-46. register settings in pwm output mode (3/3) (f) tmq0 capture/compare register s 0 to 3 (tq0ccr0 to tq0ccr3) if the tq0ccr0 register is set to d 0 and the tq0ccrk register is set to d k , the pwm waveform is as follows: pwm waveform cycle = (d 0 + 1) count clock cycle pwm waveform active level width = d k count clock cycle remarks 1. tmq0 i/o control register 1 (tq0ioc1) and tmq0 option register 0 (tq0opt0) are not used in the pwm output mode. 2. updating tmq0 capture/compare register 2 (tq0ccr2) and tmq0 capture/compare register 3 (tq0ccr3) is enabled by writ ing to tmq0 capture/compare register 1 (tq0ccr1).
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 408 of 1113 sep 22, 2011 (1) operations in pwm output mode figure 8-47. timing and processing of op erations in pwm ou tput mode (1/2) d 10 d 10 d 10 d 20 d 30 d 00 d 11 d 21 d 01 d 31 d 11 d 21 d 00 d 31 d 20 d 30 d 00 d 21 d 00 d 31 d 11 d 21 d 00 d 31 ffffh 16-bit counter 0000h tq0ce bit tq0ccr0 register ccr0 buffer register inttq0cc0 signal toq00 pin output tq0ccr1 register ccr1 buffer register inttq0cc1 signal toq01 pin output tq0ccr2 register ccr2 buffer register inttq0cc2 signal toq02 pin output tq0ccr3 register ccr3 buffer register inttq0cc3 signal toq03 pin output d 00 d 01 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 10 d 11 d 10 d 11 d 10 d 11 d 11 d 20 d 21 d 20 d 21 d 20 d 21 d 21 d 30 d 31 d 30 d 31 d 30 d 31 d 30 d 31 <1> <2> <3> <4> <5> <6> <7> d 11 d 10 d 20
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 409 of 1113 sep 22, 2011 figure 8-47. timing and processing of op erations in pwm ou tput mode (2/2) start <1> starting counting tq0ce bit = 1 set up the registers tq0ctl0 register (tq0cks0 to tq0cks2 bits) tq0ctl1 register tq0ioc0 register tq0ioc2 register tq0ccr0 to tq0ccr3 registers be sure to set up these registers before setting the tq0ce bit to 1. after setting the tq0ccrm registers, their values are transferred to the ccrm buffer registers when the counter is cleared. after setting the tq0ccrm registers, their values are transferred to the ccrm buffer registers when the counter is cleared. after setting the tq0ccrm registers, their values are transferred to the ccrm buffer registers when the counter is cleared. disables counting. counting starts (tq0ce bit = 1). the tq0cks0 to tq0cks2 bits can be set here. after setting the tq0ccrm registers, their values are transferred to the ccrm buffer registers when the counter is cleared. after setting the tq0ccrm registers, their values are transferred to the ccrm buffer registers when the counter is cleared. <2> changing both the cycle and the duty when changing both the cycle and the duty, be sure to write to the tq0ccr0, tq0ccr2, and tq0ccr3 registers before writing to the tq0ccr1 register. <3> changing the cycle the tq0ccr1 register must be written (the same value) even when only changing the cycle setting. <4> changing the duty when changing the duty, be sure to write to the tq0ccr2 and tq0ccr3 registers before writing to the tq0ccr1 register. <5> changing the duty of the toq02 and toq03 outputs the tq0ccr1 register must be written (the same value) even when only changing the duty of the toq02 and toq03 outputs. <6> changing the duty of the toq01 output only the tq0ccr1 register has to be written when only changing the duty of the toq01 output. <7> stopping counting tq0ce bit = 0 set the tq0ccr2 and tq0ccr3 registers set the tq0ccr1 register set the tq0ccr2 and tq0ccr3 registers set the tq0ccr1 register stop set the tq0ccr1 register set the tq0ccr0 register set the tq0ccr1 register set the tq0ccr0, tq0ccr2, and tq0ccr3 registers set the tq0ccr1 register remark k = 1 to 3 m = 0 to 3
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 410 of 1113 sep 22, 2011 (2) using pwm output mode (a) changing the pwm waveform wh ile the counter is incrementing to change the pwm waveform while the counter is in crementing, write to the tq0ccr1 register after changing the waveform setting. when rewriting t he tq0ccrm register after writing to the tq0ccr1 register, do so after the inttq0cc0 signal has been detected. figure 8-48. changing pwm wavefo rm while counter is incrementing ffffh 16-bit counter 0000h tq0ce bit d 30 d 00 d 01 d 30 d 30 d 20 d 20 d 20 d 21 d 11 d 00 d 00 d 31 d 01 d 01 d 21 d 11 d 31 tq0ccr0 register ccr0 buffer register inttq0cc0 signal tq0ccr1 register ccr1 buffer register inttq0cc1 signal toq01 pin output tq0ccr2 register ccr2 buffer register inttq0cc2 signal toq02 pin output tq0ccr3 register ccr3 buffer register inttq0cc3 signal toq03 pin output toq00 pin output d 10 d 10 d 10 d 00 d 11 d 10 d 11 d 10 d 21 d 20 d 21 d 20 d 31 d 30 d 31 d 30 d 00 d 01
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 411 of 1113 sep 22, 2011 in order to transfer data from the tq0ccrm register to the ccrm buffer register, the tq0ccr1 register must be written. after data is written to the tq0ccr1 register, the valu e written to the tq0ccrm register is transferred to the ccrm buffer register in synchron ization with clearing of the 16-bit counter, and is used as the value to be compared with the 16-bit counter value. <1> to change both the cycle and active level width of the pwm waveform, first set the cycle to the tq0ccr0 register and then set the active level width to the tq0ccr2 and tq0ccr3 registers, before setting the active level width to the tq0ccr1 register. <2> to change only the cycle of the pwm waveform, first set the cycle to th e tq0ccr0 register, and then write the same value to the tq0ccr1 register (that is, the same value as the value already specified for the tq0ccr1 register). <3> to change only the active level width (duty facto r) of the pwm waveform, first set the active level width to the tq0ccr2 and tq0ccr3 registers, and then set the active level width to the tq0ccr1 register. <4> to change only the active level width (duty facto r) of the pwm waveform output from the toq01 pin, only the tq0ccr1 register has to be set. <5> to change only the active level width (duty fa ctor) of the pwm waveform output from the toq02 and toq03 pins, first set the active level width to the tq0ccr2 and tq0ccr3 registers, and then write the same value to the tq 0ccr1 register (that is, the sa me value as the value already specified for the tq0ccr1 register). caution to rewrite the tq0ccr0 to tq0ccr3 regi sters after writing the tq0ccr1 register, do so after the inttq0cc0 signal has been generated; otherwise, the value of the ccrm buffer register may b ecome undefined because the timing of transferring data from the tq0ccrm register to the ccrm buffer regi ster conflicts with writing the tq0ccrm register. remark m = 0 to 3
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 412 of 1113 sep 22, 2011 (b) outputting a 0% or 100% pwm waveform to output a 0% waveform, clear the tq0ccrk register to 0000h. figure 8-49. outputting 0% pwm waveform count clock 16-bit counter tq0ce bit tq0ccr0 register tq0ccrk register inttq0cc0 signal inttq0cck signal toq0k pin output d 0 0000h d 0 0000h d 0 0000h d 0 ? 1d 0 0000 ffff 0000 d 0 ? 1d 0 0000 0001 l remark k = 1 to 3 to output a 100% waveform, set the value of tq0ccr0 register + 1 to the tq0ccrk register. if the value of the tq0ccr0 register is ffffh, a 100% waveform cannot be output. figure 8-50. outputting 100% pwm waveform count clock 16-bit counter tq0ce bit tq0ccr0 register tq0ccrk register inttq0cc0 signal inttq0cck signal toq0k pin output d 0 d 0 + 1 d 0 d 0 + 1 d 0 d 0 + 1 d 0 ? 1d 0 0000 ffff 0000 d 0 ? 1d 0 0000 0001 remark k = 1 to 3
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 413 of 1113 sep 22, 2011 (c) timing of generating the compare ma tch interrupt request signal (inttq0cck) in the pwm output mode, the inttq0cck signal is generated when the value of the 16-bit counter matches the value of the tq0ccrk register. figure 8-51. timing of generating compare match interrupt request signal (inttq0cck) count clock 16-bit counter ccrk buffer register toq0k pin output inttq0cck signal d k d k ? 2d k ? 1d k d k + 1 d k + 2 remark k = 1 to 3
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 414 of 1113 sep 22, 2011 8.4.6 free-running timer mode (t q0md2 to tq0md0 bits = 101) in the free-running timer mode, tmq0 starts incrementing w hen the tq0ctl0.tq0ce bit is set to 1. at this time, the tq0ccrm register can be used as a compare register or a capture register, according to the setting of the tq0opt0.tq0ccs0 and tq 0opt0.tq0ccs1 bits. remarks 1. for how to set the tiq0m and toq0m pins, see table 8-2 pins used by tmq0 and table 4-15 settings when pins are used for alternate functions . 2. for how to enable the inttq0ccm interrupt signal, see chapter 21 interrupt servicing/ exception processing . 3. m = 0 to 3
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 415 of 1113 sep 22, 2011 figure 8-52. configuration of tmq0 in free-running timer mode toq03 note 2 pin output toq0 note 2 pin output toq01 note 2 pin output toq00 note 1 pin output inttq0ov signal tq0ccs0, tq0ccs1 bits (capture/compare selection) inttq0cc3 signal inttq0cc2 signal inttq0cc1 signal inttq0cc0 signal tiq03 note 2 pin (capture trigger input) tq0ccr3 register (capture) tiq00 note 1 pin (external event count input/ capture trigger input) internal count clock tq0ce bit tiq01 note 2 pin (capture trigger input) tiq02 note 2 pin (capture trigger input) tq0ccr0 register (capture) tq0ccr1 register (capture) tq0ccr2 register (capture) tq0ccr3 register (compare) tq0ccr2 register (compare) tq0ccr1 register (compare) 0 1 0 1 0 1 0 1 16-bit counter tq0ccr0 register (compare) output controller output controller output controller output controller count clock selection edge detector edge detector edge detector edge detector edge detector notes 1. the external event count input/capture trigger i nput pin (tiq00) can also be used as the timer output pin (toq00); however, only one of these functions can be used at a time. 2. the capture trigger input pin (tiq0k) can al so be used as the timer output pin (toq0k); however, only one of these functions ca n be used at a time. (k = 1 to 3.)
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 416 of 1113 sep 22, 2011 ? compare operation when the tq0ce bit is set to 1, tmq0 starts incrementi ng, and the output signals of the toq00 to toq03 pins are inverted. when the value of t he 16-bit counter later matches the se t value of the tq0ccrm register, a compare match interrupt request signal (inttq0ccm) is generated, and the output signal of the toq0m pin is inverted. the 16-bit counter continues incrementing in synchronizati on with the count clock. once the counter reaches ffffh, it generates an overflow interrupt request signal (i nttq0ov) at the next cl ock, is cleared to 0000h, and continues incrementing. at this ti me, the overflow flag (the tq0opt0.tq0ovf bit) is also set to 1. the overflow flag must be cleared to 0 by executing a clr1 software instruction. the tq0ccrm register can be rewritten wh ile the counter is incrementing. if it is rewritten, the new value is immediately applied, and compar ed with the count value. remark m = 0 to 3 figure 8-53. basic timing of operations in free-running timer mode (compare function) d 10 d 20 d 30 d 00 d 20 d 31 d 31 d 30 d 00 d 11 d 11 d 21 d 01 d 11 d 21 d 01 cleared to 0 by clr1 instruction cleared to 0 by clr1 instruction cleared to 0 by clr1 instruction ffffh 16-bit counter 0000h toq01 pin output tq0ccr2 register inttq0cc2 signal toq02 pin output tq0ccr3 register inttq0cc3 signal toq03 pin output inttq0ov signal tq0ovf bit toq00 pin output tq0ccr1 register inttq0cc1 signal tq0ce bit tq0ccr0 register inttq0cc0 signal d 00 d 01 d 11 d 10 d 21 d 20 d 31 d 30
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 417 of 1113 sep 22, 2011 ? capture operation when the tq0ce bit is set to 1, the 16-bit counter starts incrementing. when it is detected that a valid edge as been input to the tiq0m pin, t he value of the 16-bit counter is st ored in the tq0ccrm register, and a capture interrupt request signal (inttq0ccm) is generated. the 16-bit counter continues incrementing in synchroniza tion with the count clock. when the counter reaches ffffh, it generates an overflow interrupt request signal (i nttq0ov) at the next cl ock, is cleared to 0000h, and continues incrementing. at this ti me, the overflow flag (the tq0opt0.tq0ovf bit) is also set to 1. the overflow flag must be cleared to 0 by executing a clr1 software instruction. remark m = 0 to 3 figure 8-54. basic timing of operations in free-running timer mode (capture function) d 20 d 00 d 30 d 10 d 11 d 21 d 31 d 12 d 01 d 02 d 22 d 32 d 03 d 13 d 33 d 23 0000 d 00 d 01 d 02 d 03 0000 d 10 d 11 d 12 d 13 0000 d 20 d 21 d 23 d 22 0000 d 30 d 31 d 32 d 33 cleared to 0 by clr1 instruction cleared to 0 by clr1 instruction cleared to 0 by clr1 instruction ffffh 16-bit counter 0000h tiq02 pin input tq0ccr2 register inttq0cc2 signal tiq03 pin input tq0ccr3 register inttq0cc3 signal inttq0ov signal tq0ovf bit tiq01 pin input tq0ccr1 register inttq0cc1 signal tq0ce bit tiq00 pin input tq0ccr0 register inttq0cc0 signal remark the valid edge is the rising edge.
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 418 of 1113 sep 22, 2011 figure 8-55. register settings in free-running timer mode (1/3) (a) tmq0 control register 0 (tq0ctl0) 0/1 0 0 0 0 tq0ctl0 these bits select the count clock note . 0: stop counting. 1: enable counting. 0/1 0/1 0/1 tq0cks2 tq0cks1 tq0cks0 tq0ce note the setting of these bits is invalid when the tq0ctl1.tq0eee bit is 1. (b) tmq0 control register 1 (tq0ctl1) 0 0 0/1 note 00 tq0ctl1 101 tq0md2 tq0md1 tq0md0 tq0eee tq0est 1, 0, 1: free-running timer mode 0: operate on count clock selected by using tq0cks0 to tq0cks2 bits. 1: increment based on external event count input signal. note the tiq00 pin cannot be used for capture operati ons when the tq0ctl1.tq0eee bit is 1.
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 419 of 1113 sep 22, 2011 figure 8-55. register settings in free-running timer mode (2/3) (c) tmq0 i/o control register 0 (tq0ioc0) 0/1 note 0/1 note 0/1 note 0/1 note 0/1 note tq0ioc0 0: disable toq00 pin output. 1: enable toq00 pin output. 0: disable toq01 pin output. 1: enable toq01 pin output. output level when toq01 pin is disabled: 0: low level 1: high level 0/1 note 0/1 note 0/1 note tq0oe1 tq0ol0 tq0oe0 tq0ol1 tq0oe3 tq0ol2 tq0oe2 tq0ol3 output level when toq03 pin is disabled: 0: low level 1: high level 0: disable toq02 pin output. 1: enable toq02 pin output. output level when toq02 pin is disabled: 0: low level 1: high level 0: disable toq03 pin output. 1: enable toq03 pin output. output level when toq00 pin is disabled: 0: low level 1: high level note the toq0m pin cannot be used when the tiq0m pin is being used. remark m = 0 to 3 (d) tmq0 i/o control register 1 (tq0ioc1) 0/1 0/1 0/1 0/1 0/1 tq0ioc1 these bits select the valid edge of the tiq00 pin input. these bits select the valid edge of the tiq01 pin input. 0/1 0/1 0/1 tq0is2 tq0is1 tq0is0 tq0is3 tq0is6 tq0is5 tq0is4 tq0is7 these bits select the valid edge of the tiq02 pin input. these bits select the valid edge of the tiq03 pin input.
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 420 of 1113 sep 22, 2011 figure 8-55. register settings in free-running timer mode (3/3) (e) tmq0 i/o control register 2 (tq0ioc2) 0 0 0 0 0/1 tq0ioc2 these bits select the valid edge of the external event count input. 0/1 0 0 tq0ees0 tq0ets1 tq0ets0 tq0ees1 (f) tmq0 option register 0 (tq0opt0) 0/1 0/1 0/1 0/1 0 tq0opt0 overflow flag specifies whether tq0ccr0 register is used for capture or compare. specifies whether tq0ccr1 register is used for capture or compare. 0 0 0/1 tq0ccs0 tq0ovf tq0ccs1 tq0ccs2 tq0ccs3 specifies whether tq0ccr2 register is used for capture or compare. specifies whether tq0ccr3 register is used for capture or compare. (g) tmq0 counter read buffer register (tq0cnt) the value of the 16-bit counter can be read by reading this register. (h) tmq0 capture/compare regist ers 0 to 3 (tq0ccr0 to tq0ccr3) these registers function as captur e registers or compare registers according to the setting of the tq0opt0.tq0ccsm bit. when the registers function as captur e registers, they store the value of the 16-bit counter when it is detected that a valid edge has been input to the t iq0m pin, after which the inttq0ccm signal is generated. when the registers function as compare register s and when the tq0ccrm register is set to d m , the inttq0ccm signal is generated t he when the counter reaches (d m + 1), and the output signal of the toq0m pin is inverted. remark m = 0 to 3
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 421 of 1113 sep 22, 2011 (1) operations in fr ee-running timer mode the following two operations occur in the free-running timer mode: ? capture operations ? compare operations (a) using a capture/compare register as a compare register figure 8-56. timing and processing of operations in free-running timer mode (compare function) (1/2) d 10 d 20 d 30 d 00 d 10 d 20 d 30 d 00 d 11 d 31 d 01 d 21 d 21 d 11 d 11 d 31 d 01 ffffh 16-bit counter 0000h tq0ce bit inttq0cc0 signal toq00 pin output inttq0cc1 signal toq01 pin output inttq0cc2 signal toq02 pin output inttq0cc3 signal toq03 pin output inttq0ov signal tq0ovf bit d 00 d 10 d 20 d 30 d 01 d 11 d 21 d 31 cleared to 0 by clr1 instruction cleared to 0 by clr1 instruction cleared to 0 by clr1 instruction <3> <1> <2> <2> <2> tq0ccr0 register (ccr0 buffer register) tq0ccr1 register (ccr1 buffer register) tq0ccr2 register (ccr2 buffer register) tq0ccr3 register (ccr3 buffer register) value changed value changed value changed value changed
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 422 of 1113 sep 22, 2011 figure 8-56. timing and processing of operations in free-running timer mode (compare function) (2/2) tq0ce bit = 1 read tq0opt0 register (check overflow flag) set up the registers tq0ctl0 register (tq0cks0 to tq0cks2 bits) tq0ctl1 register tq0ioc0 register tq0ioc2 register tq0opt0 register tq0ccr0 to tq0ccr3 registers be sure to set up these registers before setting the tq0ce bit to 1. counting is enabled (tq0ce bit = 1). the tq0cks0 to tq0cks2 bits can be set here. start execute instruction to clear tq0ovf bit (clr1 tq0ovf) <1> starting counting <2> clearing overflow flag tq0ce bit = 0 when counting is disabled (tq0ce bit = 0), the counter is reset and counting stops. stop <3> stopping counting tq0ovf bit = 1 no yes
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 423 of 1113 sep 22, 2011 (b) using a capture/compare register as a capture register figure 8-57. timing and processing of operations in free-running timer mode (capture function) (1/2) d 20 d 00 d 30 d 10 d 11 d 21 d 31 d 12 d 01 d 02 d 22 d 32 d 03 d 13 d 33 d 23 0000 d 00 d 01 d 02 d 03 0000 0000 0000 0000 0000 d 10 d 11 d 12 d 13 0000 d 20 d 21 d 23 d 22 0000 d 30 d 31 d 32 d 33 cleared to 0 by clr1 instruction cleared to 0 by clr1 instruction cleared to 0 by clr1 instruction <3> <1> <2> <2> <2> ffffh 16-bit counter 0000h tq0ce bit tiq02 pin input inttq0cc2 signal tiq03 pin input inttq0cc3 signal inttq0ov signal tq0ovf bit tiq01 pin input inttq0cc1 signal tiq00 pin input inttq0cc0 signal tq0ccr0 register (ccr0 buffer register) tq0ccr1 register (ccr1 buffer register) tq0ccr2 register (ccr2 buffer register) tq0ccr3 register (ccr3 buffer register)
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 424 of 1113 sep 22, 2011 figure 8-57. timing and processing of operations in free-running timer mode (capture function) (2/2) tq0ce bit = 1 read tq0opt0 register (check overflow flag) set up the registers tq0ctl0 register (tq0cks0 to tq0cks2 bits) tq0ctl1 register tq0ioc1 register tq0opt0 register be sure to set up these registers before setting the tq0ce bit to 1. counting is enabled (tq0ce bit = 1). the tq0cks0 to tq0cks2 bits can be set here. start execute instruction to clear tq0ovf bit (clr1 tq0ovf) <1> starting counting <2> clearing overflow flag tq0ce bit = 0 when counting is disabled (tq0ce bit = 0), the counter is reset and counting stops. stop <3> stopping counting tq0ovf bit = 1 no yes
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 425 of 1113 sep 22, 2011 (2) using free-running timer mode (a) interval operation using the tq0 ccrm register as a compare register when tmq0 is used as an interval timer with the tq 0ccrm register used as a compare register, the comparison value at which the next interrupt r equest signal is generated each time the inttq0ccm signal has been detected must be set by software. figure 8-58. interval operation of tmq0 in free-running timer mode d 00 d 10 d 20 d 01 d 30 d 12 d 03 d 22 d 31 d 21 d 23 d 02 d 13 ffffh 16-bit counter 0000h tq0ce bit inttq0cc0 signal toq00 pin output inttq0cc1 signal toq01 pin output inttq0cc2 signal toq02 pin output inttq0cc3 signal toq03 pin output interval period (d 00 + 1) interval period (10000h + d 02 ? d 01 ) interval period (d 01 ? d 00 ) interval period (d 03 ? d 02 ) interval period (d 04 ? d 03 ) d 00 d 01 d 02 d 03 d 04 d 05 interval period (d 10 + 1) interval period (10000h + d 12 ? d 11 ) interval period (d 11 ? d 10 ) interval period (d 13 ? d 12 ) d 10 d 11 d 12 d 13 d 14 interval period (d 20 + 1) interval period (10000h + d 21 ? d 20 ) interval period (10000h + d 23 ? d 22 ) interval period (d 22 ? d 21 ) interval period (d 30 + 1) interval period (10000h + d 31 ? d 30 ) d 20 d 21 d 22 d 23 d 31 d 30 d 32 d 04 d 11 tq0ccr0 register (ccr0 buffer register) tq0ccr1 register (ccr1 buffer register) tq0ccr2 register (ccr2 buffer register) tq0ccr3 register (ccr3 buffer register)
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 426 of 1113 sep 22, 2011 when performing an interval operation in the free-running timer mode, four intervals can be set for one channel. to perform the interval operation, the value of the corresponding tq 0ccrm register must be set again in the interrupt servicing that is executed when the inttq0ccm signal is detected. the value to be set in this case can be calculated by the following expression, where ?d m ? is the interval period. compare register default value: d m ? 1 value set to compare register second and subsequent time: previous set value + d m (if the calculation result is greate r than ffffh, subtract 10000h from t he result and set the register to this value.) remark m = 0 to 3
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 427 of 1113 sep 22, 2011 (b) pulse width measurement using the tq 0ccrm register as a capture register when pulse width measurement is performed with the tq0ccrm register used as a capture register, each time the inttq0ccm signal has been detected, t he capture register must be read and the interval must be calculated by software. figure 8-59. pulse width measurement by tmq0 in free-running timer mode d 20 d 00 d 30 d 10 d 11 d 21 d 31 d 12 d 01 d 02 d 32 d 13 d 03 d 22 d 33 d 23 0000 pulse interval (10000h + d 01 ? d 00 ) pulse interval (10000h + d 02 ? d 01 ) pulse interval (10000h + d 03 ? d 02 ) d 00 d 01 d 02 d 03 pulse interval (d 00 + 1) 0000 pulse interval (10000h + d 11 ? d 10 ) pulse interval (10000h + d 12 ? d 11 ) pulse interval (d 13 ? d 12 ) d 10 d 11 d 12 d 13 pulse interval (d 10 + 1) 0000 pulse interval (10000h + d 21 ? d 20 ) pulse interval (20000h + d 22 ? d 21 ) pulse interval (d 23 ? d 22 ) d 20 d 21 d 23 d 22 pulse interval (d 20 + 1) 0000 pulse interval (10000h + d 31 ? d 30 ) pulse interval (10000h + d 32 ? d 31 ) pulse interval (10000h + d 33 ? d 32 ) d 30 d 31 d 32 d 33 pulse interval (d 30 + 1) cleared to 0 by clr1 instruction cleared to 0 by clr1 instruction cleared to 0 by clr1 instruction ffffh 16-bit counter 0000h tq0ce bit tiq00 pin input inttq0cc0 signal tiq02 pin input inttq0cc2 signal tiq03 pin input inttq0cc3 signal inttq0ov signal tq0ovf bit tiq01 pin input inttq0cc1 signal tq0ccr0 register (ccr0 buffer register) tq0ccr1 register (ccr1 buffer register) tq0ccr2 register (ccr2 buffer register) tq0ccr3 register (ccr3 buffer register)
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 428 of 1113 sep 22, 2011 four pulse widths can be measured in the free-running timer mode. when measuring a pulse width, the pulse width can be calculated by reading the value of the tq0ccrm register in synchronization with the inttq0ccm signa l, and calculating the di fference between that value and the previously read value. remark m = 0 to 3
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 429 of 1113 sep 22, 2011 (c) processing an overflow when two or more capture registers are used care must be exercised in processing the overflow flag when two or more capture registers are used. first, an example of incorrect processing is shown below. figure 8-60. example of incorrect processing wh en two or more capture registers are used ffffh 16-bit counter 0000h tq0ce bit tiq00 pin input tq0ccr0 register tiq01 pin input tq0ccr1 register inttq0ov signal tq0ovf bit d 00 d 01 d 10 d 11 d 10 <1> <2> <3> <4> d 00 d 11 d 01 the following problem may occur when two pulse widt hs are measured in the free-running timer mode. <1> the tq0ccr0 register is read (the defaul t value of the tiq00 pin input is set). <2> the tq0ccr1 register is read (the defaul t value of the tiq01 pin input is set). <3> the tq0ccr0 register is read. the tq0ovf bit is read. if the tq0o vf bit is 1, it is cleared to 0. because the tq0ovf bit is 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <4> the tq0ccr1 register is read. the tq0ovf bit is read. because the tq 0ovf bit was cleared in <3>, 0 is read. because the tq0ovf bit is 0, t he pulse width can be calculated by (d 11 ? d 10 ) (incorrect). when two or more capture registers are used, and if the tq0ovf bit is cleared to 0 by one capture register, another capture register may not obtain the correct pulse width. this problem can be resolved by using software, as shown in the example below.
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 430 of 1113 sep 22, 2011 figure 8-61. example of resolving problem when tw o or more capture registers are used by using overflow interrupt ffffh 16-bit counter 0000h tq0ce bit inttq0ov signal tq0ovf bit tq0ovf0 flag note tiq00 pin input tq0ccr0 register tq0ovf1 flag note tiq01 pin input tq0ccr1 register d 10 d 11 d 00 d 01 d 10 <1> <2> <5> <6> <3> <4> d 00 d 11 d 01 note the tq0ovf0 and tq0ovf1 flags are set on the internal ram by software. <1> the tq0ccr0 register is read (the defaul t value of the tiq00 pin input is set). <2> the tq0ccr1 register is read (the defaul t value of the tiq01 pin input is set). <3> an overflow occurs. the tq0ovf0 and tq0ovf 1 flags are set to 1 in the overflow interrupt servicing, and the tq0ovf bit is cleared to 0. <4> the tq0ccr0 register is read. the tq0ovf0 flag is read. the tq0ovf0 flag is 1, so it is cleared to 0. because the tq0ovf0 flag was 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <5> the tq0ccr1 register is read. the tq0ovf1 flag is read. the tq0ovf1 flag is 1, so it is cleared to 0 (the tq0ovf0 flag was cleared in <4>; the tq0ovf1 flag remained 1). because the tq0ovf1 flag is 1, the pulse width can be calculated by (10000h + d 11 ? d 10 ) (correct). <6> same as <3>.
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 431 of 1113 sep 22, 2011 figure 8-62. example of resolving problem when two or more capture registers are used without using overflow interrupt ffffh 16-bit counter 0000h tq0ce bit inttq0ov signal tq0ovf bit tq0ovf0 flag note tiq00 pin input tq0ccr0 register tq0ovf1 flag note tiq01 pin input tq0ccr1 register d 10 d 11 d 00 d 01 d 10 <1> <2> <5> <6> <3> <4> d 00 d 11 d 01 note the tq0ovf0 and tq0ovf1 flags are set on the internal ram by software. <1> the tq0ccr0 register is read (the defaul t value of the tiq00 pin input is set). <2> the tq0ccr1 register is read (the defaul t value of the tiq01 pin input is set). <3> an overflow occurs. there is no software processing. <4> the tq0ccr0 register is read. the tq0ovf bit is read. the tq0ovf bit is 1, so only the tq0ovf1 flag is set to 1; the tq0ovf bit is cleared to 0. because the tq0ovf bit is 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <5> the tq0ccr1 register is read. the tq0ovf bit is read. the tq0ovf bi t was cleared to 0 in <4>, so 0 is read. the tq0ovf1 flag is read. the tq0ovf1 fl ag is 1, so it is cleared to 0. because the tq0ovf1 flag was 1, the pul se width can be calculated by (10000h + d 11 ? d 10 ) (correct). <6> same as <3>.
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 432 of 1113 sep 22, 2011 (d) processing of overflow if cap ture trigger interval is long if the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an overflow may occur more than once between the first capture trigger and the next. first, an example of incorrect processing is shown below. figure 8-63. example of incorrect processing when ca pture trigger interval is long (when using tiq0m) ffffh 16-bit counter 0000h tq0ce bit tiq0m pin input tq0ccrm register inttq0ov signal tq0ovf bit d m0 d m1 d m0 d m1 <1> <2> <3> <4> 1 cycle of 16-bit counter pulse width the following problem may occur when a long pulse width is measured in the free-running timer mode. <1> the tq0ccrm register is read (the defaul t value of the tiq0m pin input is set). <2> an overflow occurs. there is no software processing. <3> an overflow occurs a second time. there is no software processing. <4> the tq0ccrm register is read. the tq0ovf bit is read. the tq0ovf bit is 1, so it is cleared to 0. because the tq0ovf bit was 1, the pulse width can be calculated by (10000h + d m1 ? d m0 ) (incorrect). actually, the pulse width should be (20000h + d m1 ? d m0 ) because an overflow occurred twice. remark m = 0 to 3 if an overflow occurs twice or more when the capture tr igger interval is long, the correct pulse width may not be obtained. if the capture trigger interval is long, slow the count clock to lengthen one cycle of the 16-bit counter, or use software to resolve the problem. an example of how to use software to resolve the problem is shown below.
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 433 of 1113 sep 22, 2011 figure 8-64. example of using software processing to resolve problem when capture trigger interval is long (when using tiq0m) ffffh 16-bit counter 0000h tq0ce bit tiq0m pin input tq0ccrm register inttq0ov signal tq0ovf bit overflow counter note d m0 d m1 1h 0h 2h 0h d m0 d m1 <1> <2> <3> <4> 1 cycle of 16-bit counter pulse width note the overflow counter is set on the internal ram by software. <1> the tq0ccrm register is read (the defaul t value of the tiq0m pin input is set). <2> an overflow occurs. the overflow counter is incremented and the tq0ovf bit is cleared to 0 in the overflow interrupt servicing. <3> an overflow occurs a second time. the overfl ow counter is incremented and the tq0ovf bit is cleared to 0 in the overflow interrupt servicing. <4> the tq0ccrm register is read. the overflow counter is read. if the overflow counter is n, the pulse width can be calculated by (n 10000h + d m1 ? d m0 ). in this example, because an overflow occurred t wice, the pulse width is calculated as (20000h + d m1 ? d m0 ). the overflow counter is cleared to 0h. remark m = 0 to 3 (e) clearing the overflow flag (tq0ovf) the overflow flag (tq0ovf) can be cleared to 0 by readi ng the tq0ovf bit and, if its value is 1, either clearing the bit to 0 by using the clr1 instruction or by writing 8-bit data (with bit 0 as ?0?) to the tq0opt0 register.
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 434 of 1113 sep 22, 2011 8.4.7 pulse width measurement mode (tq0md2 to tq0md0 bits = 110) in the pulse width measurement mode, tmq0 starts incr ementing when the tq0ctl0.tq0ce bit is set to 1. each time it is detected that a valid edge has been input to the tiq0m pin, the value of th e 16-bit counter is stored in the tq0ccrm register, and the 16-bi t counter is cleared to 0000h. the interval of the valid edge can be measured by r eading the tq0ccrm register after a capture interrupt request signal (inttq0ccm) occurs. select one of the tiq00 to tiq03 pins as the capture trigger input pin. specify ?no edge detected? by using the tq0ioc1 register for the unused pins. remarks 1. for how to set the tiq0m pin, see table 8-2 pins used by tmq0 and table 4-15 settings when pins are used for alternate functions . 2. for how to enable the inttq0ccm interrupt signal, see chapter 21 interrupt servicing/ exception processing . 3. m = 0 to 3 k = 1 to 3 figure 8-65. configuration of tmq0 in pulse width measurement mode inttq0ov signal inttq0cc0 signal inttq0cc1 signal inttq0cc2 signal inttq0cc3 signal tiq03 pin (capture trigger input) tq0ccr3 register (capture) tiq00 pin (capture trigger input) count clock selection tq0ce bit edge detector tiq01 pin (capture trigger input) edge detector tiq02 pin (capture trigger input) edge detector tq0ccr0 register (capture) tq0ccr1 register (capture) tq0ccr2 register (capture) edge detector 16-bit counter clear
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 435 of 1113 sep 22, 2011 figure 8-66. basic timing of operati ons in pulse width measurement mode ffffh 16-bit counter 0000h tq0ce bit tiq0m pin input tq0ccrm register inttq0ccm signal inttq0ov signal tq0ovf bit d 0 0000h d 1 d 2 d 3 cleared to 0 by clr1 instruction remark m = 0 to 3 when the tq0ce bit is set to 1, the 16-bit counter starts incrementing. when it is subsequently det ected that a valid edge has been input to the tiq0m pi n, the value of the 16-bit counter is stored in the tq0ccrm register, the 16-bit counter is cleared to 0000h, and a capture interrupt request signal (inttq0ccm) is generated. the pulse width is calculated as follows. pulse width = captured value count clock cycle if a valid edge has not been input to t he tiq0m pin by the time the 16-bit counter has incremented up to ffffh, an overflow interrupt request signal (inttq0ov) is generated at the next count clock, an d the counter is cleared to 0000h and continues incrementing. at this time, the overfl ow flag (tq0opt0.tq0ovf bit) is also set to 1. clear the overflow flag to 0 by executing the clr1 software instruction. if the overflow flag is set to 1, the pu lse width can be calculated as follows. pulse width = (10000h number of times the tq0ovf bit was set (1) + captured value) count clock cycle remark m = 0 to 3
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 436 of 1113 sep 22, 2011 figure 8-67. register settings in pulse width measurement mode (1/2) (a) tmq0 control register 0 (tq0ctl0) 0/1 0 0 0 0 tq0ctl0 these bits select the count clock. 0: stop counting. 1: enable counting. 0/1 0/1 0/1 tq0cks2 tq0cks1 tq0cks0 tq0ce (b) tmq0 control register 1 (tq0ctl1) 00000 tq0ctl1 110 tq0md2 tq0md1 tq0md0 tq0eee tq0est 1, 1, 0: pulse width measurement mode (c) tmq0 i/o control register 1 (tq0ioc1) 0/1 0/1 0/1 0/1 0/1 tq0ioc1 these bits select the valid edge of the tiq00 pin input. these bits select the valid edge of the tiq01 pin input. 0/1 0/1 0/1 tq0is2 tq0is1 tq0is0 tq0is3 tq0is6 tq0is5 tq0is4 tq0is7 these bits select the valid edge of the tiq02 pin input. these bits select the valid edge of the tiq03 pin input. (d) tmq0 option register 0 (tq0opt0) 00000 tq0opt0 overflow flag 0 0 0/1 tq0ovf tq0ccs1 tq0ccs2 tq0ccs3 tq0ccs0
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 437 of 1113 sep 22, 2011 figure 8-67. register settings in pulse width measurement mode (2/2) (e) tmq0 counter read buffer register (tq0cnt) the value of the 16-bit counter can be read by reading this register. (f) tmq0 capture/compare register s 0 to 3 (tq0ccr0 to tq0ccr3) these registers store the 16-bit c ounter value upon detection of the i nput of a valid edge to the tiq0m pin. remark tmq0 i/o control register 0 (tq0ioc0) and tm q0 i/o control register 2 (tq0ioc2) are not used in the pulse width measurement mode.
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 438 of 1113 sep 22, 2011 (1) operations in pulse width measurement mode figure 8-68. timing and processing of operat ions in pulse width measurement mode <1> <2> set up the tq0ctl0 register (tq0ce bit = 1) tq0ce bit = 0 set up the registers tq0ctl0 register (tq0cks0 to tq0cks2 bits) tq0ctl1 register tq0ioc1 register tq0opt0 register be sure to set up these registers before setting the tq0ce bit to 1. counting is enabled (tq0ce bit = 1). the tq0cks0 to tq0cks2 bits can be set here. when counting is disabled (tq0ce bit = 0), the counter is reset and counting stops. start stop <1> starting counting <2> stopping counting ffffh 16-bit counter 0000h tq0ce bit tiq00 pin input tq0ccr0 register inttq0cc0 signal d 0 0000h 0000h d 1 d 2
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 439 of 1113 sep 22, 2011 (2) using pulse width measurement mode (a) clearing the overflow flag (tq0ovf) the overflow flag (tq0ovf) can be cleared to 0 by readi ng the tq0ovf bit and, if its value is 1, either clearing the bit to 0 by using the clr1 instruction or by writing 8-bit data (with bit 0 as ?0?) to the tq0opt0 register. 8.4.8 timer output operations the following table shows the operations and out put levels of the toq00 to toq03 pins. table 8-8. timer output control in each mode operation mode toq00 pin toq 01 pin toq02 pin toq03 pin interval timer mode square wave output external event count mode ? external trigger pulse output mode external trigger pulse output external trigger pulse output external trigger pulse output one-shot pulse output mode one-shot pulse output one-shot pulse output one-shot pulse output pwm output mode square wave output pwm output pwm output pwm output free-running timer mode square wave output (only when compare function is used) pulse width measurement mode ? table 8-9. truth table of toq00 to toq03 pins under control of timer output control bits tq0ioc0.tq0olm bit tq0ioc0.tq0oem bit tq0ctl0.tq0ce bit level of toq0m pin 0 low-level output 0 low-level output 0 1 1 low level immediately before counting, high level after counting is started 0 high-level output 0 high-level output 1 1 1 high level immediately before counting, low level after counting is started remark m = 0 to 3
v850es/jg3-l chapter 8 16-bit timer/event counter q (tmq) r01uh0165ej0700 rev.7.00 page 440 of 1113 sep 22, 2011 8.5 cautions (1) capture operation when the capture operation is used and f xx /8, f xx /16, f xx /32, f xx /64, f xx /128, or the external event counter (tq0clt1.tq0eee bit = 1) is selected as the count clock, ffffh, not 0000h, may be captured in the tq0ccr0, tq0ccr1, tq0ccr2, and tq0ccr3 register s, or the capture operation may not be performed at all (the capture interrupt does not occur) if the capture trigger is input immediately after the tq0ce bit is set to 1. (a) free-running timer mode count clock 0000h ffffh tq0ce bit tq0ccr0 register ffffh 0001h 0000h tiq00 pin input capture trigger input 16-bit counter sampling clock (f xx ) capture trigger input (b) pulse width measurement mode 0000h ffffh ffffh 0002h 0000h count clock tq0ce bit tq0ccr0 register tiq00 pin input capture trigger input 16-bit counter sampling clock (f xx ) capture trigger input
v850es/jg3-l chapter 9 16-bit interval timer m (tmm) r01uh0165ej0700 rev.7.00 page 441 of 1113 sep 22, 2011 chapter 9 16-bit interval timer m (tmm) timer m (tmm) is a 16-bit interval timer. the v850es/jg3-l incorporates one tmm timer, tmm0. 9.1 features tmm0 is a dedicated interval timer that generates interr upt requests at a specified interval based on the count clock selected from one of eight clock sources: the main clock (f xx ), a divided main clock (f xx /2, f xx /4, f xx /64, f xx /512), the watch timer interrupt signal (intwt), the internal clock (f r /8), and the subclock (f xt ). tmm0 can only be used in the clear & start mode; it cannot be used in the free-running timer mode.
v850es/jg3-l chapter 9 16-bit interval timer m (tmm) r01uh0165ej0700 rev.7.00 page 442 of 1113 sep 22, 2011 9.2 configuration tmm0 includes the following hardware. table 9-1. configuration of tmm0 item configuration register 16-bit counter tmm0 compare register 0 (tm0cmp0) tmm0 control register 0 (tm0ctl0) figure 9-1. block diagram of tmm0 tm0ctl0 internal bus f xx f xx /2 f xx /4 f xx /64 f xx /512 intwt f r /8 f xt controller 16-bit counter match clear inttm0eq0 tm0cmp0 tm0ce tm0cks2 tm0cks1tm0cks0 selector remark f xx : main clock frequency f r : internal clock frequency f xt : subclock frequency intwt: watch timer interrupt request signal (1) 16-bit counter this counter counts the internal clock. this counter cannot be read or written. (2) tmm0 compare register 0 (tm0cmp0) this is a 16-bit compare register. (3) tmm0 control register 0 (tm0ctl0) this is an 8-bit register used to control the operation of tmm0. (4) selector the selector is used to select the count clock of t he 16-bit counter. the count clock can be selected from eight clock sources.
v850es/jg3-l chapter 9 16-bit interval timer m (tmm) r01uh0165ej0700 rev.7.00 page 443 of 1113 sep 22, 2011 9.3 registers (1) tmm0 control register (tm0ctl0) the tm0ctl0 register is an 8-bit register that controls the operation of tmm0. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. except for the tm0ce bit, the bits of the tm0ctl0 register cannot be rewri tten to different values while tmm0 is operating (bits can be rewritten only to the same value as was previously specified). tm0ce tmm0 operation disabled (16-bit counter reset asynchronously). tmm0 operation enabled. tm0ce 0 1 internal clock operation enable/disable specification tm0ctl0 0 0 0 0 tm0cks2 tm0cks1 tm0cks0 654321 after reset: 00h r/w address: fffff690h when the tm0ce bit is cleared to 0, the internal clock of tmm0 is disabled (fixed to low level) and 16-bit counter is reset asynchronously. <7> 0 f xx f xx /2 f xx /4 f xx /64 f xx /512 intwt f r /8 f xt tm0cks2 0 0 0 0 1 1 1 1 count clock selection tm0cks1 0 0 1 1 0 0 1 1 tm0cks0 0 1 0 1 0 1 0 1 cautions 1. set the tm0cks2 to tm0cks0 bi ts while tmm0 is stopped (tm0ce bit = 0). the tm0cks2 to tm0cks0 bits cannot be set at the same time as changing the value of tm0ce from 0 to 1. 2. be sure to clear bits 3 to 6 to ?0?. remark f xx : main clock frequency f r : internal oscillator clock frequency f xt : subclock frequency intwt: watch timer interrupt request signal
v850es/jg3-l chapter 9 16-bit interval timer m (tmm) r01uh0165ej0700 rev.7.00 page 444 of 1113 sep 22, 2011 (2) tmm0 compare register 0 (tm0cmp0) the tm0cmp0 register is a 16-bit compare register. this register can be read or written in 16-bit units. reset sets this register to 0000h. however, if tmm0 is reset while it is stopped, this register is set to ffffh. the same value can always be written to the tm0cmp0 register by software. the tm0cmp0 register cannot be rewritten while tmm0 is operating (tm0ctl0.tm0ce bit = 1). caution do not set the tm0cmp0 register to ffffh. tm0cmp0 12 10 8 6 4 2 after reset: 0000h r/w address: fffff694h 14 0 13 11 9 7 5 3 15 1
v850es/jg3-l chapter 9 16-bit interval timer m (tmm) r01uh0165ej0700 rev.7.00 page 445 of 1113 sep 22, 2011 9.4 operation 9.4.1 interval timer mode when the tm0ce bit is set to 1, the value of the 16-bit c ounter is cleared from ffffh to 0000h in synchronization with the count clock, and the count er starts incrementing. when the value of the 16-bit counter matc hes the value of the tm0cmp0 register , the 16-bit counter is cleared to 0000h and a compare match interrupt request signal (i nttm0eq0) is generated at the specified interval. figure 9-2. configuration of interval timer 16-bit counter tm0cmp0 register tm0ce bit count clock selection clear match signal inttm0eq0 signal figure 9-3. basic timing of op eration in interval timer mode ffffh 16-bit counter 0000h tm0ce bit tm0cmp0 register inttm0eq0 signal d d d d d interval (d + 1) interval (d + 1) interval (d + 1) interval (d + 1)
v850es/jg3-l chapter 9 16-bit interval timer m (tmm) r01uh0165ej0700 rev.7.00 page 446 of 1113 sep 22, 2011 an example of the register settings when the interv al timer mode is used is shown in the figure below. figure 9-4. register settings in interval timer mode (a) tmm0 control register 0 (tm0ctl0) 0/1 0 0 0 0 tm0ctl0 0/1 0/1 0/1 tm0cks2 tm0cks1 tm0cks0 tm0ce 0: stop counting 1: enable counting these bits select the count clock. (b) tmm0 compare register 0 (tm0cmp0) if the tm0cmp0 register is set to d, the interval is as follows: interval = (d + 1) count clock cycle (0000h tm0cmp0 register value < ffffh)
v850es/jg3-l chapter 9 16-bit interval timer m (tmm) r01uh0165ej0700 rev.7.00 page 447 of 1113 sep 22, 2011 (1) operations in interval timer mode figure 9-5. timing and processing of operations in interval timer mode ffffh 16-bit counter 0000h tm0ce bit tm0cmp0 register inttm0eq0 signal d d d d <1> <2> tm0ce bit = 1 tm0ce bit = 0 set up the registers tm0ctl0 register (tm0cks0 to tm0cks2 bits) tm0cmp0 register be sure to set up these registers before setting the tm0ce bit to 1. counting is enabled (tm0ce bit = 1). the tm0cks0 to tm0cks2 bits cannot be set here. when counting is disabled (tm0ce bit = 0), the counter is reset and counting stops. start stop <1> starting counting <2> stopping counting
v850es/jg3-l chapter 9 16-bit interval timer m (tmm) r01uh0165ej0700 rev.7.00 page 448 of 1113 sep 22, 2011 (2) using interval timer mode (a) operation when tm0cmp0 register is set to 0000h when the tm0cmp0 register is set to 0000h, the in ttm0eq0 signal is generated for each count clock cycle. the value of the 16-bit counter is always 0000h. figure 9-6. operation of interval time r when tm0cmp0 register is set to 0000h count clock 16-bit counter tm0ce bit tm0cmp0 register inttm0eq0 signal 0000h interval time count clock cycle ffffh 0000h 0000h 0000h 0000h interval time count clock cycle (b) operation when tm0cmp0 register is set to n when the tm0cmp0 register is set to n , the 16-bit counter increments up to n and is reset to 0000h in synchronization with the next increment timing . the inttm0eq0 signal is then generated. figure 9-7. operation of interv al timer when tm0cmp0 register is set to other than 0000h, ffffh n n ffffh 16-bit counter 0000h tm0ce bit tm0cmp0 register inttm0eq0 signal interval time (n + 1) count clock cycle interval time (n + 1) count clock cycle interval time (n + 1) count clock cycle remark 0000h < n < ffffh
v850es/jg3-l chapter 9 16-bit interval timer m (tmm) r01uh0165ej0700 rev.7.00 page 449 of 1113 sep 22, 2011 9.4.2 cautions (1) it takes the 16-bit counter up to the following time to start counting after the tm0ctl0.tm0ce bit is set to 1, depending on the count clock selected. selected count clock maximum time before counting starts f xx 2/f xx f xx /2 3/f xx f xx /4 6/f xx f xx /64 128/f xx f xx /512 1024/f xx intwt second rising edge of intwt signal f r /8 16/f r f xt 2/f xt (2) rewriting the tm0cmp0 and tm0ctl0 regist ers is prohibited while tmm0 is operating. if these registers are rewritten while the tmm0 is operating (tm0ce bit = 1) , the operation cannot be guaranteed. if these registers are rewritten by mistak e, clear the tm0ctl0.tm0ce bit to 0, and set the registers again.
v850es/jg3-l chapter 10 watch timer r01uh0165ej0700 rev.7.00 page 450 of 1113 sep 22, 2011 chapter 10 watch timer 10.1 functions the watch timer has the following functions. ? watch timer: an interrupt request signal (intwt) is generated at intervals of 0.5 or 0.25 seconds by using the main clock or subclock. ? interval timer: an interrupt request sig nal (intwti) is generated at set intervals. the watch timer and interval timer functions can be used at the same time. caution intwti interrupt of the watch timer and intr tc2 interrupt of rtc, and intwt interrupt of the watch timer and intrtc0 interrupt of rtc are alternate interrupt signals, and therefore cannot be used simultaneously. ( pd70f3792, 70f3793, 70f3841, 70f3842 only.)
v850es/jg3-l chapter 10 watch timer r01uh0165ej0700 rev.7.00 page 451 of 1113 sep 22, 2011 10.2 configuration the block diagram of the watch timer is shown below. figure 10-1. block diagram of watch timer internal bus watch timer operation mode register (wtm) f brg f w /2 4 f w /2 5 f w /2 6 f w /2 7 f w /2 8 f w /2 10 f w /2 11 f w /2 9 f xt 11-bit prescaler clear clear intwt intwti wtm0 wtm1 wtm2 wtm3 wtm4 wtm5 wtm6 wtm7 5-bit counter f w 3 f x f x /8 f x /4 f x /2 f x bgcs00 bgcs01 bgce0 3-bit prescaler 8-bit counter clear match f bgcs prsm0 register prscm0 register 2 internal bus clock control selector selector selector selector selector 1/2 remark f x : main clock oscillation frequency f bgcs : watch timer source clock frequency f brg : watch timer count clock frequency f xt : subclock frequency f w : watch timer clock frequency intwt: watch timer interrupt request signal intwti: interval timer interrupt request signal
v850es/jg3-l chapter 10 watch timer r01uh0165ej0700 rev.7.00 page 452 of 1113 sep 22, 2011 (1) clock control this block controls supplying and stopping the operating clock (f x ) when the watch timer operates on the main clock. (2) 3-bit prescaler this prescaler divides f x to generate f x /2, f x /4, or f x /8. (3) 8-bit counter this counter counts the source clock (f bgcs ). (4) 11-bit prescaler this prescaler divides f w to generate a clock of f w /2 4 to f w /2 11 . (5) 5-bit counter this counter counts f w or f w /2 9 , and generates a watch timer interrupt request signal at intervals of 2 4 /f w , 2 5 /f w , 2 12 /f w , or 2 14 /f w . (6) selector the watch timer has the following five selectors. ? selector that selects one of f x , f x /2, f x /4, or f x /8 as the source clock of the watch timer ? selector that selects the main clock (f x ) or subclock (f xt ) as the clock of the watch timer ? selector that selects f w or f w /2 9 as the count clock frequency of the 5-bit counter ? selector that selects 2 4 /f w , 2 13 /f w , 2 5 /f w , or 2 14 /f w as the intwt signal generation time interval ? selector that selects 2 4 /f w to 2 11 /f w as the interval timer interrupt r equest signal (intwti) generation time interval (7) prscm0 register this is an 8-bit compare register that sets the interval time. (8) prsm0 register this register controls clock supply to the watch timer. (9) wtm register this is an 8-bit register that contro ls the operation of the wa tch timer/interval timer, and sets the interrupt request signal generation interval.
v850es/jg3-l chapter 10 watch timer r01uh0165ej0700 rev.7.00 page 453 of 1113 sep 22, 2011 10.3 control registers the following registers are provided for the watch timer. ? prescaler mode register 0 (prsm0) ? prescaler compare register 0 (prscm0) ? watch timer operation mode register (wtm) (1) prescaler mode register 0 (prsm0) the prsm0 register controls the generat ion of the watch timer count clock. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 prsm0 0 0 bgce0 0 0 bgcs01 bgcs00 disabled enabled bgce0 0 1 main clock operation enable f x f x /2 f x /4 f x /8 5 mhz 200 ns 400 ns 800 ns 1.6 s 4 mhz 250 ns 500 ns 1 s 2 s bgcs01 0 0 1 1 bgcs00 0 1 0 1 selection of watch timer source clock (f bgcs ) after reset: 00h r/w address: fffff8b0h < > cautions 1. do not change the values of the bgcs00 and bgcs01 bits during watch timer operation. 2. set the prsm0 register befo re setting the bgce0 bit to 1. 3. set the prsm0 and prscm0 registers accordi ng to the main clock fr equency that is used so as to obtain an f brg frequency of 32.768 khz.
v850es/jg3-l chapter 10 watch timer r01uh0165ej0700 rev.7.00 page 454 of 1113 sep 22, 2011 (2) prescaler compare register 0 (prscm0) the prscm0 register is an 8-bit compare register. this register can be read or written in 8-bit units. reset sets this register to 00h. prscm07 prscm0 prscm06 prscm05 prscm04 prscm03 prscm02 prscm01 prscm00 after reset: 00h r/w address: fffff8b1h cautions 1. do not rewrite the prscm0 register during watc h timer operation. 2. set the prscm0 register before setting the prsm0.bgce0 bit to 1. 3. set the prsm0 and prscm0 registers accordi ng to the main clock fr equency that is used so as to obtain an f brg frequency of 32.768 khz. the calculation for f brg is shown below. f brg = f bgcs /2n remark f bgcs : watch timer source clock set by the prsm0 register n: set value of the prscm0 register = 1 to 256 however, n = 256 when the prscm0 register is set to 00h.
v850es/jg3-l chapter 10 watch timer r01uh0165ej0700 rev.7.00 page 455 of 1113 sep 22, 2011 (3) watch timer operation mode register (wtm) the wtm register enables or disables the count clock and operation of the watch timer, sets the interval time of the prescaler, controls the operat ion of the 5-bit counter, and sets the set time of the watch flag. set the prsm0 register before setting the wtm register. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. (1/2) wtm7 2 4 /f w (488 s: f w = f xt ) 2 5 /f w (977 s: f w = f xt ) 2 6 /f w (1.95 ms: f w = f xt ) 2 7 /f w (3.91 ms: f w = f xt ) 2 8 /f w (7.81 ms: f w = f xt ) 2 9 /f w (15.6 ms: f w = f xt ) 2 10 /f w (31.3 ms: f w = f xt ) 2 11 /f w (62.5 ms: f w = f xt ) 2 4 /f w (488 s: f w = f brg ) 2 5 /f w (977 s: f w = f brg ) 2 6 /f w (1.95 ms: f w = f brg ) 2 7 /f w (3.90 ms: f w = f brg ) 2 8 /f w (7.81 ms: f w = f brg ) 2 9 /f w (15.6 ms: f w = f brg ) 2 10 /f w (31.2 ms: f w = f brg ) 2 11 /f w (62.5 ms: f w = f brg ) wtm7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 wtm6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 selection of interval time of prescaler wtm wtm6 wtm5 wtm4 wtm3 wtm2 wtm1 wtm0 wtm5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 wtm4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 after reset: 00h r/w address: fffff680h < > < >
v850es/jg3-l chapter 10 watch timer r01uh0165ej0700 rev.7.00 page 456 of 1113 sep 22, 2011 (2/2) 2 14 /f w (0.5 s: f w = f xt ) 2 13 /f w (0.25 s: f w = f xt ) 2 5 /f w (977 s: f w = f xt ) 2 4 /f w (488 s: f w = f xt ) 2 14 /f w (0.5 s: f w = f brg ) 2 13 /f w (0.25 s: f w = f brg ) 2 5 /f w (977 s: f w = f brg ) 2 4 /f w (488 s: f w = f brg ) wtm7 0 0 0 0 1 1 1 1 selection of set time of watch flag clears after operation stops starts wtm1 0 1 control of 5-bit counter operation wtm3 0 0 1 1 0 0 1 1 wtm2 0 1 0 1 0 1 0 1 stops operation (clears both prescaler and 5-bit counter) enables operation wtm0 0 1 watch timer operation enable caution rewrite the wtm2 to wtm7 bits wh ile both the wtm0 and wtm1 bits are 0. remarks 1. f w : watch timer clock frequency 2. values in parentheses apply to operation with f w = 32.768 khz
v850es/jg3-l chapter 10 watch timer r01uh0165ej0700 rev.7.00 page 457 of 1113 sep 22, 2011 10.4 operation 10.4.1 watch timer operations the watch timer operates on the main clock or subclock (32.768 khz) and generates an interrupt request signal (intwt) at fixed, exact time in tervals of 0.25 or 0.5 seconds. counting starts when the wtm.wtm1 and wtm.wtm0 bits ar e set to 11. when the wtm0 bit is cleared to 0, the 11-bit prescaler and 5-bit counter are cleared and counting stops. the time of the watch timer can be adjusted by cleari ng the wtm1 bit to 0 and then clearing the 5-bit counter when the watch timer is operating at the same time as the inte rval timer. at this time, an error of up to 15.6 ms may occur in the watch timer, but the interval timer is not affected. if the main clock is used as the count clock of the watc h timer, set the count clo ck using the prsm0.bgcs01 and bgcs00 bits and the 8-bit comparison value using t he prscm0 register, and set the count clock frequency (f brg ) of the watch timer to 32.768 khz. when the prsm0.bgce0 bit is set to 1, f brg is supplied to the watch timer. f brg can be calculated by using the following expression. f brg = f x /(2 m+1 n) to set f brg to 32.768 khz, perform the following calculat ion and set the bgcs01 and bgcs00 bits and the prscm0 register. <1> set n = f x /65,536. set m = 0. <2> when the value resulting from rounding up the first dec imal place of n is even, set n before the roundup as n/2 and m as m + 1. <3> repeat <2> until n is odd or m = 3. <4> set the value resulting from rounding up the first dec imal place of n to the prscm0 register and m to the bgcs01 and bgcs00 bits. example: when f x = 4.00 mhz <1> n = 4,000,000/65,536 = 61.03?, m = 0 <2>, <3> because n (round up the first decimal place) is odd, n = 61, m = 0. <4> set value of prscm0 register: 3dh (61), set value of bgcs01 and bgcs00 bits: 00 at this time, the actual f brg frequency is as follows. f brg = f x /(2 m+1 n) = 4,000,000/(2 61) = 32.787 khz remark m: division value (set value of bgcs01 and bgcs00 bits) = 0 to 3 n: set value of prscm0 register = 1 to 256 however, n = 256 when prscm0 register is set to 00h. f x : main clock oscillator frequency
v850es/jg3-l chapter 10 watch timer r01uh0165ej0700 rev.7.00 page 458 of 1113 sep 22, 2011 10.4.2 interval timer operations the watch timer can also be used as an interval timer that repeatedly generates an interrupt request signal (intwti) at intervals determined by certain conditions. the interval time can be selected by using t he wtm4 to wtm7 bits of the wtm register. table 10-1. interval ti me of interval timer wtm7 wtm6 wtm5 wtm4 interval time 0 0 0 0 2 4 1/fw 488 s (operating at f w = f xt = 32.768 khz) 0 0 0 1 2 5 1/fw 977 s (operating at f w = f xt = 32.768 khz) 0 0 1 0 2 6 1/fw 1.95 ms (operating at f w = f xt = 32.768 khz) 0 0 1 1 2 7 1/fw 3.91 ms (operating at f w = f xt = 32.768 khz) 0 1 0 0 2 8 1/fw 7.81 ms (operating at f w = f xt = 32.768 khz) 0 1 0 1 2 9 1/fw 15.6 ms (operating at f w = f xt = 32.768 khz) 0 1 1 0 2 10 1/fw 31.3 ms (operating at f w = f xt = 32.768 khz) 0 1 1 1 2 11 1/fw 62.5 ms (operating at f w = f xt = 32.768 khz) 1 0 0 0 2 4 1/fw 488 s (operating at f w = f brg = 32.768 khz) 1 0 0 1 2 5 1/fw 977 s (operating at f w = f brg = 32.768 khz) 1 0 1 0 2 6 1/fw 1.95 ms (operating at f w = f brg = 32.768 khz) 1 0 1 1 2 7 1/fw 3.91 ms (operating at f w = f brg = 32.768 khz) 1 1 0 0 2 8 1/fw 7.81 ms (operating at f w = f brg = 32.768 khz) 1 1 0 1 2 9 1/fw 15.6 ms (operating at f w = f brg = 32.768 khz) 1 1 1 0 2 10 1/fw 31.3 ms (operating at f w = f brg = 32.768 khz) 1 1 1 1 2 11 1/fw 62.5 ms (operating at f w = f brg = 32.768 khz) remark f w : watch timer clock frequency
v850es/jg3-l chapter 10 watch timer r01uh0165ej0700 rev.7.00 page 459 of 1113 sep 22, 2011 figure 10-2. timing of watch time r and interval timer operations start overflow overflow 0h interrupt time of watch timer (0.5 s) interrupt time of watch timer (0.5 s) interval time (t) interval time (t) nt nt 5-bit counter count clock watch timer interrupt intwt interval timer interrupt intwti remarks 1. when 0.5 seconds is set as the watch timer interrupt time. 2. f w : watch timer clock frequency values in parentheses apply to operation with f w = 32.768 khz. (wtm7 = 1, wtm3, wtm2 = 00) n: number of interval timer operations
v850es/jg3-l chapter 10 watch timer r01uh0165ej0700 rev.7.00 page 460 of 1113 sep 22, 2011 10.5 cautions (1) operation as watch timer the first watch timer interrupt request signal (intwt) is not generated at the exact time specified using the wtm2 and wtm3 bits after operation is enabled (wtm .wtm1 and wtm.wtm0 bits = 11). the second and subsequent intwt signals are generated at the specified time. figure 10-3. example of generation of watc h timer interrupt request signal (intwt) (when interrupt cycle = 0.5 s) it takes 0.515625 seconds (max.) for the first intwt signal to be generated (2 9 1/32768 = 0.015625 seconds longer (max.)). the intwt signal is then generated every 0.5 seconds. 0.5 s 0.5 s 0.515625 s wtm0, wtm1 intwt (2) when watch timer and interval timer wt operate simultaneously the interval time of interval timer wt can be set to a value between 488 s and 62.5 ms. it cannot be changed later. do not stop interval timer wt (by clearing the wtm.wtm0 bit to 0) while the watch timer is operating. if the wtm0 bit is set to 1 again after it had been cleared to 0, the watch timer will have a discrepancy of up to 0.5 or 0.25 seconds.
v850es/jg3-l chapter 11 real-time counter ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 461 of 1113 sep 22, 2011 chapter 11 real-time counter ( pd70f3792, 70f3793, 70f3841, 70f3842) 11.1 functions the real-time counter (rtc) has the following features. ? counting up to 99 years using year, month, day-of-w eek, day, hour, minute, and second sub-counters provided ? year, month, day-of-week, day, hour, minute, and second counter display using bcd codes note 1 ? alarm interrupt function ? constant-period interrupt function (period: 1 month to 0.5 second) ? interval interrupt function (period: 1.95 ms to 125 ms) ? pin output function of 1 hz ? pin output function of 32.768 khz ? pin output function of 512 hz or 16.384 khz ? watch error correction function ? subclock operation or main clock operation note 2 selectable notes 1. a bcd (binary coded decimal) code expresses each digit of a decimal number in 4-bit binary format. 2. use the baud rate generator dedicated to the real -time counter to divide the main clock frequency to 32.768 khz for use. cautions 1. the watch timer and rtc alternate interrupt signal and therefore cannot be used simultaneously. 2. if the normal operating mode is restored a fter entering the rtc backup mode, an error of up to 1 second might occur for the rtc subcounter. 3. the usable rtc functions differ as shown below in the normal operating mode and rtc backup mode. function normal operation mode rtc backup mode year, month, day-of-week, day, hour, minute, sub-coubters count function enable enable interrupt function (alarm, constant-period, interval) enable disable pin output function (32.768 khz, 16.384 khz, 512 khz, 1hz) enable disable watch error correction function enable disable
v850es/jg3-l chapter 11 real-time counter ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 462 of 1113 sep 22, 2011 11.2 configuration the real-time counter includes the following hardware. table 11-1. configuration of real-time counter item configuration control registers real-time counter control register 0 (rc1cc0) real-time counter control register 1 (rc1cc1) real-time counter control register 2 (rc1cc2) real-time counter control register 3 (rc1cc3) sub-count register (rc1subc) second count register (rc1sec) minute count register (rc1min) hour count register (rc1hour) day count register (rc1day) day-of-week count register (rc1week) month count register (rc1month) year count register (rc1year) watch error correction register (rc1subu) alarm minute register (rc1alm) alarm hour register (rc1alh) alarm week register (rc1alw) prescaler mode register 0 (prsm0) prescaler compare register 0 (prscm0)
v850es/jg3-l chapter 11 real-time counter ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 463 of 1113 sep 22, 2011 figure 11-1. block diagram of real-time counter count enable/ disable circuit sub-counter (16-bit) second counter (7-bit) second counter write buffer minute counter write buffer hour counter write buffer day counter write buffer week counter write buffer minute counter (7-bit) hour counter (6-bit) day counter (3-bit) day-of week counter (3-bit) intrtc0 intrtc1 1 minute 1 hour 1 day 1 month count clock = 32.768 khz f xt f xt /2 6 f xt /2 f xt /2 6 f xt /2 7 f xt /2 8 f xt /2 9 f xt /2 10 f xt /2 11 f xt /2 12 f brg note month counter write buffer year counter write buffer month counter (5-bit) year counter (8-bit) minute alarm ict2 to ict0 hour alarm day-of-week alarm 12-bit counter ckdiv rinte intrtc2 rtcdiv cloe2 rtccl cloe0 rtc1hz cloe1 selector selector selector selector note for detail of f brg , refer to 11.3 (17) prescaler mode register 0 (prsm0) and 11.3 (18) prescaler compare register 0 (prscm0). remark f brg : real-time counter count clock frequency f xt : subclock frequency intrtc0: real-time counter fixed-cycle signal intrtc1: real-time counter alarm interrupt signal intrtc2: real-time counter interval signal
v850es/jg3-l chapter 11 real-time counter ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 464 of 1113 sep 22, 2011 11.2.1 pin configuration the rtc outputs included in the real-tim e counter are alternatively used as sh own in table 11-2. the port function must be set when using each pin (see table 4-15 settings when pins are used for alternate functions ). table 11-2. pin configuration pin number gc f1 port rtc output other alternate function 30 g3 p03 rtc1hz intp0/adtrg 28 h4 p04 rtcdiv intp1/adtrg /rtccl 28 h4 p04 rtccl intp1/adtrg /rtcdiv remark gc : 100-pin plastic lqfp (fine pitch) (14 14) f1 : 121-pin plastic fbga (8 8) 11.2.2 interrupt functions the rtc includes the following three types of interrupt signals. (1) intrtc0 a fixed-cycle interrupt signal is generated every 0.5 second, second, minute, hour, day, or month. (2) intrtc1 alarm interrupt signal (3) intrtc2 an interval interrupt signal of a cycle of f xt /2 6 , f xt /2 7 , f xt /2 8 , f xt /2 9 , f xt /2 10 , f xt /2 11 , or f xt /2 12 is generated.
v850es/jg3-l chapter 11 real-time counter ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 465 of 1113 sep 22, 2011 11.3 registers the real-time counter is controlle d by the following 18 registers. (1) real-time counter cont rol register 0 (rc1cc0) the rc1cc0 register selects the real-time counter input clock. this register can be read or written in 8-bit or 1-bit units. rc1pwr stops real-time counter operation. enables real-time counter operation. rc1pwr 0 1 real-time counter operation control rc1cc0 rc1cks 0 0 0 0 0 0 654321 selects f xt as operation clock. selects f brg as operation clock. rc1cks note2 0 1 operation clock selection 0 7 after reset: note 1 r/w address: fffffaddh notes1. rv dd power-on reset : 00h other kind of reset : previous value retained 2. be sure to clear rc1 cks bit to 0 in the rtc backup mode (rtcbumctl0.rbmset = 1). for detail, see 23.9 rtc backup mode ( pd70f3792, 70f3793, 70f3841, 70f3842). cautions 1. follow the descrip tion in 11.4.8 initializing r eal-time counter when stopping (rc1pwr = 1 0) the real-time counter while it is operating. 2. the rc1cks bit can be rewritten onl y when the real-time counter is stopped (rc1pwr bit = 0). furthermore, rewriti ng the rc1cks bit at the same time as setting the rc1pwr bit from 0 to 1 is prohibited. (2) real-time counter cont rol register 1 (rc1cc1) the rc1cc1 register is an 8-bit regist er that starts or stops the real-t ime counter, controls the rtccl and rtc1hz pins, selects the 12-hour or 24-hour system , and sets the fixed-cycle interrupt function. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h.
v850es/jg3-l chapter 11 real-time counter ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 466 of 1113 sep 22, 2011 rtce stops counter operation. enables counter operation. rtce 0 1 control of operation of each counter rc1cc1 0 cloe1 cloe0 note ampm ct2 ct1 ct0 654321 disables rtc1hz pin output (1 hz) enables rtc1hz pin output (1 hz) cloe1 0 1 rtc1hz pin output control disables rtccl pin output (32.768 khz) enables rtccl pin output (32.768 khz) cloe0 0 1 rtccl pin output control 12-hour system (a.m. and p.m. are displayed.) 24-hour system ampm 0 1 12-hour system/24-hour system selection 0 7 after reset: note r/w address: fffffadeh does not use fixed-cycle interrupts once in 0.5 second (synchronous with second count-up) once in 1 second (simultaneous with second count-up) once in 1 minute (every minute at 00 seconds) once in 1 hour (every hour at 00 minutes 00 seconds) once in 1 day (every day at 00 hours 00 minutes 00 seconds) once in 1 month (one day every month at 00 hours 00 minutes 00 seconds a.m.) ct2 0 0 0 0 1 1 1 fixed-cycle interrupt (intrtc0) selection ct1 0 0 1 1 0 0 1 ct0 0 1 0 1 0 1 note rv dd power-on reset : 00h other kind of reset : previous value retained cautions 1. writing 0 to the rtce bit while the rt ce bit is 1 is prohibited. clear the rtce bit by clearing the rc1pwr bit according to 11.4.8 initializing real-time counter. 2. the rtc1hz output operates as follows when the cloe1 bit setting is changed. ? when changed from 0 to 1: the rtc1 hz output outputs a 1 hz pulse after two clocks or less (2 32.768 khz). ? when changed from 1 to 0: the rt c1hz output is stopped (fixed to low level) after two clocks or less (2 32.768 khz). 3. see 11.4.1 initial settings and 11.4.2 re writing each counter dur ing real-time counter operation for setting or changing the ampm bit. furthermore, re-set the rc1hour register when the ampm bit is rewritten. 4. see 11.4.4 changing intrtc0 interrupt setting during real-time counter operation when rewriting the ct2 to ct0 bits whil e the real-time count er operates (rc1pwr bit = 1). remark when rtc back up mode, fixed-cycle and rtccl pin output are stop.
v850es/jg3-l chapter 11 real-time counter ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 467 of 1113 sep 22, 2011 (3) real-time counter cont rol register 2 (rc1cc2) the rc1cc2 register is an 8-bit regi ster that controls the alarm interr upt function and waiting of counters. this register can be read or written in 8-bit or 1-bit units. wale does not generate interrupt upon alarm match. generates interrupt upon alarm match. wale 0 1 alarm interrupt (intrtc1) operation control rc1cc2 0000 0 rwst rwait 654321 counter operating counting up of second to year counters stopped (reading and writing of counter values enabled) rwst 0 1 real-time counter wait state this is a status flag indicating whether the rwait bit setting is valid. read or write counter values after confirming that the rwst bit is 1. sets counter operation. stops count operation of second to year counters. (counter value read/write mode) rwait 0 1 real-time counter wait control this bit controls the operation of the counters. be sure to write 1 to this bit when reading or writing counter values. if the rc1subc register overflows while the rwait bit is 1, the overflow information is retained internally and the rc1sec register is counted up after two clocks or less (2 32.768 khz) after 0 is written to the rwait bit. however, if the second counter value is rewritten while the rwait bit is 1, the retained overflow information is discarded. 0 7 after reset: note r/w address: fffffadfh note rv dd power-on reset : 00h other kind of reset : previous value retained cautions 1. see 11.4.5 changing intrtc1 inte rrupt setting during real-ti me counter operation when rewriting the wale bit while the r eal-time counter operates (rc1pwr bit = 1). 2. confirm that the rwst bit is set to 1 when reading or writing each counter value. 3. the rwst bit does not become 0 while each counter is being written, even if the rwait bit is set to 0. it becomes 0 wh en writing to each c ounter is completed. remark when rtc back up mode, alarm interrupt is stop.
v850es/jg3-l chapter 11 real-time counter ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 468 of 1113 sep 22, 2011 (4) real-time counter cont rol register 3 (rc1cc3) the rc1cc3 register is an 8-bit register that cont rols the interval interrupt function and rtcdiv pin. this register can be read or written in 8-bit or 1-bit units. rinte does not generate interval interrupt. generates interval interrupt. rinte 0 1 interval interrupt (intrtc2) control rc1cc3 cloe2 ckdiv 00 ict2 ict1 ict0 654321 disables rtcdiv pin output. enables rtcdiv pin output. cloe2 0 1 rtcdiv pin output control outputs 512 hz (1.95 ms) from rtcdiv pin. outputs 16.384 khz (0.061 ms) from rtcdiv pin. ckdiv 0 1 rtcdiv pin output frequency selection 0 7 after reset: note r/w address: fffffae0h 2 6 /f xt (1.953125 ms) 2 7 /f xt (3.90625 ms) 2 8 /f xt (7.8125 ms) 2 9 /f xt (15.625 ms) 2 10 /f xt (31.25 ms) 2 11 /f xt (62.5 ms) 2 12 /f xt (125 ms) ict2 0 0 0 0 1 1 1 interval interrupt (intrtc2) selection ict1 0 0 1 1 0 0 1 ict0 0 1 0 1 0 1 note rv dd power-on reset : 00h other kind of reset : previous value retained cautions 1. see 11.4.7 changing intrtc2 inte rrupt setting during real-ti me counter operation when rewriting the rinte bit during real-t ime counter operation (rc1pwr bit = 1). 2. the rtcdiv output operates as follows when the cloe2 bit se tting is changed. ? when changed from 0 to 1: a pulse set by the ckdiv bit is output after two clocks or less (2 32.768khz). ? when changed from 1 to 0: output of the rtcdiv output is stopped after two clocks or less (fixed to low level, 2 32.768khz)). 3. see 11.4.7 changing intrtc2 interrupt setting during real-time counter operation when rewriting the ict2 to ict0 bits wh ile the real-time counter operates (rc1pwr bit = 1). remark when rtc back up mode, interval inte rrupt and rtcdiv pin output are stop.
v850es/jg3-l chapter 11 real-time counter ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 469 of 1113 sep 22, 2011 (5) sub-count register (rc1subc) the rc1subc register is a 16-bit regi ster that counts the reference time of 1 second of the real-time counter. it takes a value of 0000h to 7fffh and counts one second with a cl ock of 32.768 khz. this register is read-only, in 16-bit units. cautions 1 when a correction is made by us ing the rc1subu register, the value may become 8000h or more. 2. this register is al so cleared by writing to the second count register. 3. the value read from this register is not guaranteed if it is read during operation, because a changing value is read. rc1subc 12 1 08 6 42 after reset: note r address: fffffad0h 14 0 1 3 11 9 7 53 1 5 1 note rv dd power-on reset : 0000h other kind of reset : previous value retained (6) second count register (rc1sec) the rc1sec register is an 8-bit register that takes a value of 0 to 59 (decimal) and indicates the count value of seconds. it counts up when the sub-counter overflows. when data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (2 32.768 khz) later. set a decimal value of 00 to 59 to this regi ster in bcd code. if a value outside this range is set, the register value returns to the normal value after one period. this register can be read or written in 8-bit units. caution setting the rc1sec register to values other than 00 to 59 is prohibited. remark see 11.4.1 initial settings , 11.4.2 rewriting each counter dur ing real-time counter operation , and 11.4.3 reading each counter durin g real-time counter operation when reading or writing the rc1sec register. 0 rc1sec after reset: note r/w address: fffffad2h note rv dd power-on reset : 00h other kind of reset : previous value retained
v850es/jg3-l chapter 11 real-time counter ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 470 of 1113 sep 22, 2011 (7) minute count register (rc1min) the rc1min register is an 8-bit regist er that takes a value of 0 to 59 ( decimal) and indicates the count value of minutes. it counts up when the second counter overflows. when data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (2 32.768 khz) later. set a decimal value of 00 to 59 to this register in bcd code. this register can be read or written 8-bit units. caution setting a value other than 00 to 59 to the rc1min register is prohibited. remark see 11.4.1 initial settings , 11.4.2 rewriting each counter dur ing real-time counter operation , and 11.4.3 reading each counter durin g real-time counter operation when reading or writing the rc1min register. 0 rc1min after reset: note r/w address: fffffad3h note rv dd power-on reset : 00h other kind of reset : previous value retained (8) hour count register (rc1hour) the rc1hour register is an 8-bit regi ster that takes a value of 0 to 23 or 1 to 12 (decimal) and indicates the count value of hours. it counts up when the minute counter overflows. when data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (2 32.768 khz) later. set a decimal value of 00 to 23, 01 to 12, or 21 to 32 to this register in bcd code. if a value outside this range is set, the register value returns to the normal value after 1 period. this register can be read or written 8-bit units. however, the value of this register is 00h if the ampm bit is set to 1 after rv dd power-on reset . cautions 1. bit 5 of the rc1hour register indi cates a.m. (0) or p.m. (1) if ampm = 0 (if the 12-hour system is selected). 2. setting a value other than 01 to 12, 21 to 32 (ampm bit= 0), or 00 to 23 (ampm bit = 1) to the rc1hour register is prohibited. remark see 11.4.1 initial settings , 11.4.2 rewriting each counter dur ing real-time counter operation , and 11.4.3 reading each counter durin g real-time counter operation when reading or writing the rc1hour register. 00 rc1hour after reset: note r/w address: fffffad4h note rv dd power-on reset : 12h other kind of reset : previous value retained
v850es/jg3-l chapter 11 real-time counter ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 471 of 1113 sep 22, 2011 table 11-3 shows the relationship among the ampm bit setting value, rc1hour register value, and time. table 11-3. time digit display 12-hour display (ampm bit = 0) 24-hour display (ampm bit = 1) time rc1hour register value time rc1hour register value 0:00 a.m. 12 h 0:00 00h 1:00 a.m. 01 h 1:00 01 h 2:00 a.m. 02 h 2:00 02 h 3:00 a.m. 03 h 3:00 03 h 4:00 a.m. 04 h 4:00 04 h 5:00 a.m. 05 h 5:00 05 h 6:00 a.m. 06 h 6:00 06 h 7:00 a.m. 07 h 7:00 07 h 8:00 a.m. 08 h 8:00 08 h 9:00 a.m. 09 h 9:00 09 h 10:00 a.m. 10 h 10:00 10 h 11:00 a.m. 11 h 11:00 11 h 0:00 p.m. 32 h 12:00 12 h 1:00 p.m. 21 h 13:00 13 h 2:00 p.m. 22 h 14:00 14 h 3 :00 p.m. 23 h 15:00 15 h 4:00 p.m. 24 h 16:00 16 h 5:00 p.m. 25 h 17:00 17 h 6:00 p.m. 26 h 18:00 18 h 7:00 p.m. 27 h 19:00 19 h 8:00 p.m. 28 h 20:00 20 h 9:00 p.m. 29 h 21:00 21 h 10:00 p.m. 30 h 22:00 22 h 11:00 p.m. 31 h 23:00 23 h the rc1hour register value is displayed in 12 hour-for mat if the ampm bit is 0 and in 24-hour format when the ampm bit is 1. in 12-hour display, a.m. or p.m. is indicated by t he fifth bit of rchour: 0 indicating before noon (a.m.) and 1 indicating noon or afternoon (p.m.).
v850es/jg3-l chapter 11 real-time counter ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 472 of 1113 sep 22, 2011 (9) day count register (rc1day) the rc1day register is an 8-bit register that takes a value of 1 to 31 (decimal) and indicates the count value of days. it counts up when the hour counter overflows. this counter counts as follows. ? 01 to 31 (january, march, may, july, august, october, december) ? 01 to 30 (april, june, september, november) ? 01 to 29 (february in leap year) ? 01 to 28 (february in normal year) when data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (2 32.768 khz) later. set a decimal value of 00 to 31 to this register in bcd code. this register can be read or written in 8-bit units. caution setting a value other than 01 to 31 to the rc1day register is prohibited. setting a value outside the above-mentioned count range, such as ?february 30? is also prohibited. remark see 11.4.1 initial settings , 11.4.2 rewriting each counter dur ing real-time counter operation , and 11.4.3 reading each counter durin g real-time counter operation when reading or writing the rc1day register. 00 rc1day after reset: note r/w address: fffffad6h note rv dd power-on reset : 01h other kind of reset : previous value retained
v850es/jg3-l chapter 11 real-time counter ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 473 of 1113 sep 22, 2011 (10) day-of-week count register (rc1week) the rc1week register is an 8-bit register that ta kes a value of 0 to 6 (decimal) and indicates the day-of-week count value. it counts up in synchronization with the day counter. when data is written to this register , it is written to a buffer and t hen to the counter up to 2 clocks (2 32.768 khz) later. set a decimal value of 00 to 06 to this register in bcd code. if a value outside this range is set, the register value returns to the normal value after 1 period. this register can be read or written in 8-bit units. 00000 rc1week after reset: note r/w address: fffffad5h note rv dd power-on reset : 00h other kind of reset : previous value retained cautions 1. setting a value other than 00 to 06 to the rc1week register is prohibited. 2. values corresponding to the month count register and day count register are not automatically stored to the day-of-week register. be sure to set as follows after rest release. day of week rc1week sunday 00h monday 01h tuesday 02h wednesday 03h thursday 04h friday 05h saturday 06h remark see 11.4.1 initial settings , 11.4.2 rewriting each counter dur ing real-time counter operation , and 11.4.3 reading each counter dur ing real-time counter operation when reading or writing the rc1week register.
v850es/jg3-l chapter 11 real-time counter ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 474 of 1113 sep 22, 2011 (11) month count register (rc1month) the rc1month register is an 8-bit r egister that takes a value of 1 to 12 (decimal) and indicates the count value of months. it counts up when the day counter overflows. when data is written to this register , it is written to a buffer and t hen to the counter up to 2 clocks (2 32.768 khz) later. set a decimal value of 01 to 12 to this register in bcd code. this register can be read or written in 8-bit units. caution setting a value other than 01 to 12 to the rc1month register is prohibited. remark see 11.4.1 initial settings , 11.4.2 rewriting each counter dur ing real-time counter operation , and 11.4.3 reading each counter dur ing real-time counter operation when reading or writing the rc1month register. 000 rc1month after reset: note r/w address: fffffad7h note rv dd power-on reset : 01h other kind of reset : previous value retained (12) year count re gister (rc1year) the rc1year register is an 8-bit register that takes a value of 0 to 99 (decimal) and indicates the count value of years. it counts up when the month counter overflows. values 00, 04, 08, ?, 92, and 96 indicate a leap year. when data is written to this register , it is written to a buffer and t hen to the counter up to 2 clocks (2 32.768 khz) later. set a decimal value of 00 to 99 to this register in bcd code. this register can be read or written in 8-bit units. caution setting a value other than 00 to 99 to the rc1year register is prohibited. remark see 11.4.1 initial settings , 11.4.2 rewriting each counter dur ing real-time counter operation , and 11.4.3 reading each counter dur ing real-time counter operation when reading or writing the rc1year register. rc1year after reset: note r/w address: fffffad8h note rv dd power-on reset : 00h other kind of reset : previous value retained
v850es/jg3-l chapter 11 real-time counter ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 475 of 1113 sep 22, 2011 (13) watch error correction register (rc1subu) the rc1subu register is an 8-bit register that can be used to correct the watch with high accuracy when the watch is early or late, by changing the value (refere nce value: 7fffh) overflow ing from the sub-count register (rsubc) to the second counter register. this register can be read or written in 8-bit or 1-bit units. remarks 1. the rc1subu register can be rewritten only when the real-time counter is set to its initial values. be sure to see 11.4.1 initial settings . 2. see 11.4.9 watch error correcti on example of real-time counter for details of watch error correction. 3. when rtc back up mode, watch error correction is stop. dev corrects watch errors when rc1sec (second counter) is at 00, 20, or 40 seconds (every 20 seconds). corrects watch errors when rc1sec (second counter) is at 00 seconds (every 60 seconds). dev 0 1 setting of watch error correction timing rc1subu f6 f5 f4 f3 f2 f1 f0 654321 increments the rc1subc count value by the value set using the f5 to f0 bits (positive correction). expression for calculating increment value: (setting value of f5 to f0 bits ? 1) 2 decrements the rc1subc count value by the value set using the f5 to f0 bits (negative correction). expression for calculating decrement value: (inverted value of setting value of f5 to f0 bits + 1) 2 f6 0 1 setting of watch error correction value if the f6 to f0 bit values are {1/0, 0, 0, 0, 0, 0, 1/0}, watch error correction is not performed. 0 7 after reset: note r/w address: fffffad9h note rv dd power-on reset : 00h other kind of reset : previous value retained
v850es/jg3-l chapter 11 real-time counter ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 476 of 1113 sep 22, 2011 (14) alarm minute setting register (rc1alm) the rc1alm register is an 8-bit register that is used to set minutes of alarm. this register can be read or written in 8-bit units. caution set a decimal value of 00 to 59 to this register in bcd code. if a value outside the range is set, the alarm is not detected. 0 rc1alm after reset: note r/w address: fffffadah note rv dd power-on reset : 00h other kind of reset : previous value retained (15) alarm hour setting register (rc1alh) the rc1alh register is an 8-bit register that is used to set hours of alarm. this register can be read or written in 8-bit units. cautions 1. set a decimal value of 00 to 23, 01 to 12, or 21 to 32 to this register in bcd code. if a value outside the range is set, the alarm is not detected. 2. bit 5 of the rc1alh regi ster indicates a.m. (0) or p.m. (1) if the ampm bit = 0 (12-hour system) is selected. 00 rc1alh after reset: note r/w address: fffffadbh note rv dd power-on reset : 12h other kind of reset : previous value retained
v850es/jg3-l chapter 11 real-time counter ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 477 of 1113 sep 22, 2011 (16) alarm day-of-week setting register (rc1alw) the rc1alw register is an 8-bit register that is used to set the day-of-week of the alarm. this register can be read or written in 8-bit units. caution see 11.4.5 changing intrtc1 interrupt setting during clock operation when rewriting the rc1alw register while the real-time counter operates (rc1pwr bit = 1). 0 rc1alw6 rc1alw5 rc1alw4 rc1alw3 rc1alw2 rc1alw1 rc1alw0 saturday friday thursday wednesday tuesday monday sunday rc1alw after reset: note r/w address: fffffadch does not generate alarm interrupt if rc1week = 06h (saturday). generates an alarm interrupt if the time specified by using the rc1alm and rc1alh registers is reached while rc1week is set to 06h (saturday). rc1alw6 0 1 alarm interrupt day-of-week bit 6 does not generate alarm interrupt if rc1week = 05h (friday). generates an alarm interrupt if the time specified by using the rc1alm and rc1alh registers is reached while rc1week is set to 05h (friday). rc1alw5 0 1 alarm interrupt day-of-week bit 5 does not generate alarm interrupt if rc1week = 04h ( thursday ). generates an alarm interrupt if the time specified by using the rc1alm and rc1alh registers is reached while rc1week is set to 04h (thursday). rc1alw4 0 1 alarm interrupt day-of-week bit 4 does not generate alarm interrupt if rc1week = 03h (wednesday). generates an alarm interrupt if the time specified by using the rc1alm and rc1alh registers is reached while rc1week is set to 03h (wednesday). rc1alw3 0 1 alarm interrupt day-of-week bit 3 does not generate alarm interrupt if rc1week = 02h ( tues day). generates an alarm interrupt if the time specified by using the rc1alm and rc1alh registers is reached while rc1week is set to 02h (tuesday). rc1alw2 0 1 alarm interrupt day-of-week bit 2 does not generate alarm interrupt if rc1week = 01h (monday). generates an alarm interrupt if the time specified by using the rc1alm and rc1alh registers is reached while rc1week is set to 01h ( monday ). rc1alw1 0 1 alarm interrupt day-of-week bit 1 does not generate alarm interrupt if rc1week = 00h (sunday). generates an alarm interrupt if the time specified by using the rc1alm and rc1alh registers is reached while rc1week is set to 00h (sunday). rc1alw0 0 1 alarm interrupt day-of-week bit 0 note rv dd power-on reset : 00h other kind of reset : previous value retained
v850es/jg3-l chapter 11 real-time counter ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 478 of 1113 sep 22, 2011 (a) alarm interrupt setting examples (rc1al m, rc1alh, and rc1alw setting examples) tables 11-4 and 11-5 show setting examples if sunday is rc1week = 00, monday is rc1week = 01, tuesday is rc1week = 02, , and saturday is rc1week = 06. table 11-4. alarm setting example if ampm = 0 (rc1hour register 12-hour display) register alarm setting time rc1alw rc1alh rc1alm sunday, 7:00 a.m. 01h 07h 00h sunday/monday, 00:15 p.m. 03h 32h 15h monday/tuesday/friday, 5:30 p.m. 26h 25h 30h everyday, 10:45 p.m. 7fh 30h 45h table 11-5. alarm setting example if ampm = 1 (rc1hour register 24-hour display) register alarm setting time rc1alw rc1alh rc1alm sunday, 7:00 01h 07h 00h sunday/monday, 12:15 03h 12h 15h monday/tuesday/friday, 17:30 26h 17h 30h everyday, 22:45 7fh 22h 45h (17) prescaler mode register 0 (prsm0) the prsm0 register controls the generation of the real time counter count clock (f brg ). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 prsm0 0 0 bgce0 0 0 bgcs01 bgcs00 disabled enabled bgce0 0 1 main clock operation enable f x f x /2 f x /4 f x /8 5 mhz 200 ns 400 ns 800 ns 1.6 s 4 mhz 250 ns 500 ns 1 s 2 s bgcs01 0 0 1 1 bgcs00 0 1 0 1 selection of real time counter source clock(f bgcs ) after reset : 00h r/w address : fffff8b0h < > cautions 1. do not change the values of the bgcs00 and bgcs01 bits during real time counteroperation. 2. set the prsm0 register before setting the bgce0 bit to 1. 3. set the prsm0 and prscm0 registers according to the main clock frequency that is usedso as to obtain an f brg frequency of 32.768 khz.
v850es/jg3-l chapter 11 real-time counter ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 479 of 1113 sep 22, 2011 (18) prescaler compare register 0 (prscm0) the prscm0 register is an 8-bit compare register. this register can be read or written in 8-bit units. reset sets this register to 00h. prscm07 prscm0 prscm06 prscm05 prscm04 prscm03 prscm02 prscm01 prscm00 after reset: 00h r/w address: fffff8b1h cautions 1. do not rewrite the prscm0 re gister during real ti me counter operation. 2. set the prscm0 register before setting the prsm0.bgce0 bit to 1. 3. set the prsm0 and prscm0 registers accordi ng to the main clock fr equency that is used so as to obtain an f brg frequency of 32.768 khz. the calculation for f brg is shown below. f brg = f bgcs /2n remark f bgcs : watch timer source clock set by the prsm0 register n: set value of the prscm0 register = 1 to 256 however, n = 256 when the prscm0 register is set to 00h.
v850es/jg3-l chapter 11 real-time counter ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 480 of 1113 sep 22, 2011 11.4 operation 11.4.1 initial settings the initial settings are set when operating the watch f unction and performing a fixed-cycle interrupt operation. figure 11-2. initial setting procedure setting ampm and ct2 to ct0 rc1cc0.rc1pwr bit = 0 start intrtc = 1? stops counter operation. selects 12-hour system or 24-hour system and interrupt (intrtc0). rc1cc0.rc1pwr bit = 1 enables real-time counter (rtc) internal clock operation. sets each count register. setting rc1subu sets watch error correction. setting rc1cks selects real-time counter (rtc) operation clock. no yes clearing interrupt if flag clears interrupt request flag (rtc0if) clearing interrupt mk flag clears interrupt mask flag (rtc0mk) rc1cc1.rtce bit = 1 starts counter operation. reading counter setting rc1sec (clearing rc1subc) setting rc1min setting rc1hour setting rc1week setting rc1day setting rc1month setting rc1year
v850es/jg3-l chapter 11 real-time counter ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 481 of 1113 sep 22, 2011 11.4.2 rewriting each counter du ring real-time c ounter operation set as follows when rewriting each counter (rc1se c, rc1min, rc1hour, rc1week, rc1day, rc1month, rc1year) during real-time counter operation (rc1pwr = 1, rtce = 1). figure 11-3. rewriting each counter during real-time counter operation start rc1cc2.rwait bit = 1 stops rc1sec to rc1year counters. counter value write/read mode setting ampm writing rc1sec writing rc1min writing rc1hour writing rc1week writing rc1day writing rc1month setting rc1year writes to each count register. selects watch counter display method. rc1cc2.rwait bit = 0 sets rc1sec to rc1year counter operation. rc1cc2.rwst bit = 0? no yes checks counter wait status. checks whether previous writing to rc1sec to rc1year counters is completed. end rc1cc2.rwst bit = 1? note no yes note be sure to confirm that rwst = 0 before setting stop mode. caution complete the series of operations for setting rwait to 1 to clearing rwait to 0 within 1 second. if rwait = 1 is set, the operation of rc1sec to rc1year is stopped. if a carry occurs from rc1subc while rwait = 1, one carry can be internally retained. however, if two or more carries occur, the number of carries cannot be retained. remark rc1sec, rc1min, rc1hour, rc1week, rc1day, rc1month, and rc1year may berewrite in any sequence. all the registers do not have to be set and only some registers may be read.
v850es/jg3-l chapter 11 real-time counter ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 482 of 1113 sep 22, 2011 11.4.3 reading each counter durin g real-time counter operation set as follows when reading each counter (rc1sec, rc1min, rc1hour, rc1w eek, rc1day, rc1month, rc1year) during real-time counter operation (rc1pwr = 1, rtce = 1). figure 11-4. reading each counter during real-time counter operation start rc1cc2.rwait bit = 1 stops rc1sec to rc1year counters. counter value write/read mode rc1cc2.rwait bit = 0 sets rc1sec to rc1year counter operation. rc1cc2.rwst bit = 0? no yes checks counter wait status. checks whether previous writing to rc1sec to rc1year is completed. end rc1cc2.rwst bit = 1? note no yes reading rc1sec reading rc1min reading rc1hour reading rc1week reading rc1day reading rc1month setting rc1year reads each count register. note be sure to confirm that rwst = 0 before setting stop mode. caution complete the series of operations for setting rwait to 1 to clearing rwait to 0 within 1 second. if rwait = 1 is set, the operation of rc1sec to rc1year is stopped. if a carry occurs from rc1subc while rwait = 1, one carry can be internally retained. however, if two or more carries occur, the number of carries cannot be retained. remark rc1sec, rc1min, rc1hour, rc1week, rc1 day, rc1month, and rc1year may be read in any sequence. all the registers do not have to be set and only some registers may be read.
v850es/jg3-l chapter 11 real-time counter ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 483 of 1113 sep 22, 2011 11.4.4 changing intrtc0 interrupt setti ng during real-time counter operation if the setting of the intrtc0 interrupt (fixed-cycle interrupt) signal is changed while the real-time counter clock operates (pc1pwr = 1, rtce =1), the intrct0 interrupt waveform may include whiskers and unintended signals may be output. set as follows when changing the setting of the intrtc0 interrupt signal during real-time counter operation (rc1pwr = 1, rtce = 1), in order to mask the whiskers. figure 11-5. changing intrtc0 interrupt setting during real-time counter operation start setting rtc0mk bit masks intrtc0 interrupt signal. setting rc1cc1.ct2 to rc1cc1.ct0 changes intrtc0 interrupt signal setting. end clearing rtc0if flag clears interrupt request flag. clearing rtc0mk flag unmasks intrtc0 interrupt signal. remark see 21.3.4 interrupt control register (xxicn) for details of the rtc0if and rtc0mk bits.
v850es/jg3-l chapter 11 real-time counter ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 484 of 1113 sep 22, 2011 11.4.5 changing intrtc1 interrupt setti ng during real-time counter operation if the setting of the intrtc1 interrupt (alarm interrupt) signal is changed while the real-time counter operates (rc1pwr = 1, rtce = 1), the intrct1 interrupt wavefo rm may include whiskers and unintended signals may be output. set as follows when changing the setting of the in trtc1 interrupt signal during real-time counter operation (pc1pwr = 1, rtce = 1), in order to mask the whiskers. figure 11-6. changing intrtc1 interrupt setting during real-time counter operation start setting rtc1mk bit masks interrupt signal (intrtc1). rc1cc2.wale bit = 0 disables alarm interrupt. rc1cc2.wale bit = 1 enables alarm interrupt. end clearing rtc1if flag clears interrupt pending bit. setting rc1alm setting rc1alh setting rc1alw sets alarm minute register. sets alarm hour register sets alarm day-of-week register clearing rtc1mk flag unmasks interrupt signal (intrtc1). remark see 21.3.4 interrupt control register (xxicn) for details of the rtc1if and rtc1mk bits.
v850es/jg3-l chapter 11 real-time counter ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 485 of 1113 sep 22, 2011 11.4.6 initial intrtc2 interrupt settings set as follows to set the intrtc 1 interrupt (interval interrupt). figure 11-7. intrtc2 interrupt setting start rc1cc0.rc1pwr bit = 1 enables counter operation. setting rc1cc3.ict2 to rc1cc3.ict0 bits <1> selects intrtc2 (interval) interrupt interval. end rc1cc3.rinte bit = 1 <2> enables intrtc2 (interval) interrupt. caution set <1> and <2> simultaneously or set <1> first. unintended waveform interrupts may occur if <2> is set first.
v850es/jg3-l chapter 11 real-time counter ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 486 of 1113 sep 22, 2011 11.4.7 changing intrtc2 interrupt setti ng during real-time counter operation if the setting of the intrtc2 interrupt (interval interrup t) is changed while the real-time counter clock operates (pc1pwr = 1, rtce = 1), the intrct2 interrupt waveform may include whiskers and unintended signals may be output. set as follows when changing the setting of the in trtc2 interrupt signal during real-time counter operation (pc1pwr = 1, rtce = 1), in order to mask the whiskers. figure 11-8. changing intrtc2 inte rrupt setting during clock operation start setting rtc2mk bit masks interrupt signal (intrtc2). setting rc1cc3.ict2 to rc1cc3.ict0 bits selects intrtc2 (interval) interrupt interval. end rc1cc3.rinte bit = 1 enables intrtc2 (interval) interrupt. clearing rtc2if flag clears interrupt pending bit. clearing rtc2mk flag unmasks interrupt signal (intrtc2). remark see 21.3.4 interrupt control register (xxicn) for details of the rtc2if and rtc2mk bits.
v850es/jg3-l chapter 11 real-time counter ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 487 of 1113 sep 22, 2011 11.4.8 initializing real-time counter the procedure for initializing the real-time counter is shown below. figure 11-9. initializing real-time counter start setting rtcnmk bit masks interrupt signal (intrtcn) end rc1cc0.rc1pwr bit = 0 initializes real-time counter (rtc). rtcdiv interrupt disable processing rtc1hz interrupt disable processing rtccl interrupt disable processing rc1cc3.cloe2 bit = 0 rc1cc1.cloe1 bit = 0 rc1cc1.cloe0 bit = 0 clearing rtcnif flag clears interrupt request bit. clearing rtcnmk flag unmasks interrupt signal (intrtcn). remarks 1. see 21.3.4 interrupt control register (xxicn) for details of the rtcnif and rtcnmk bits. 2. n = 0 to 2
v850es/jg3-l chapter 11 real-time counter ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 488 of 1113 sep 22, 2011 11.4.9 watch error correction exa mple of real-time counter the watch error correction function corrects deviation in the oscillation frequency of a resonator connected to the pd70f3792, 70f3793, 70f3841, 70f3842. deviation, here, refers to steady-state deviation, wh ich is deviation in the fr equency when the resonator is designed. next, the timing chart when an error has occurred in the input clock intended to be 32.768 khz but a 32.7681 khz resonator has been connected when designing the system, and the rc1subc and rc1sec count operations to correct the error are shown below. figure 11-10. watch error correction example rtcclk (32.768 khz) rc1subc watch count (32.768 khz) rc1sec 01 01 00 00 7fffh 0000h 7fffh 0000h 7fffh 0000h 7fffh 7fffh 0000h 0000h 20 20 19 19 rtcclk (32.7681 khz) rc1subc rc1sec 7fffh 7fffh 0000h 0000h 0000h 7fffh 7fffh 0000h 7fffh 8000h 8001h 8000h 8001h 0000h 0000h rtcclk (32.7681 khz) rc1subc rc1sec 20 seconds note 3 00 20 20 seconds note 1 01 19 7fffh 0000h 0000h 7fffh 7fffh 7fffh 0000h 19.99994 seconds note 2 watch count (32.7681 khz /error correction (dev bit = 0, f6 bit = 0, f5 to f0 bit = 000010)) watch count (32.7681 khz /no error correction ) 2 count numbers are added. 2 count numbers are added. notes 1. the rc1sec counter counts 20 seconds every 32,7 68 cycles (0000h to 7fffh) of the 32.768 khz clock. 2. when 32,768 cycles (0 000h to 7fffh) of the 32.7681 khz clo ck are input, the time counted by the rc1sec counter is calculated as follows: 32,768/3,268.1 ? 0.999997 seconds if this counting continues 20 times, the time is calculated as follows: (32,768/32,768.1) x 20 ? 19.99994 seconds, which causes an error of 0.00006 seconds. 3. to precisely count 20 seconds by using a 32.7681 khz clock, clear the dev and f6 bits to 0 and set the f5 to f0 bits to 2h (000010b) in the rc1subu register. as a result, two additional cycles are counted every 20 seconds (when the rc1sec counter count is 00, 20, and 40 seconds), so that the number of cycles counted at these po ints is not 32,768, but 32,770 (0000h to 8001h), which is exactly 20 seconds.
v850es/jg3-l chapter 11 real-time counter ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 489 of 1113 sep 22, 2011 as shown in figure 11-10, the watch can be accurately co unted by incrementing the rc1subc count value, if a positive error faster than 32.768 khz occu rs at the resonator. similarly, if a negative error slower than 32.768 khz occurs at the resonator, the watch can be accurately counted by decrementing the rc1subc count value. the rc1subc correction value is determined by using the rc1subu.f6 to rc1subu.f0 bits. the f6 bit is used to determine whether to increment or decrement rc1subc and the f5 to f0 bits to determine the rc1subc value. (1) incrementing the rc1subc count value the rc1subc count value is incremented by the value set using the f5 to f0 bits, by setting the f6 bit to 0. expression for calculating the increment value: (f5 to f0 bit value ? 1) 2 [example of incrementing the rc1subc count value: f6 bit = 0] if 15h (010101b) is set to the f5 to f0 bits (15h ? 1) 2 = 40 (increments the rc1subc count value by 40) rc1subc count value = 32,768 + 40 = 32,808 (2) decrementing the rc1subc count value the rc1subc count value is decremented by an inverted va lue of the value set using the f5 to f0 bits, by setting the f6 bit to 1. expression for calculating the decrement value: (inverted value of f5 to f0 bit value + 1) 2 [example of decrementing the rc1subc count value: f6 bit = 1] if 15h (010101b) is set to the f5 to f0 bits inverted data of 15h (010101b) = 2ah (101010b) (2ah + 1) 2 = 86 (decrements the rc1subc count value by 86) rc1subc count value = 32,768 ? 86 = 32,682
v850es/jg3-l chapter 11 real-time counter ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 490 of 1113 sep 22, 2011 (3) dev bit the dev bit determines when the setting by the f6 to f0 bits is enabled. the value set by the f6 to f0 bits is reflected upon t he next timing, but not to the rc1subc count value every time. table 11-6. dve bit setting dev bit value timing of reflecting value to rc1subc 0 when rc1sec is 00, 20, or 40 seconds. 1 when rc1sec is 00 seconds. [example when 0010101b is set to f6 to f0 bits] ? if the dev bit is 0 the rc1subc count value is 32,808 at 00, 20, or 40 seconds. otherwise, it is 32,768. ? if dev bit is 1 the rc1subc count value is 32,808 at 00 seconds. otherwise, it is 32,768. as described above, the rc1subc count value is corrected every 20 seconds or 60 seconds, instead of every second, in order to match the rc1subc count value with the deviation width of the resonator. the range in which the resonator frequency can be actually corrected is shown below. ? if the dev bit is 0: 32.76180000 khz to 32.77420000 khz ? if the dev bit is 1: 32.76593333 khz to 32.77006667 khz the range in which the frequency can be corrected when the dev bit is 0 is three times wider than when the dev bit is 1. however, the accuracy of setting the frequency when the d ev bit is 1 is three times that when the dev bit is 0. tables 11-7 and 11-8 show the setting values of the dev, and f6 to f0 bits, and the corresponding frequencies that can be corrected.
v850es/jg3-l chapter 11 real-time counter ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 491 of 1113 sep 22, 2011 table 11-7. range of frequencies tha t can be corrected when dev bit = 0 f6 f5 to f0 rc1subc correction value frequency of connected clock (including steady-state deviation) 0 000000 no correction ? 0 000001 no correction ? 0 000010 increments rc1subc count value by 2 once every 20 seconds 32.76810000 khz 0 000011 increments rc1subc count value by 4 once every 20 seconds 32.76820000 khz 0 000100 increments rc1subc count value by 6 once every 20 seconds 32.76830000 khz . . . . 0 111011 increments rc1subc count value by 120 once every 20 seconds 32.77400000 khz 0 111110 increments rc1subc count value by 122 once every 20 seconds 32.77410000 khz 0 111111 increments rc1subc count value by 124 once every 20 seconds 32.77420000 khz (upper limit) 1 000000 no correction ? 1 000001 no correction ? 1 000010 decrements rc1subc count value by 124 once every 20 seconds 32.76180000 khz (lower limit) 1 000011 decrements rc1subc count value by 122 once every 20 seconds 32.76190000 khz 1 000100 decrements rc1subc count value by 120 once every 20 seconds 32.76200000 khz . . . . 1 11011 decrements rc1subc count value by 6 once every 20 seconds 32.76770000 khz 1 11110 decrements rc1subc count value by 4 once every 20 seconds 32.76780000 khz 1 11111 decrements rc1subc count value by 2 once every 20 seconds 32.76790000 khz table 11-8. range of frequencies tha t can be corrected when dev bit = 1 f6 f5 to f0 rc1subc correction value frequency of connected clock (including steady-state deviation) 0 000000 no correction ? 0 000001 no correction ? 0 000010 increments rc1subc count value by 2 once every 60 seconds 32.76803333 khz 0 000011 increments rc1subc count value by 4 once every 60 seconds 32.76806667 khz 0 000100 increments rc1subc count value by 6 once every 60 seconds 32.76810000 khz . . . . 0 111011 increments rc1subc count value by 120 once every 60 seconds 32.77000000 khz 0 111110 increments rc1subc count value by 122 once every 60 seconds 32.77003333 khz 0 111111 increments rc1subc count value by 124 once every 60 seconds 32.77006667 khz (upper limit) 1 000000 no correction ? 1 000001 no correction ? 1 000010 decrements rc1subc count value by 124 once every 60 seconds 32.76593333 khz (lower limit) 1 000011 decrements rc1subc count value by 122 once every 60 seconds 32.76596667 khz 1 000100 decrements rc1subc count value by 120 once every 60 seconds 32.76600000 khz . . . . 1 11011 decrements rc1subc count value by 6 once every 60 seconds 32.76790000 khz 1 11110 decrements rc1subc count value by 4 once every 60 seconds 32.76793333 khz 1 11111 decrements rc1subc count value by 2 once every 60 seconds 32.76796667 khz
v850es/jg3-l chapter 12 watchdog timer 2 r01uh0165ej0700 rev.7.00 page 492 of 1113 sep 22, 2011 chapter 12 watchdog timer 2 12.1 functions watchdog timer 2 is the default-start watchdog timer and st arts up automatically immediately after a reset ends. watchdog timer 2 starts up in reset mode and with the over flow time set to internal oscillator clock = 2 19 /f r . when watchdog timer 2 overflows, it generates the wdt2res signal to trigger a reset. watchdog timer 2 has the following features: ? it is the default-start watchdog timer note 1 . ? it triggers the following operations when it overflows: reset mode: watchdog timer 2 triggers a reset when it overflows (by generating the wdt2res signal). non-maskable interrupt request mode: watchdog timer 2 triggers nmi servicing when it overflows (by generating the intwdt2 signal) note 2 . ? either the main clock, internal oscillator clo ck, or subclock can be input as the source clock. notes 1. watchdog timer 2 automatically starts in the reset mode following reset release. when not using watchdog timer 2, either stop it oper ating before it triggers a reset, or clear it once and stop it before the next overflow. also, write to the wdtm2 register for verificati on purposes only once, even if the default settings (reset mode, loop detection time interval: 2 19 /f r ) do not need to be changed. 2. for details of the non-maskable interrupt serv icing that occurs due to the generation of the non-maskable interrupt request signal (intwdt2), see 21.2.2 (2) from intwdt2 signal .
v850es/jg3-l chapter 12 watchdog timer 2 r01uh0165ej0700 rev.7.00 page 493 of 1113 sep 22, 2011 12.2 configuration watchdog timer 2 includes the following hardware. table 12-1. configuration of watchdog timer 2 item configuration control registers watchdog timer mode register 2 (wdtm2) watchdog timer enable register (wdte) the following shows the block diagram of watchdog timer 2. figure 12-1. block diag ram of watchdog timer 2 f xx /2 9 clock input controller output controller wdt2res (internal reset signal) wdcs22 internal bus intwdt2 wdcs21 wdcs20 f xt wdcs23 wdcs24 0 wdm21 wdm20 selector 16-bit counter f xx /2 18 to f xx /2 25 , f xt /2 9 to f xt /2 16 , f r /2 12 to f r /2 19 watchdog timer enable register (wdte) watchdog timer mode register 2 (wdtm2) 3 3 2 clear f r /2 3 remark f xx : main clock frequency f xt : subclock frequency f r : internal oscillator clock frequency intwdt2: non-maskable interrupt request signal from watchdog timer 2 wdtres2: watchdog timer 2 reset signal
v850es/jg3-l chapter 12 watchdog timer 2 r01uh0165ej0700 rev.7.00 page 494 of 1113 sep 22, 2011 12.3 registers (1) watchdog timer mode register 2 (wdtm2) the wdtm2 register sets the overflow time and operation clock of watchdog timer 2. this register can be read or written in 8-bit units. th is register can be read any number of times, but it can be written only once following reset release. reset sets this register to 67h. caution accessing the wdtm2 register is prohibited in the following statuses. moreover, if the system is in the wait status, the only way to cancel the wait status is to execute a reset. for details, see 3.4.9 (1) accessing speci fic on-chip peripheral i/o registers. ? when the cpu operates on the subclock and main clock oscillation is stopped ? when the cpu operates on th e internal oscillator clock 0 wdtm2 wdm21 note wdm20 note wdcs24 note wdcs23 note wdcs22 wdcs21 wdcs20 after reset: 67h r/w address: fffff6d0h stops operation non-maskable interrupt request mode (generation of intwdt2 signal) reset mode (generation of wdt2res signal) wdm21 0 0 1 wdm20 0 1 - selection of operation mode of watchdog timer 2 note when the option byte function is used, if the wdtmd1 bit is set (to 1), the wmd21 and wdm20 bits are fixed to 1 (which specifies the reset mode) , and the wdcs24 and wdcs23 bits are fixed to 0 (which specifies the internal oscillation clock (f r ) as the operation clock). for detail, refer to chapter 29 option byte . cautions 1. for details of the wdcs20 to wdcs24 bi ts, see table 12-2 loop detection time interval of watchdog timer 2. 2. if the wdtm2 register is rewritten twice after a reset, an overfl ow signal is forcibly generated and the counter is reset. 3. to intentionally generate an overflow signa l, write data to the wdtm2 register twice, or write a value other than ?ach? to the wdte register once. however, when watchdog timer 2 is set to ?s top operation?, an overflow signal is not generated even if data is wri tten to the wdtm2 register twice, or a value other than ?ach? is written to the wdte register once. 4. to stop the operation of watchdog timer 2, set the rcm.rstop bit to 1 (to stop the internal oscillator) and write 00h in the wdtm2 register . if the rcm.rstop bit cannot be set to 1, set the wdcs23 bit to 1 (2 n /f xx is selected and the clock can be stopped in the idle1, idle2, sub-idle, and s ubclock operation modes).
v850es/jg3-l chapter 12 watchdog timer 2 r01uh0165ej0700 rev.7.00 page 495 of 1113 sep 22, 2011 table 12-2. loop detection time interval of watchdog timer 2 wdcs24 wdcs23 wdcs22 wdcs21 wdcs20 selected clock 100 khz (min.) 220 khz (typ.) 400 khz (max.) 0 0 0 0 0 2 12 /f r 41.0 ms 18.6 ms 10.2 ms 0 0 0 0 1 2 13 /f r 81.9 ms 37.2 ms 20.5 ms 0 0 0 1 0 2 14 /f r 163.8 ms 74.5 ms 41.0 ms 0 0 0 1 1 2 15 /f r 327.7 ms 148.9 ms 81.9 ms 0 0 1 0 0 2 16 /f r 655.4 ms 297.9 ms 163.8 ms 0 0 1 0 1 2 17 /f r 1310.7 ms 595.8 ms 327.7 ms 0 0 1 1 0 2 18 /f r 2621.4 ms 1191.6 ms 655.4 ms internal oscillator clock 0 0 1 1 1 2 19 /f r 5242.9 ms 2383.1 ms 1310.7 ms f xx = 20 mhz f xx = 16 mhz f xx = 10 mhz 0 1 0 0 0 2 18 /f xx 13.1 ms 16.4 ms 26.2 ms 0 1 0 0 1 2 19 /f xx 26.2 ms 32.8 ms 52.4 ms 0 1 0 1 0 2 20 /f xx 52.4 ms 65.5 ms 104.9 ms 0 1 0 1 1 2 21 /f xx 104.9 ms 131.1 ms 209.7 ms 0 1 1 0 0 2 22 /f xx 209.7 ms 262.1 ms 419.4 ms 0 1 1 0 1 2 23 /f xx 419.4 ms 524.3 ms 838.9 ms 0 1 1 1 0 2 24 /f xx 838.9 ms 1048.6 ms 1677.7 ms main clock 0 1 1 1 1 2 25 /f xx 1677.7 ms 2097.2 ms 3355.4 ms f xt = 32.768 khz 1 0 0 0 2 9 /f xt 15.625 ms 1 0 0 1 2 10 /f xt 31.25 ms 1 0 1 0 2 11 /f xt 62.5 ms 1 0 1 1 2 12 /f xt 125 ms 1 1 0 0 2 13 /f xt 250 ms 1 1 0 1 2 14 /f xt 500 ms 1 1 1 0 2 15 /f xt 1000 ms subclock 1 1 1 1 2 16 /f xt 2000 ms remark = either 0 or 1
v850es/jg3-l chapter 12 watchdog timer 2 r01uh0165ej0700 rev.7.00 page 496 of 1113 sep 22, 2011 (2) watchdog timer enable register (wdte) the counter of watchdog timer 2 is cl eared and counting is restarted by wr iting ?ach? to the wdte register. the wdte register can be read or wr itten in 8-bit units. (when a 1-bit memory manipulation instruction is executed on the wdte register, an over flow signal is forcibly generated.) reset sets this register to 9ah. wdte after reset: 9ah r/w address: fffff6d1h cautions 1. when a value other than ?ach? is writ ten to the wdte register , an overflow signal is forcibly output. 2. to intentionally generate an overflow signal, write a value other than ?ach? to the wdte register once, or write data to the wdtm2 register twice. however, when watchdog timer 2 is set to ?stop operation?, an o verflow signal is not generated even if a value other than ?ach? is written to th e wdte register once, or data is written to the wdtm2 register twice. 3. the read value of the wdte register is ?9ah? (which differs from the written value ?ach?). 12.4 operation watchdog timer 2 automatically starts in the reset mode immediately after a reset. the wdtm2 register can be written to only once immediatel y after a reset using byte access. to use watchdog timer 2, write the operation mode setting and the loop detecti on time interval to the wdtm2 register using an 8-bit memory manipulation instruction. after this, the operation of watchdog ti mer 2 cannot be stopped. the wdcs24 to wdcs20 bits of the wd tm2 register are used to select t he watchdog timer 2 loop detection time interval. writing ach to the wdte register cl ears the counter of watchdog timer 2 and starts the count operation again. after the count operation has start ed, write ach to wdte within the loop detection time interval. if the loop detection time interval expires without ach being written to the wdte register, a reset signal (wdt2res) or a non-maskable interrupt request signal (i ntwdt2) is generated, depending on the values of the wdtm2.wdm21 and wdtm2.wdm20 bits. when the wdtm2.wdm21 bit is set to 1 (reset mode), if watchdog timer 2 overflows during oscillation stabilization immediately after a reset ends or after a st andby is released, no internal reset will occur and the cpu clock will switch to the internal oscillator clock. to not use watchdog timer 2, write 00h to the wdtm2 register. for details of the non-maskable interrupt servicing that occurs when the non-maskable interrupt request mode is set, see 21.2.2 (2) from intwdt2 signal .
v850es/jg3-l chapter 13 real-t ime output function (rto) r01uh0165ej0700 rev.7.00 page 497 of 1113 sep 22, 2011 chapter 13 real-time output function (rto) 13.1 function the real-time output function transfers preset data to the real-time outpu t buffer registers (rtbl0 and rtbh0), and then transfers this data by hardware to an external de vice via the output latches, upon occurrence of a timer interrupt. the pins through which the data is output to an external device constitute a port called the real-time output function (rto). because rto can output signals without jitter, it is suitable for controlling a stepper motor. in the v850es/jg3-l, one 6-bit real-t ime output port channel is provided. the real-time output port can be se t to the port mode or real-time output port mode in 1-bit units.
v850es/jg3-l chapter 13 real-t ime output function (rto) r01uh0165ej0700 rev.7.00 page 498 of 1113 sep 22, 2011 13.2 configuration rto includes the following hardware. table 13-1. configuration of rto item configuration registers real-time output buffer registers 0l, 0h (rtbl0, rtbh0) real-time output latches 0h, 0l real-time output port mode register 0 (rtpm0) real-time output port control register 0 (rtpc0) the block diagram of rto is shown below. figure 13-1. block diagram of rto inttp0cc0 inttp5cc0 inttp4cc0 rtpoe0 rtpeg0 byte0 extr0 rtpm05 rtpm04 rtpm03 rtpm02 rtpm01 rtpm00 4 2 2 4 rtp04, rtp05 rtp00 to rtp03 real-time output buffer register 0h (rtbh0) real-time output latch 0h selector real-time output latch 0l real-time output port control register 0 (rtpc0) transfer trigger (h) transfer trigger (l) real-time output port mode register 0 (rtpm0) internal bus real-time output buffer register 0l (rtbl0)
v850es/jg3-l chapter 13 real-t ime output function (rto) r01uh0165ej0700 rev.7.00 page 499 of 1113 sep 22, 2011 (1) real-time output buffer regi sters 0l, 0h (rtbl0, rtbh0) the rtbl0 and rtbh0 registers are 4-bit registers that hold preset output data. these registers are mapped to different addresses in the peripheral i/o register area. these registers can be read or wr itten in 8-bit or 1-bit units. reset sets these registers to 00h. if an operation mode of 4 bits 1 channel or 2 bits 1 channel is specified (rtpc0.byte0 bit = 0), data can be individually set to the rtbl0 and rtbh0 registers. the data of both these registers can be read at once by specifying the address of either of these registers. if an operation mode of 6 bits 1 channel is specified (byte0 bit = 1) , 8-bit data can be set to both the rtbl0 and rtbh0 registers by writing the dat a to either of these registers. moreover, the data of both these registers can be read at once by specifying the address of either of these registers. table 13-2 shows the operation when the rt bl0 and rtbh0 register s are manipulated. 0 rtbl0 rtbh0 0 rtbh05 rtbh04 rtbl03 rtbl02 rtbl01 rtbl00 after reset: 00h r/w address: rtbl0 fffff6e0h, rtbh0 fffff6e2h cautions 1. when writing to bits 6 an d 7 of the rtbh0 register, always set 0. 2. if the rtbl0 and rtbh0 registers are accessed in the fo llowing statuses, a wait will occur. once the system enters th e wait status, the only way to cancel the wait status is to execute a reset . for details, see 3.4.9 (1) accessing special on-chip peripheral i/o registers. ? when the cpu operates with the subclo ck and the main clock oscillation is stopped ? when the cpu operates with th e internal oscillator clock table 13-2. operation during manipul ation of rtbl0 and rtbh0 registers read write note operation mode register to be manipulated higher 4 bits lower 4 bits higher 4 bits lower 4 bits rtbl0 rtbh0 rtbl0 invalid rtbl0 4 bits 1 channel, 2 bits 1 channel rtbh0 rtbh0 rtbl0 rtbh0 invalid rtbl0 rtbh0 rtbl0 rtbh0 rtbl0 6 bits 1 channel rtbh0 rtbh0 rtbl0 rtbh0 rtbl0 note after setting the real-time output port, output data must be set to t he rtbl0 and rtbh0 registers before a real-time output tr igger is generated.
v850es/jg3-l chapter 13 real-t ime output function (rto) r01uh0165ej0700 rev.7.00 page 500 of 1113 sep 22, 2011 13.3 registers rto is controlled using the following two registers. ? real-time output port mode register 0 (rtpm0) ? real-time output port control register 0 (rtpc0) caution in order to use the real-time output pins (rtp00 to rtp05), set these pins as real-time output port pins using the pmc and pfc registers. (1) real-time output port mode register 0 (rtpm0) the rtpm0 register enables the se lection of real-time output port mode or port mode in 1-bit units. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 rtpm0m 0 1 real-time output disabled real-time output enabled control of real-time output port (m = 0 to 5) rtpm0 0 rtpm05 rtpm04 rtpm03 rtpm02 rtpm01 rtpm00 after reset: 00h r/w address: fffff6e4h cautions 1. by enabling the real-time output operation (rtpc0.rtpoe0 bit = 1), the bits enabled to real-time output among th e rtp00 to rtp05 signals perform real-time output, and the bits set to port mode output 0. 2. if real-time output is disabled (rtpoe0 bit = 0), the real-time output pins (rtp00 to rtp05) all output 0, regard less of the rtpm0 register setting. 3. when writing to bits 6 and 7 of the rtpm0 register, always set 0.
v850es/jg3-l chapter 13 real-t ime output function (rto) r01uh0165ej0700 rev.7.00 page 501 of 1113 sep 22, 2011 (2) real-time output port control register 0 (rtpc0) the rtpc0 register is a register that sets the operat ion mode and output trigger of the real-time output port. the relationship between the operation mode and output tri gger of the real-time out put port is as shown in table 13-3. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. rtpoe0 disables operation note 1 enables operation rtpoe0 0 1 control of real-time output operation rtpc0 rtpeg0 byte0 extr0 0 0 0 0 falling edge note 2 rising edge valid edge of inttp0cc0 signal 4 bits 1 channel, 2 bits 1 channel 6 bits 1 channel byte0 0 1 rtpeg0 0 1 specification of channel configuration for real-time output after reset: 00h r/w address: fffff6e5h < > notes 1. when real-time output operation is disabl ed (rtpoe0 bit = 0), all the bits of the real-time output pins (rtp 00 to rtp05) output ?0?. 2. with this setting, the transfer of data bet ween the buffer and the latch will be delayed by one clock cycle. caution set the rtpeg0, byte0, and ext r0 bits only when rtpoe0 bit = 0. table 13-3. operation modes and output triggers of real-time output port byte0 extr0 operation mode rtbh0 (rtp04, rtp05) rtbl0 (rtp00 to rtp03) 0 inttp5cc0 inttp4cc0 0 1 4 bits 1 channel, 2 bits 1 channel inttp4cc0 inttp0cc0 0 inttp4cc0 1 1 6 bits 1 channel inttp0cc0
v850es/jg3-l chapter 13 real-t ime output function (rto) r01uh0165ej0700 rev.7.00 page 502 of 1113 sep 22, 2011 13.4 operation if the real-time output operati on is enabled by setting the rtpc0.rtpoe0 bit to 1, the data of the rtbh0 and rtbl0 registers is transferred to the real-time output latch in synchronizati on with the generation of the selected transfer trigger (set by the rtpc0.ext r0 and rtpc0.byte0 bits). of the tr ansferred data, only the data of the bits for which real-time output is enabled by the rtpm0 register is output from the rtp00 to rtp05 bits. the bits for which real-time output is disabled by the rtpm0 register output 0. if the real-time output operatio n is disabled by clearing the rtpoe0 bit to 0, the rtp00 to rtp05 pins output 0 regardless of the setting of the rtpm0 register. figure 13-2. example of operation timing of rto0 (when extr0 bit = 0, byte0 bit = 0) abababab d01 d02 d03 d04 d11 d12 d13 d14 d11 d12 d13 d14 d01 d02 d03 d04 inttp5cc0 (internal) inttp4cc0 (internal) cpu operation rtbh0 rtbl0 rt output latch 0 (h) rt output latch 0 (l) d00 note d10 note note if the rtbh0 and rtbl0 registers are written when the rtpoe0 bit is 0, the written value is transferred to real-time output latches 0h and 0l, respectively. a: software processing by inttp5cc0 interrupt request (rtbh0 write) b: software processing by inttp4cc0 interrupt request (rtbl0 write) remark for the operation during standby, see chapter 23 standby function .
v850es/jg3-l chapter 13 real-t ime output function (rto) r01uh0165ej0700 rev.7.00 page 503 of 1113 sep 22, 2011 13.5 usage (1) disable real-time output. clear the rtpc0.rtpoe0 bit to 0. (2) perform initialization as follows. ? set the alternate-function pins of port 5 set the pfc5.pfc5m bit and pfce5.pfce5m bit to 1, and then set the pmc5.pmc5m bit to 1 (m = 0 to 5). ? specify the real-time output port mode or port mode in 1-bit units. set the rtpm0 register. ? channel configuration: select the trigger and valid edge. set the rtpc0.extr0, rtpc0. byte0, and rtpc0.rtpeg0 bits. ? set the initial values to the rtbh0 and rtbl0 registers note 1 . (3) enable real-time output. set the rtpoe0 bit = 1. (4) set the next output value to the rtbh0 and rtbl0 re gisters by the time the selected transfer trigger is generated note 2 . (5) set the next real-time output value to the rtbh0 and rtbl0 registers via interrupt servicing corresponding to the selected trigger. notes 1. if the rtbh0 and rtbl0 registers are written when the rtpoe0 bit is 0, the written value is transferred to real-time output latches 0h and 0l, respectively. 2. even if the rtbh0 and rtbl0 registers are wr itten when the rtpoe0 bit = 1, data is not transferred to real-time output latches 0h and 0l. caution to apply the above settings to the real-time output pins (rtp00 to rtp05), set the real-time output pins by using the pmc5 and pfc5 registers. 13.6 cautions (1) prevent the following conflicts by using software, such as by writing to the rtbl0, rtbh0, and rtpc0 registers inside the interrupt servicing routin e of the selected real-time output trigger. ? conflict between real-time output disable/enable sw itching (rtpoe0 bit) and selected real-time output trigger. ? conflict between writing to the rtbh0 and rtbl0 regist ers in the real-time output enabled status and the selected real-time output trigger. (2) before performing initialization, disable real-time output (rtpoe0 bit = 0). (3) once real-time output has been disabled (rtpoe0 bi t = 0), be sure to initialize the rtbh0 and rtbl0 registers before enabling real-time output again (rtpoe0 bit = 0 1).
v850es/jg3-l chapter 14 a/d converter r01uh0165ej0700 rev.7.00 page 504 of 1113 sep 22, 2011 chapter 14 a/d converter 14.1 overview the a/d converter converts analog input signals into digital values, has a resolution of 10 bits, and can handle 12 analog input signal channels (ani0 to ani11). the a/d converter has the following features. { 10-bit resolution { 12 channels { successive approximation method { operating voltage: av ref0 = 2.7 to 3.6 v { analog input voltage: 0 v to av ref0 { the following functions are provided as operation modes. ? continuous select mode ? continuous scan mode ? one-shot select mode ? one-shot scan mode { the following functions are provided as trigger modes. ? software trigger mode ? external trigger mode (external, 1) ? timer trigger mode { conversion time 2.6 to 24 s@3.0 v av ref0 3.6 v 3.9 to 24 s@2.7 v av ref0 < 3.0 v { power-fail monitor function (conversion result compare function) 14.2 functions (1) 10-bit resolution a/d conversion a/d conversion is repeated at a resolution of 10 bits fo r an analog signal that is input to a channel selected from ani0 to ani11. each time a/d conversion is completed, an interrupt request signal (intad) is generated. (2) power-fail detection this function is used to detect a drop in the battery volt age. the result of a/d conversion (the value of the ada0crnh register) is compared with the value of th e ada0pft register, and the intad signal is generated only when the comparison condition specified by the ada0pfm register is satisfied (n = 0 to 11).
v850es/jg3-l chapter 14 a/d converter r01uh0165ej0700 rev.7.00 page 505 of 1113 sep 22, 2011 14.3 configuration the a/d converter includes the following hardware. table 14-1. configuration of a/d converter item configuration analog inputs 12 channels (ani0 to ani11 pins) registers successive approximation register (sar) a/d conversion result registers 0 to 11 (ada0cr0 to ada0cr11) a/d conversion result registers 0h to 11h (adcr0 h to adcr11h): only higher 8 bits can be read a/d converter mode registers 0 to 2 (ada0m0 to ada0m2) a/d converter channel specification register 0 (ada0s) power fail compare mode register (ada0pfm) power fail compare threshold value register (ada0pft) the block diagram of the a/d converter is shown below. figure 14-1. block diagram of a/d converter ani0 : : ani1 ani2 ani9 ani10 ani11 ada0m2 ada0m1 ada0m0 ada0s ada0pft controller comparator ada0pfm ada0cr0 ada0cr1 : : ada0cr2 ada0cr10 ada0cr11 internal bus av ref0 ada0ce bit av ss intad edge detection adtrg controller sample & hold circuit ada0ets0 bit inttp2cc0 inttp2cc1 ada0ets1 bit ada0ce bit ada0tmd1 bit ada0tmd0 bit selector selector ada0pfe bit ada0pfc bit sar voltage comparator & compare voltage generation dac
v850es/jg3-l chapter 14 a/d converter r01uh0165ej0700 rev.7.00 page 506 of 1113 sep 22, 2011 (1) ani0 to ani11 pins these are analog input pins for the 12 a/d converter channels and are used to input analog signals to be converted into digital signals. pins other than the o nes selected as analog input pins by the ada0s register can be used as i/o port pins. caution make sure that the voltages input to the ani0 to ani11 pins do not exceed the rated values. in particular if a voltage of av ref0 or higher is input to a channel, the conversion value of that channel becomes undefined, and the conversion values of the other channels may also be affected. (2) sample & hold circuit the sample & hold circuit samples each of the analog input signals selected by the input circuit and sends the sampled data to the voltage comparator. this circuit also holds the sampled analog input signal voltage during a/d conversion. (3) compare voltage generation dac the compare voltage generation dac is connected between av ref0 and av ss and generates the voltage to be compared with the value that was sampled and held by the sample & hold circuit. (4) voltage comparator the voltage comparator compares the voltage value that was sampled and held with the output voltage of the compare voltage generation dac. (5) successive approximation register (sar) this register compares the voltage of the sampled analog input signal wit h the output voltag e of the compare voltage generation dac (compare voltage), and sequentially retains the comparison result bit by bit starting from the most significant bit (msb). when the comparison result has been held down to th e least significant bit (lsb) (that is, when a/d conversion is complete), the contents of the sar r egister are transferred to the ada0crn register. remark n = 0 to 11 (6) 10-bit ad conversion result register n (ada0crn) the ada0crn register is a 16-bit re gister that stores the a/d conversi on result. ada0arn consist of 12 registers and the a/d conversion result is stored in the 10 higher bits of the ad0crn register corresponding to analog input. (the lower 6 bits are fixed to 0.) (7) a/d conversion result register nh (ada0crnh) this is a 8-bit register that stores the a/d conversion result. ada0crn h consists of 12 registers and the a/d conversion result is stored in the hi gher 8 bits of the ada0crnh register corresponding to the analog input signal. (8) a/d converter mode register 0 (ada0m0) this register specifies the operation mode a nd controls conversion by the a/d converter. (9) a/d converter mode register 1 (ada0m1) this register specifies the time required to convert an analog input signal to a digital signal.
v850es/jg3-l chapter 14 a/d converter r01uh0165ej0700 rev.7.00 page 507 of 1113 sep 22, 2011 (10) a/d converter mode register 2 (ada0m2) this register specifies the hardware trigger mode. (11) a/d converter channel sp ecification register (ada0s) this register specifies the pin to which t he analog voltage to be converted is input. (12) power-fail compare mode register (ada0pfm) this register controls power-fail monitoring. (13) power-fail compare thres hold value register (ada0pft) the ada0pft register sets the threshold value that is compared with the value of a/d conversion result register nh (ada0crnh). the 8-bit data set to the ada0 pft register is compared wi th the higher 8 bits of the a/d conversion result register (ada0crnh). (14) controller the controller compares the result of a/d conversion (the value of the ada0crnh register) with the value of the ada0pft register when a/d conv ersion is completed or when the po wer-fail detection function is used, and generates the intad signal only when the specified comparison condition is satisfied. (15) av ref0 pin this is the pin used to input the refe rence voltage of the a/d converter. always make the potential of this pin the same as that of the v dd pin even when the a/d converter is not used. the signals input to the ani0 to ani11 pins are converted to digital si gnals based on the voltage applied between the av ref0 and av ss pins. (16) av ss pin this is the ground pin of the a/d conv erter. always make the potential of this pin the same as that of the v ss pin even when the a/d converter is not used.
v850es/jg3-l chapter 14 a/d converter r01uh0165ej0700 rev.7.00 page 508 of 1113 sep 22, 2011 14.4 registers the a/d converter is controlled by the following registers. ? a/d converter mode registers 0, 1, 2 (ada0m0, ada0m1, ada0m2) ? a/d converter channel specification register 0 (ada0s) ? power-fail compare mode register (ada0pfm) the following registers are also used. ? a/d conversion result register n (ada0crn) ? a/d conversion result register nh (ada0crnh) ? power-fail compare threshold value register (ada0pft) (1) a/d converter mode register 0 (ada0m0) the ada0m0 register is an 8-bit register that s pecifies the operation mode and controls conversion. this register can be read or written in 8-bit or 1-bit units. however, the ada0ef bit is read-only. reset sets this register to 00h. caution accessing the ada0m0 register is prohibited in the following statuses. if a wait cycle is generated, it can be cleared only by a reset. for details, see 4.4.9 (1) accessing special on-chip peripheral i/o registers. ? when the cpu operates on the subclock and main clock oscillation is stopped ? when the cpu operates on th e internal oscillator clock (1/2) ada0ce ada0ce 0 1 stops a/d conversion enables a/d conversion a/d conversion control ada0m0 0 ada0md1 ada0md0 ada0ets1 ada0ets0 ada0tmd ada0ef ada0md1 0 0 1 1 ada0md0 0 1 0 1 continuous select mode continuous scan mode one-shot select mode one-shot scan mode specification of a/d converter operation mode after reset: 00h r/w address: fffff200h < > < >
v850es/jg3-l chapter 14 a/d converter r01uh0165ej0700 rev.7.00 page 509 of 1113 sep 22, 2011 (2/2) ada0tmd 0 1 software trigger mode external trigger mode/timer trigger mode trigger mode selection ada0ef 0 1 a/d conversion stopped a/d conversion in progress a/d converter status display ada0ets1 0 0 1 1 ada0ets0 0 1 0 1 no edge detection falling edge detection rising edge detection detection of both rising and falling edges specification of external trigger (adtrg pin) input valid edge cautions 1. a write operation to bit 0 is ignored. 2. changing the ada0m1.ada0fr2 to ada0 m1.ada0fr0 bits is prohibited while a/d conversion is enabled (ada0ce bit = 1). 3. in the following modes, write data to the ada0m0, ada0m2, ada0s, ada0pfm, or ada0pft registers while a/d conversion is st opped (ada0ce bit = 0), and then enable a/d conversion (ada0ce bit = 1). ? normal conversion mode ? one-shot select mode/one-shot scan mode in high-speed conversion mode if the ada0m0, ada0m2, ada0s, ada0pfm, and ada0pft registers are written in other modes during a/d conversion (ada0ef bi t = 1), the following will be performed, according to the mode. ? in software trigger mode a/d conversion is stopped and started again from the beginning. ? in hardware trigger mode a/d conversion is stopped, and the trigger standby status is set. 4. to select the external trigger mode/tim er trigger mode (ada0tmd bit = 1), set the high-speed conversion mode (ada0m1.ada0hs 1 bit = 1). do not input a trigger during the stabilization time that is inser ted once after a/d conversion is enabled (ada0ce bit = 1). 5. when not using the a/d converter, stop a/d conversion by setting the ada0ce bit to 0 to reduce power consumption.
v850es/jg3-l chapter 14 a/d converter r01uh0165ej0700 rev.7.00 page 510 of 1113 sep 22, 2011 (2) a/d converter mode register 1 (ada0m1) the ada0m1 register is an 8-bit regist er that specifies the conversion time. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. ada0hs1 ada0m1 0 00 0 ada0fr2 ada0fr1 ada0fr0 after reset: 00h r/w address: fffff201h ada0hs1 0 1 normal conversion mode high-speed conversion mode normal conversion mode/high-speed mode (a/d conversion time) selection cautions 1. changing the ada0m1 register is prohibited while a/d conversion is enabled (ada0m0.ada0ce bit = 1). 2. when selecting the external trigger m ode/timer trigger mode (ada0m0.ada0tmd bit = 1), set the high-speed conversion mode (ada0 hs1 bit = 1). do not input a trigger during the stabilization time that is inser ted once after a/d conversion is enabled (ada0ce bit = 1). 3. be sure to clear bits 6 to 3 to ?0?. remark for a/d conversion time setting examples, see tables 14-2 and 14-3 .
v850es/jg3-l chapter 14 a/d converter r01uh0165ej0700 rev.7.00 page 511 of 1113 sep 22, 2011 examples of the conversion time for each clock are shown below. table 14-2. conversion time selection in normal conversion mode (ada0hs1 bit = 0) a/d conversion time ada0 fr2 ada0 fr1 ada0 fr0 stabilization time + conversion time + wait time f xx = 20 mhz f xx = 16 mhz f xx = 12 mhz f xx = 10 mhz f xx = 4 mhz trigger response time 0 0 0 66/f xx (13/f xx + 26/f xx + 27/f xx ) setting prohibited setting prohibited setting prohibited 6.6 s note 16.5 s 3/f xx 0 0 1 131/f xx (26/f xx + 52/f xx + 53/f xx ) 6.55 s note 8.19 s note 10.92 s 13.1 s setting prohibited 3/f xx 0 1 0 196/f xx (39/f xx + 78/f xx + 79/f xx ) 9.8 s 12.25 s 16.33 s 19.6 s setting prohibited 3/f xx 0 1 1 259/f xx (50/f xx + 104/f xx + 105/f xx ) 12.95 s 16.19 s 21.58 s setting prohibited setting prohibited 3/f xx 1 0 0 311/f xx (50/f xx + 130/f xx + 131/f xx ) 15.55 s 19.44 s setting prohibited setting prohibited setting prohibited 3/f xx 1 0 1 363/f xx (50/f xx + 156/f xx + 157/f xx ) 18.15 s 22.69 s setting prohibited setting prohibited setting prohibited 3/f xx 1 1 0 415/f xx (50/f xx + 182/f xx + 183/f xx ) 20.75 s setting prohibited setting prohibited setting prohibited setting prohibited 3/f xx 1 1 1 467/f xx (50/f xx + 208/f xx + 209/f xx ) 23.35 s setting prohibited setting prohibited setting prohibited setting prohibited 3/f xx other than above setting prohibited note setting prohibited when 2.7 v av ref0 < 3.0 v remarks 1. stabilization time: a/d converter setup time (1 s or longer) conversion time: actual a/d conversion time (2.6 to 10.4 s) wait time: wait time inserted before the next conversion trigger response time: if a software trigger is ge nerated after the stabilization time, it is inserted before the conversion time. 2. for details about the operation timing, see 14.5.2 conversion operation timing . in the normal conversion mode, conversion is star ted after the stabilization time has elapsed after the ada0m0.ada0ce bit is set to 1, and a/d conversion is performed only during the specified conversion time (2.6 to 10.4 s). conversion stops after the c onversion ends and the a/d conversion end interrupt request signal (intad) is generated after the wait time has elapsed. because conversion is stopped during the wa it time, the operating current can be reduced. cautions 1. set as 2.6 s conversion time 10.4 s when 3.0 v av ref0 3.6 v. set as 3.9 s conversion time 10.4 s when 2.7 v av ref0 < 3.0 v . 2. during a/d conversion, if th e ada0m0, ada0m2, ada0s, ada0pfm, and ada0pft registers are written or a trigger is input, reconversion is carried out. however, if the stabilization time end timing conflicts with writing to these registers, or if the stabilization time en d timing conflicts with the trigger input, the stabilization time of 64 clocks is reinserted. if a conflict occurs again with the rein serted stabilization time end timing, the stabilization time is reinserted. therefo re do not set the trigger input interval and control register write inte rval to 64 clocks or lower.
v850es/jg3-l chapter 14 a/d converter r01uh0165ej0700 rev.7.00 page 512 of 1113 sep 22, 2011 table 14-3. conversion time selection in hi gh-speed conversion mode (ada0hs1 bit = 1) a/d conversion time ada0 fr2 ada0 fr1 ada0 fr0 conversion time (+ stabilization time) f xx = 20 mhz f xx = 16 mhz f xx = 12 mhz f xx = 10 mhz f xx = 4 mhz trigger response time 0 0 0 26/f xx (+ 13/f xx ) setting prohibited setting prohibited setting prohibited 2.6 s note (+ 1.3 s) 6.5 s (+ 3.25 s) 3/f xx 0 0 1 52/f xx (+ 26/f xx ) 2.6 s note (+ 1.3 s) 3.25 s note (+ 1.625 s ) 4.333 s (+ 2.167 s ) 5.2 s (+ 2.6 s) setting prohibited 3/f xx 0 1 0 78/f xx (+ 39/f xx ) 3.9 s (+ 1.95 s) 4.875 s (+ 2.438 s ) 6.5 s (+ 3.25 s) 7.8 s (+ 3.9 s) setting prohibited 3/f xx 0 1 1 104/f xx (+ 50/f xx ) 5.2 s (+ 2.5 s) 6.5 s (+ 3.125 s ) 8.667 s (+ 4.167 s ) 10.4 s (+ 5 s) setting prohibited 3/f xx 1 0 0 130/f xx (+ 50/f xx ) 6.5 s (+ 2.5 s) 8.125 s (+ 3.125 s ) setting prohibited setting prohibited setting prohibited 3/f xx 1 0 1 156/f xx (+ 50/f xx ) 7.8 s (+ 2.5 s) 9.75 s (+ 3.125 s ) setting prohibited setting prohibited setting prohibited 3/f xx 1 1 0 182/f xx (+ 50/f xx ) 9.1 s (+ 2.5 s) setting prohibited setting prohibited setting prohibited setting prohibited 3/f xx 1 1 1 208/f xx (+ 50/f xx ) 10.4 s (+ 2.5 s) setting prohibited setting prohibited setting prohibited setting prohibited 3/f xx other than above setting prohibited note setting prohibited when 2.7 v av ref0 < 3.0 v remarks 1. conversion time: actual a/d conversion time (2.6 to 10.4 s) stabilization time: a/d converter setup time (1 s or longer) trigger response time: if a software trigger, exter nal trigger, or timer trigger is generated after the stabilization time, it is inserted before the conversion time. 2. for details about the operation timing, see 14.5.2 conversion operation timing . in the high-speed conversion mode, conversion is st arted after the stabilization time has elapsed after the ada0m0.ada0ce bit is set to 1, and a/d conv ersion is performed only during the specified conversion time (2.6 to 10.4 s). the a/d conversion end inte rrupt request signal (intad) is generated immediately after conversion ends. in continuous conversion mode, the stabilization time is inserted only before the first conversion, and is not inserted after the second conversion (the a/d converter continues running). cautions 1. set as 2.6 s conversion time 10.4 s when 3.0 v av ref0 3.6 v. set as 3.9 s conversion time 10.4 s when 2.7 v av ref0 < 3.0 v. 2. in the high-speed conversion mode , rewriting the ada0m0, ada0m2, ada0s, ada0pfm, and ada0pft registers and inputti ng a trigger are prohibited during the stabilization time.
v850es/jg3-l chapter 14 a/d converter r01uh0165ej0700 rev.7.00 page 513 of 1113 sep 22, 2011 (3) a/d converter mode register 2 (ada0m2) the ada0m2 register specifies the hardware trigger mode. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 ada0m2 0 0 0 00 ada0tmd1 ada0tmd0 ada0tmd1 0 0 1 1 ada0tmd0 0 1 0 1 specification of hardware trigger mode external trigger mode (when adtrg pin valid edge is detected) timer trigger mode 0 (when inttp2cc0 interrupt request is generated) timer trigger mode 1 (when inttp2cc1 interrupt request is generated) setting prohibited after reset: 00h r/w address: fffff203h 6543210 7 cautions 1. in the follo wing modes, write data to the ada0m2 register while a/d conversion is stopped (ada0m0.ada0ce bit = 0), and then enable a/d conversion (ada0ce bit = 1). ? normal conversion mode ? one-shot select mode/one-shot scan mode in high-speed conversion mode 2. be sure to clear bits 7 to 2 to ?0?.
v850es/jg3-l chapter 14 a/d converter r01uh0165ej0700 rev.7.00 page 514 of 1113 sep 22, 2011 (4) analog input channel specification register 0 (ada0s) the ada0s register specifies the pin that inputs the analog voltage to be converted into a digital signal. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 ada0s 0 0 0 ada0s3 ada0s2 ada0s1 ada0s0 after reset: 00h r/w address: fffff202h ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 ani8 ani9 ani10 ani11 setting prohibited setting prohibited setting prohibited setting prohibited ani0 ani0, ani1 ani0 to ani2 ani0 to ani3 ani0 to ani4 ani0 to ani5 ani0 to ani6 ani0 to ani7 ani0 to ani8 ani0 to ani9 ani0 to ani10 ani0 to ani11 setting prohibited setting prohibited setting prohibited setting prohibited ada0s3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ada0s2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ada0s1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ada0s0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 select mode scan mode cautions 1. in the following m odes, write data to the ada0s re gister while a/d conversion is stopped (ada0m0.ada0ce bit = 0), and then enable a/d conversion (ada0ce bit = 1). ? normal conversion mode ? one-shot select mode/one-shot scan mode in high-speed conversion mode 2. be sure to clear bits 7 to 4 to ?0?.
v850es/jg3-l chapter 14 a/d converter r01uh0165ej0700 rev.7.00 page 515 of 1113 sep 22, 2011 (5) a/d conversion result regi sters n, nh (ada0crn, ada0crnh) the ada0crn and ada0crnh registers store the a/d conversion results. these registers are read-only, in 16-bit or 8-bit unit s. however, specify the ada0crn register for 16-bit access and the ada0crnh register for 8-bit access. for ada0crn, the 10 bits of the conversion result are read from the higher 10 bits, and 0 is read from the lower 6 bits. for ada0crnh, the higher 8 bits of the conversion result are read. caution accessing the ada0crn and ada0crnh registers is prohibited in the following statuses. if a wait cycle is generated, it can be cleared only by a reset. for details, see 3.4.9 (1) accessing special on-ch ip peripheral i/o registers. ? when the cpu operates on the subclock a nd main clock oscillation is stopped ? when the cpu operates on th e internal oscillator clock after reset: undefined r address: ada0cr0 fffff210h, ada0cr1 fffff212h, ada0cr2 fffff214h, ada0cr3 fffff216h, ada0cr4 fffff218h, ada0cr5 fffff21ah, ada0cr6 fffff21ch, ada0cr7 fffff21eh, ada0cr8 fffff220h, ada0cr9 fffff222h, ada0cr10 fffff224h, ada0cr11 fffff226h ada0crn (n = 0 to 11) ad9 ad8 ad7 ad6 ad0000000 ad1 ad2 ad3 ad4 ad5 ad9 ada0crnh (n = 0 to 11) ad8 ad7 ad6 ad5 ad4 ad3 ad2 76 54 32 1 0 after reset: undefined r address: ada0cr0h fffff211h, ada0cr1h fffff213h, ada0cr2h fffff215h, ada0cr3h fffff217h, ada0cr4h fffff219h, ada0cr5h fffff21bh, ada0cr6h fffff21dh, ada0cr7h fffff21fh, ada0cr8h fffff221h, ada0cr9h fffff223h, ada0cr10h fffff225h, ada0cr11h fffff227h caution a write operation to the ada0m0 and ada0s registers may cause the contents of the ada0crn register to become undefined. after conversion, read the conversion result before writing to the ada0m0 and ada0s registers. correct conversion results may not be read if a sequence other than the above is used.
v850es/jg3-l chapter 14 a/d converter r01uh0165ej0700 rev.7.00 page 516 of 1113 sep 22, 2011 the relationship between the analog volta ge input to the analog input pins (a ni0 to ani11) and the a/d conversion result (ada0crn register) is as follows. v in sar = int ( av ref0 1,024 + 0.5) ada0cr note = sar 64 or, av ref0 av ref0 (sar ? 0.5) 1,024 v in < (sar + 0.5) 1,024 int( ): function that returns the integer of the value in ( ) v in : analog input voltage av ref0 : av ref0 pin voltage ada0cr: value of ada0crn register note the lower 6 bits of the ada0crn register are fixed to 0. the following shows the relationship between the analo g input voltage and the a/d conversion results. figure 14-2. relationship between analog input voltage and a/d conversion results 1,023 1,022 1,021 3 2 1 0 input voltage/av ref0 1 2,048 1 1,024 3 2,048 2 1,024 5 2,048 3 1,024 2,043 2,048 1,022 1,024 2,045 2,048 1,023 1,024 2,047 2,048 1 a/d conversion results ada0crn sar ffc0h ff80h ff40h 00c0h 0080h 0040h 0000h
v850es/jg3-l chapter 14 a/d converter r01uh0165ej0700 rev.7.00 page 517 of 1113 sep 22, 2011 (6) power-fail compare m ode register (ada0pfm) the ada0pfm register is an 8-bit register that sets the power-fail compare mode. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. ada0pfe power-fail compare disabled power-fail compare enabled ada0pfe 0 1 selection of power-fail compare enable/disable ada0pfm ada0pfc 00 00 0 0 generate an interrupt request signal (intad) when ada0crnh ada0pft generate an interrupt request signal (intad) when ada0crnh < ada0pft ada0pfc 0 1 selection of power-fail compare mode after reset: 00h r/w address: fffff204h <7>6543210 cautions 1. in the select mode, the 8-bit data set to the ada0pft register is compared with the conversion result of the ch annel specified by the ada0s register. if the result matches the condition specified by the ada0pf c bit, the conversion result is stored in the ada0crn register and the intad signal is generated. if it does not match, the conversion result is stored in the ada0cr0 register and the intad signal is not generated. 2. in the scan mode, the 8-bit data set to the ada0pft register is compared with the conversion result of channel 0. if the r esult matches the condition specified by the ada0pfc bit, the conversion result is stor ed in the ada0cr0 register and the intad signal is generated. if it does not match, the conversion result is stored in the ada0cr0 register but the intad signal is not generated. also, regardless of the comparison result, scanning c ontinues after comparison and the conversion result continue to be stored in the ada0crn register until scanning ends. however, the intad signal is not generated a fter the scanning has finished. 3. in the following modes, write data to the ada0pfm register while a/d conversion is stopped (ada0m0.ada0ce bit = 0), and then enable a/d conversion (ada0ce bit = 1). ? normal conversion mode ? one-shot select mode/one-shot scan mode in high-speed conversion mode
v850es/jg3-l chapter 14 a/d converter r01uh0165ej0700 rev.7.00 page 518 of 1113 sep 22, 2011 (7) power-fail compare thres hold value register (ada0pft) the ada0pft register sets the compare value in the power-fail compare mode. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. ada0pft after reset: 00h r/w address: fffff205h 76 54 321 0 caution in the following modes, write data to the ada0pft register while a/d conversion is stopped (ada0m0.ada0ce bit = 0), and then enable a/d conversion (ada0ce bit = 1). ? normal conversion mode ? one-shot select mode/one-shot scan m ode in high-speed conversion mode
v850es/jg3-l chapter 14 a/d converter r01uh0165ej0700 rev.7.00 page 519 of 1113 sep 22, 2011 14.5 operation 14.5.1 basic operation <1> set the operation mode, trigger mode, and conversi on time for executing a/d conversion by using the ada0m0, ada0m1, ada0m2, and ada0s registers. when the ada0ce bit of the ada0m0 register is set, conversion is started in the software trigger mode and the a/d converter wait s for a trigger in the external or timer trigger mode. <2> when a/d conversion is started, t he voltage input to the selected anal og input channel is sampled by the sample & hold circuit. <3> once the sample & hold circuit has sampled the input channel for a specific time , it enters the hold status, and holds the input analog voltage until a/d conversion is complete. <4> set bit 9 of the successive approximation regi ster (sar). the tap selector selects (1/2) av ref0 as the compare voltage generation dac. <5> the voltage difference between the voltage of the compare voltage generation dac and the analog input voltage is compared by the volt age comparator. if the analog input voltage is higher than (1/2) av ref0 , the msb of the sar register remains set (1). if it is lower than (1/2) av ref0 , the msb is reset. <6> next, bit 8 of the sar register is automatically set and the next comparison is started. depending on the value of bit 9, to which a result has been already se t, the voltage tap of the compare voltage generation dac is selected as follows. ? bit 9 = 1: (3/4) av ref0 ? bit 9 = 0: (1/4) av ref0 this compare voltage and the analog input voltage are compared and, depending on the result, bit 8 is manipulated as follows. analog input voltage compare voltage: bit 8 = 1 analog input voltage compare voltage: bit 8 = 0 <7> this comparison is continued to bit 0 of the sar register. <8> when comparison of the 10 bits is complete, the valid di gital result is stored in the sar register, and is then transferred to and stored in the ada0crn register. after that, an a/d conversion end interrupt request signal (intad) is generated at the following timing. ? continuous/one-shot select mode: afte r the fist a/d conversion is complete ? continuous/one-shot scan mode: after a/d conversions are performed sequentially for analog input pins up to the one specified by the ada0s register <9> in one-shot select mode, conversion stops here note . in one-shot scan mode, conversion stops after scanning once note . in continuous select mode, repeat steps <2> to <8> until the ada0m0.ada0ce bit is cleared to 0. in continuous scan mode, repeat steps <2> to <8> for each channel. note in the external trigger mode, timer trigger m ode 0, or timer trigger m ode 1, the trigger standby status is entered. remark the trigger standby status me ans the status after the st abilization time has passed.
v850es/jg3-l chapter 14 a/d converter r01uh0165ej0700 rev.7.00 page 520 of 1113 sep 22, 2011 14.5.2 conversion timing figure 14-3. conversion timing (continuous conversion) (1) operation in normal conversion mode (ada0hs1 bit = 0) ada0m0.ada0ce bit processing state setup stabilization time conversion time wait time sampling first conversion second conversion setup sampling wait a/d conversion intad signal 2/f xx (max.) 0.5/f xx sampling time (2) operation in high-speed con version mode (ada0hs1 bit = 1) ada0m0.ada0ce bit processing state setup conversion time sampling first conversion second conversion sampling a/d conversion a/d conversion intad signal 0.5/f xx stabilization time 2/f xx (max.) sampling time ada0fr2 to ada0fr0 bits stabilization time conversion time (sampling time) wait time trigger response time 000 13/f xx 26/f xx (8/f xx ) 27/f xx 3/f xx 001 26/f xx 52/f xx (16/f xx ) 53/f xx 3/f xx 010 39/f xx 78/f xx (24/f xx ) 79/f xx 3/f xx 011 50/f xx 104/f xx (32/f xx ) 105/f xx 3/f xx 100 50/f xx 130/f xx (40/f xx ) 131/f xx 3/f xx 101 50/f xx 156/f xx (48/f xx ) 157/f xx 3/f xx 110 50/f xx 182/f xx (56/f xx ) 183/f xx 3/f xx 111 50/f xx 208/f xx (64/f xx ) 209/f xx 3/f xx remark the above timings apply to the software trigger mode. in the external trigger mode/timer trigger mode, a trigger response time is inserted.
v850es/jg3-l chapter 14 a/d converter r01uh0165ej0700 rev.7.00 page 521 of 1113 sep 22, 2011 14.5.3 trigger modes the timing of starting conversion is specified by setting a trigger mode. the trigger modes include a software trigger mode and hardware trigger mode s. the hardware trigger modes incl ude timer trigger modes 0 and 1, and external trigger mode. the ada0m0.ada0tmd bit is us ed to set the trigger mode. the hardware trigger modes are set by the ada0m2.ada0tmd1 and ada0m2.ada0tmd0 bits. table 14-4. trigger modes ada0m0 register ada0m2 register ada0tmd bit ada0tmd1 bit ada0tmd0 bit trigger mode 0 ? ? software trigger mode 0 0 external trigger mode (based on adtrg pin valid edge detection) 0 1 timer trigger mode 0 (based on inttp2cc0 interrupt request occurrence) 1 0 timer trigger mode 1 (based on inttp2cc1 interrupt request occurrence) 1 1 1 setting prohibited (1) software trigger mode when the ada0m0.ada0ce bit is set to 1, the signal of the analog input pin (anin pin) specified by the ada0s register is converted. when conversion is comp lete, the result is stored in the ada0crn register. at the same time, the a/d conversion end interrupt request signal (intad) is generated. if the operation mode specified by the ada0m0.ada0m d1 and ada0m0.ada0md0 bits is the continuous select/scan mode, the next conversion is started, unless the ada0ce bit is cleared to 0 after completion of the first conversion. conversion is performed once and e nds if the operation mode is the one-shot select/scan mode. when conversion is started, the ada0m0.ada0ef bit is set to 1 (indicating that conversion is in progress). if the ada0m0, ada0m2, ada0s, ada0pfm, or ada0 pft register is written during conversion, the conversion is aborted and started again from the beginning. however, writi ng to these registers is prohibited in the normal conversion mode and one-shot select mode/one-shot scan mode in the high-speed conversion mode (n = 0 to 11). (2) external trigger mode in this mode, converting the signal of the analog input pin (anin pin) specified by the ada0s register is started when an external trigger is input (to the adtr g pin). which edge of the external trigger is to be detected (that is, the rising edge, falling edge, or both rising and falling edges) can be specified by using the ada0m0.ada0ets1 and ada0m0.ata0ets0 bits. when the ada0ce bit is set to 1, the a/d converter waits for the trigger, and starts conversion after the external trigger has been input. when conversion is completed, the result of conversi on is stored in the ada0crn register, regardless of whether the continuous select, cont inuous scan, one-shot select, or one-shot scan mode is set as the operation mode by the ada0md1 and ada0md0 bits. at the same time, the intad signal is generated, and the a/d converter waits for the trigger again. when conversion is started, the ada0ef bit is set to 1 (indicating that conversion is in progress). while the a/d converter is waiting for the trigger, however, the ada0ef bit is cleared to 0 (indicating that conversion is stopped). if a valid trigger is input during conversion, the conversion is aborted and started again from the beginning. if the ada0m0, ada0m2, ada0s, ada0pfm, or ada0 pft register is written during conversion, the conversion is aborted, and the a/d converter waits for th e trigger again. however, writing to these registers is prohibited in the one-shot select mo de/one-shot scan mode (n = 0 to 11).
v850es/jg3-l chapter 14 a/d converter r01uh0165ej0700 rev.7.00 page 522 of 1113 sep 22, 2011 caution when selecting the external trigger mode , set the high-speed conversion mode. do not input a trigger during the stabilization time th at is inserted once after a/d conversion is enabled (ada0m0.ada0ce bit = 1). remark the trigger standby status means the status after the st abilization time has passed. (3) timer trigger mode in this mode, converting the signal of the analog input pi n (ani0 to ani11) specified by the ada0s register is started by the compare match interrupt request signa l (inttp2cc0 or inttp2cc1 ) of the capture/compare register connected to the timer. the inttp2cc0 or inttp2cc1 signal is selected by the ada0tmd1 and ada0tmd0 bits, and conversion is started at the rising edge of the specified compar e match interrupt request signal. when the ada0ce bit is set to 1, the a/d converter waits for a trigger, and starts conversion when the compare match interrupt request signal of the timer is input. when conversion is completed, regardless of whethe r the continuous select, continuous scan, one-shot select, or one-shot scan mode is set as the operation mode by the ada0md1 and ada0md0 bits, the result of the conversion is stored in the ada0crn register. at the same time, the intad signal is generated, and the a/d converter waits for the trigger again. when conversion is started, the ada0ef bit is set to 1 (indicating that conversion is in progress). while the a/d converter is waiting for the trigger, however, the ada0ef bit is cleared to 0 (indicating that conversion is stopped). if a valid trigger is input during conversion, the conversion is aborted and started again from the beginning. if the ada0m0, ada0m2, ada0s, ada0pfm, or ada0 pft register is written during conversion, the conversion is stopped and the a/d converter waits for the trigger again. however, writing to these registers is prohibited in the one-shot select mode/one-shot scan mode. caution when selecting the timer trigger mode, set the high-speed conversion mode. do not input a trigger during the stabilizati on time that is inserted once a fter a/d conversion is enabled (ada0m0.ada0ce bit = 1). remark the trigger standby status means the status after the st abilization time has passed.
v850es/jg3-l chapter 14 a/d converter r01uh0165ej0700 rev.7.00 page 523 of 1113 sep 22, 2011 14.5.4 operation mode four operation modes are av ailable: continuous select mode, continuous scan mode, one-shot select mode, and one-shot scan mode. the operation mode is selected by the ad a0m0.ada0md1 and ada0m0.ada0md0 bits. (1) continuous select mode in this mode, the voltage of one analog input pin sele cted by the ada0s register is continuously converted into a digital value. the conversion result is stored in the ada0crn regist er corresponding to the analog input pin. each time a/d conversion is completed, the a/d conversion end interrupt request signal (intad) is generated. after completion of conversion, the next conversion is star ted, unless the ada0m0.ada0ce bit is cleared to 0 (n = 0 to 11). figure 14-4. example of timing in continuous select mode (ada0s register = 01h) ani1 a/d conversion data 1 (ani1) data 2 (ani1) data 3 (ani1) data 4 (ani1) data 5 (ani1) data 1 data 2 data 3 data 4 data 5 data 1 (ani1) data 2 (ani1) data 3 (ani1) data 4 (ani1) ada0cr1 intad conversion start set ada0ce bit to 1 conversion end set ada0ce bit to 0 remark the above timing applies to the software tri gger mode (ada0m0.ad0tmd bit = 0) or the high-speed conversion mode (ada0m1.ada0hs1 bit = 1). (2) continuous scan mode in this mode, analog input pins are sequentially selected , from the ani0 pin to the pin specified by the ada0s register, and their values are converted into digital values. the result of each conversion is st ored in the ada0crn register corresponding to the analog input pin. when conversion of the analog input pin specified by the ada0s register is complete, the intad signal is generated, and a/d conversion is started again from the an i0 pin, unless the ada0ce bit is cleared to 0 (n = 0 to 11).
v850es/jg3-l chapter 14 a/d converter r01uh0165ej0700 rev.7.00 page 524 of 1113 sep 22, 2011 figure 14-5. example of timing in continuous scan mode (ada0s register = 03h) (1/2) (a) timing example a/d conversion data 1 (ani0) data 2 (ani1) data 3 (ani2) data 4 (ani3) data 5 (ani0) data 6 (ani1) data 7 (ani2) intad data 1 (ani0) data 5 (ani0) ada0cr0 data 2 (ani1) data 6 (ani1) ada0cr1 data 3 (ani2) ada0cr2 data 4 (ani3) ada0cr3 ani3 ani0 ani1 ani2 data 1 data 2 data 3 data 4 data 6 data 5 data 7 conversion start set ada0ce bit to 1 remark the above timing applies to the software tri gger mode (ada0m0.ad0tmd bit = 0) or the high-speed conversion mode (ada0m1.ada0hs1 bit = 1).
v850es/jg3-l chapter 14 a/d converter r01uh0165ej0700 rev.7.00 page 525 of 1113 sep 22, 2011 figure 14-5. example of timing in continuous scan mode (ada0s register = 03h) (2/2) (b) relationship between analog input pins and a/d conversion result registers a/d converter ada0crn register analog input pin ani0 ani1 ani2 ani3 ani4 ani5 ani9 ani10 ani11 . . . . ada0cr0 ada0cr1 ada0cr2 ada0cr3 ada0cr4 ada0cr5 ada0cr9 ada0cr10 ada0cr11 . . .
v850es/jg3-l chapter 14 a/d converter r01uh0165ej0700 rev.7.00 page 526 of 1113 sep 22, 2011 (3) one-shot select mode in this mode, the voltage of the anal og input pin specified by the ada0s register is converted into a digital value only once. the conversion result is stored in th e ada0crn register corresponding to the analog input pin. in this mode, an analog input pin and an ada0crn register correspond on a one-to-one basis. when a/d conversion has been completed once, the intad signal is generated. a/d conversion is stopped after it has been completed (n = 0 to 11). figure 14-6. example of timing in one-s hot select mode (ada0s register = 01h) ani1 a/d conversion data 1 (ani1) data 2 (ani1) data 1 data 2 data 1 (ani1) data 2 (ani1) ada0cr1 intad conversion end conversion end conversion start set ada0ce bit to 1 conversion start set ada0ce bit to 1 remark the above timing applies to the software tri gger mode (ada0m0.ad0tmd bit = 0) or the high-speed conversion mode (ada0m1.ada0hs1 bit = 1). (4) one-shot scan mode in this mode, analog input pins are sequentially selected , from the ani0 pin to the pin specified by the ada0s register, and their values are converted into digital values . each conversion result is stored in the ada0crn re gister corresponding to the analog input pin. when conversion of the analog input pin spec ified by the ada0s register is comp lete, the intad signal is generated. a/d conversion is stopped after it has been completed (n = 0 to 11).
v850es/jg3-l chapter 14 a/d converter r01uh0165ej0700 rev.7.00 page 527 of 1113 sep 22, 2011 figure 14-7. example of timing in one-shot scan mode (ada0s register = 03h) (1/2) (a) timing example a/d conversion data 1 (ani0) data 2 (ani1) data 3 (ani2) data 4 (ani3) intad conversion end ani3 ani0 ani1 ani2 data 1 data 2 data 3 data 4 data 1 (ani0) ada0cr0 data 2 (ani1) ada0cr1 data 3 (ani2) ada0cr2 data 4 (ani3) ada0cr3 conversion start set ada0ce bit to 1 remark the above timing applies to the software tri gger mode (ada0m0.ad0tmd bit = 0) or the high-speed conversion mode (ada0m1.ada0hs1 bit = 1).
v850es/jg3-l chapter 14 a/d converter r01uh0165ej0700 rev.7.00 page 528 of 1113 sep 22, 2011 figure 14-7. example of timing in one-shot scan mode (ada0s register = 03h) (2/2) (b) relationship between analog input pins and a/d conversion result registers a/d converter ada0crn register analog input pin ani0 ani1 ani2 ani3 ani4 ani5 ani9 ani10 ani11 . . . . ada0cr0 ada0cr1 ada0cr2 ada0cr3 ada0cr4 ada0cr5 ada0cr9 ada0cr10 ada0cr11 . . .
v850es/jg3-l chapter 14 a/d converter r01uh0165ej0700 rev.7.00 page 529 of 1113 sep 22, 2011 14.5.5 power-fail compare mode in this mode, whether the input analog signa l voltage is the specified voltage or higher or whether it is lower than the specified voltage is judged, and if th e condition specified by the ada0pfc bit is satisfied, the a/d conversion end interrupt request signal (intad) is generated. ? when the ada0pfm.ada0pfe bit is 0, the intad signa l is generated each time a/d conversion is completed at the following timing (normal use of the a/d converter) . ? continuous/one-shot select mode: afte r the fist a/d conversion is complete ? continuous/one-shot scan mode: after a/d conversi ons are performed sequentially for the analog input pins up to the one specified by the ada0s register ? when the ada0pfe bit is 1 and when the ada0pfm.ada0pf c bit is 0, the value of the ada0crnh register is compared with the value of the ada0 pft register when conversion is completed, and the intad signal is generated only if ada0crnh ada0pft. ? when the ada0pfe bit is 1 and when the ada0pfc bit is 1, the value of the ada0cr nh register is compared with the value of the ada0pft register when conversion is completed, and the intad signal is generated only if ada0crnh < ada0pft. remark n = 0 to 11 in the power-fail compare mode, four modes are available: continuous se lect mode, continuous scan mode, one-shot select mode, and one-shot scan mode.
v850es/jg3-l chapter 14 a/d converter r01uh0165ej0700 rev.7.00 page 530 of 1113 sep 22, 2011 (1) continuous select mode in this mode, the result of converting the voltage of the analog input pin specified by the ada0s register is compared with the set value of the ada0pft register. if the result of power-fail comparison matches the condition set by the ada0pfc bit, the conversion result is stored in the ada0crn register, and the intad signal is generated. if it does not match, the conversi on result is stored in the ada0crn register, and the intad signal is not generated. after completion of the firs t conversion, the next conv ersion is started, unless the ada0m0.ada0ce bit is clear ed to 0 (n = 0 to 11). figure 14-8. example of timing in continuous select mode (when power-fail comparison is made: ada0pfm.ada0pfc bit = 0, ada0s register = 01h) ani1 power-fail comparison value a/d conversion data 1 (ani1) data 2 (ani1) data 3 (ani1) data 4 (ani1) data 5 (ani1) data 1 data 2 data 3 data 4 data 5 data 1 (ani1) data 2 (ani1) data 3 (ani1) data 4 (ani1) ada0cr1 intad ada0pft mismatch ada0pft mismatch ada0pft match ada0pft match conversion start set ada0ce bit to 1 conversion end set ada0ce bit to 0 remark the above timing applies to the software tri gger mode (ada0m0.ad0tmd bit = 0) or the high-speed conversion mode (ada0m1.ada0hs1 bit = 1). (2) continuous scan mode in this mode, the results of converting the voltages of the analog input pins, from the ani0 pin to the pin specified by the ada0s register , are stored sequentially. first, the conversion result of channel 0 is compared. if the result of power-fail comparison matches the condition set by the ada0pfc bit, the conversion result is stored in the ada0cr0 register, and the intad signal is generated. if it does not match, the conversi on result is stored in the ada0cr0 register, and the intad signal is not generated. after the result of the first conversion has been stored in the ada0cr0 register, the results of sequentially converting the voltages of the analog i nput pins up to the pin specified by the ada0s register are continuously stored. after completion of conversion, the next conv ersion is started from the ani0 pin again, unless the ada0ce bit is cleared to 0.
v850es/jg3-l chapter 14 a/d converter r01uh0165ej0700 rev.7.00 page 531 of 1113 sep 22, 2011 figure 14-9. example of timing in continuous scan mode (when power-fail comparison is made: ada0pfm.ada0pfc bit = 0, ada0s register = 03h) (1/2) (a) timing example a/d conversion data 1 (ani0) data 2 (ani1) data 3 (ani2) data 4 (ani3) data 5 (ani0) data 6 (ani1) data 7 (ani2) intad data 1 (ani0) data 5 (ani0) ada0cr0 data 2 (ani1) data 6 (ani1) ada0cr1 data 3 (ani2) ada0cr2 data 4 (ani3) ada0cr3 ani3 ani0 ani1 ani2 data 1 data 2 data 3 data 4 data 6 data 5 data 7 power-fail comparison value ada0pft match ada0pft mismatch conversion start set ada0ce bit to 1 remark the above timing applies to the software tri gger mode (ada0m0.ad0tmd bit = 0) or the high-speed conversion mode (ada0m1.ada0hs1 bit = 1).
v850es/jg3-l chapter 14 a/d converter r01uh0165ej0700 rev.7.00 page 532 of 1113 sep 22, 2011 figure 14-9. example of timing in continuous scan mode (when power-fail comparison is made: ada0pfm.ada0pfc bit = 0, ada0s register = 03h) (2/2) (b) relationship between analog input pins and a/d conversion result registers a/d converter ada0crn register analog input pin ani0 ani1 ani2 ani3 ani4 ani5 ani9 ani10 ani11 . . . . ada0cr0 ada0cr1 ada0cr2 ada0cr3 ada0cr4 ada0cr5 ada0cr9 ada0cr10 ada0cr11 . . .
v850es/jg3-l chapter 14 a/d converter r01uh0165ej0700 rev.7.00 page 533 of 1113 sep 22, 2011 (3) one-shot select mode in this mode, the result of converting the voltage of the analog input pin specified by the ada0s register is compared with the set value of the ada0pft register. if the result of power-fail comparison matches the condition set by the ada0pfc bit, the conversion result is stored in the ada0crn register, and the intad signal is generated. if it does not match, the conversi on result is stored in the ada0crn register, and the intad signal is not generated. conversion is stopped after it has been completed. figure 14-10. example of timing in one-shot select mode (when power-fail comparison is made: ada0pfm.ada0pfc bit = 1, ada0s register = 01h) ani1 a/d conversion data 1 (ani1) data 2 (ani1) data 1 data 2 data 1 (ani1) data 2 (ani1) ada0cr1 intad ada0pft match conversion end ada0pft mismatch conversion end power-fail comparison value conversion start set ada0ce bit to 1 conversion start set ada0ce bit to 1 remark the above timing applies to the software tri gger mode (ada0m0.ad0tmd bit = 0) or the high-speed conversion mode (ada0m1.ada0hs1 bit = 1). (4) one-shot scan mode in this mode, the results of converting the voltages of the analog input pins seque ntially selected from the ani0 pin to the pin specified by the ada0s register ar e stored, and the set value of the ada0cr0h register of channel 0 is compared with the set value of the ada0p ft register. if the result of power-fail comparison matches the condition set by the ada0pfc bit, the conver sion result is stored in the ada0cr0 register and the intad signal is generated. if it does not match, the conversion result is stored in the ada0cr0 register, and the intad0 signal is not generated. after the resu lt of the first conversion has been stored in the ada0cr0 register, the results of converting the signal s on the analog input pins specified by the ada0s register are sequentially stored. conver sion is stopped after it has been completed.
v850es/jg3-l chapter 14 a/d converter r01uh0165ej0700 rev.7.00 page 534 of 1113 sep 22, 2011 figure 14-11. example of timing in one-shot scan mode (when power-fail comparison is made: ada0pfm.ada0pfc bit = 0, ada0s register = 03h) (1/2) (a) timing example a/d conversion data 1 (ani0) data 2 (ani1) data 3 (ani2) data 4 (ani3) intad ada0pft match ani3 ani0 ani1 ani2 data 1 data 2 data 3 data 4 data 1 (ani0) ada0cr0 data 2 (ani1) ada0cr1 data 3 (ani2) ada0cr2 data 4 (ani3) ada0cr3 power-fail comparison value conversion start set ada0ce bit to 1 remark the above timing applies to the software tri gger mode (ada0m0.ad0tmd bit = 0) or the high-speed conversion mode (ada0m1.ada0hs1 bit = 1).
v850es/jg3-l chapter 14 a/d converter r01uh0165ej0700 rev.7.00 page 535 of 1113 sep 22, 2011 figure 14-11. example of timing in one-shot scan mode (when power-fail comparison is made: ada0pfm.ada0pfc bit = 0, ada0s register = 03h) (2/2) (b) relationship between analog input pins and a/d conversion result registers a/d converter ada0crn register analog input pin ani0 ani1 ani2 ani3 ani4 ani5 ani9 ani10 ani11 . . . . ada0cr0 ada0cr1 ada0cr2 ada0cr3 ada0cr4 ada0cr5 ada0cr9 ada0cr10 ada0cr11 . . .
v850es/jg3-l chapter 14 a/d converter r01uh0165ej0700 rev.7.00 page 536 of 1113 sep 22, 2011 14.6 cautions (1) when a/d converter is not used when the a/d converter is not used, the power consumption can be reduced by clearing the ada0m0.ada0ce bit to 0. (2) input range of ani0 to ani11 pins input a voltage within the ratings to the ani0 to an i11 pins. if a voltage equal to or higher than av ref0 or equal to or lower than av ss (even within the range of the absolute ma ximum ratings) is input to any of these pins, the conversion value of that c hannel is undefined, and the conversion value of the other channels may also be affected. (3) countermeasures against noise to maintain the 10-bit reso lution, the ani0 to ani11 pins must be effectively protected from noise. the influence of noise increases as the output impedance of the analog input source becomes higher. to lower the noise, connecting an external capacitor as shown in figure 14-12 is recommended. the capacitor must have a capacitance appr opriate for the input signal change speed. figure 14-12. handling of analog input pin av ref0 v dd v ss av ss clamp using a diode with a low v f (0.3 v or less). ani0 to ani11
v850es/jg3-l chapter 14 a/d converter r01uh0165ej0700 rev.7.00 page 537 of 1113 sep 22, 2011 (4) alternate i/o the analog input pins (ani0 to ani11) function alternat ely as port pins. when selecting one of the ani0 to ani11 pins to execute a/d conversion , do not execute an instruction to r ead an input port or write to an output port during conversion as the conversion resolution may drop. also the conversion resolution may drop at the pins set as output port pins during a/ d conversion if the output current fluctuates due to the ef fect of the external circuit connected to the port pins. if a digital pulse is applied to a pin adjacent to the pin whose input signal is being converted, the a/d conversion value may not be as expected due to the infl uence of coupling noise. therefore, do not apply a pulse to a pin adjacent to the pin undergoing a/d conversion. (5) interrupt request flag (adif) the interrupt request flag (adif) is not cleared (0) even if the contents of the ada0s register are changed. if the analog input pin is changed during a/d conversion, therefore, the result of converting the previously selected analog input signal may be stored and the conversion end interrupt request flag may be set (1) immediately before the ada0s register is rewritten. if the adif flag is read immediately after the ada0s register is rewritten, the adif flag may be set (1) even though the a/d conversion of the newly selected analog input pin has not been completed. when a/d co nversion is stopped, clear (0) the adif flag before resuming conversion. figure 14-13. timing of generating a/d conversion end interrupt request ada0s rewriting (anin conversion start) ada0s rewriting (anim conversion start) adif is set, but anim conversion does not end a/d conversion ada0crn intad anin anin anim anim anim anin anin anim remark n = 0 to 11 m = 0 to 11
v850es/jg3-l chapter 14 a/d converter r01uh0165ej0700 rev.7.00 page 538 of 1113 sep 22, 2011 (6) internal equivalent circuit the following shows the equivalent circuit of the analog input block. figure 14-14. internal equivalent circuit of anin pin anin c in r in r in c in 14 k 8.0 pf remarks 1. the above values are reference values. 2. n = 0 to 11 (7) av ref0 pin (a) the av ref0 pin is used as the power supply pin of the a/ d converter and also supplies power to the alternate-function ports. in an application where a backup power supply is used, be sure to supply the same voltage as v dd to the av ref0 pin as shown in figure 14-15. (b) the av ref0 pin is also used as the reference voltage pin of the a/d converter. if the source supplying power to the av ref0 pin has a high impedance or if the power supply has a low current supply capability, the reference voltage may fluctuate due to the cu rrent that flows during conversion (especially, immediately after the conversion enable bit ada0ce has been set to 1). as a result, the conversion accuracy may drop. to avoid this, it is re commended to connect a capacitor across the av ref0 and av ss pins to suppress the reference voltage fluctuation as shown in figure 14-15. (c) if the source supplying power to the av ref0 pin has a high dc resistance, the voltage when conversion is enabled may be lower than the voltage when conversi on is stopped, because of a voltage drop caused by the a/d conversion current. figure 14-15. example of handling av ref0 pin av ref0 note av ss main power supply note parasitic inductance
v850es/jg3-l chapter 14 a/d converter r01uh0165ej0700 rev.7.00 page 539 of 1113 sep 22, 2011 (8) reading ada0crn register when the ada0m0 to ada0m2, ada0s, ada0pfm, or ad a0pft register is written, the contents of the ada0crn register may be undefined. read the conversi on result after completion of conversion and before writing to the ada0m0 to ada0m2, ada0s, ada0pfm, or ada0pft register. also, when an external/timer trigger is acknowledged, the cont ents of the ada0crn register may be undefined. read the conversion result after completion of conversion and before the ne xt external/timer trigger is acknowledged. the correct conversion result may not be read at a timing different from the above. (9) standby mode because the a/d converter stops operating in the st op mode, power consumption can be reduced, but the conversion results will be invalid. operations are resumed after the stop mode is released, but the a/d conversion results after the stop mode is released ar e invalid. when using the a/d converter after the stop mode is released, before setting the stop mode or releasing the stop mode, clear the ada0m0.ada0ce bit to 0 then set the ada0ce bit to 1 after releasing the stop mode. in the idle1, idle2, or subclock operation mode, operation continues. in the idle1 and idle2 modes, since the analog input voltage value cannot be retained, the a/d conversion results after the idle1 and idle2 modes are released are invalid. the results of conv ersions before the idle1 and idle2 modes were set are valid. to lower the power consumption, therefore, clear the ada0m0.ada0ce bit to 0. (10) high-speed conversion mode in the high-speed conversion mode, rewriting t he ada0m0, ada0m2, ada0s, ada0pfm, and ada0pft registers and inputting a trigger during the stabilization time are prohibited. (11) a/d conversion time a/d conversion time is the total time of stabilizati on time, conversion time, wait time, and trigger response time (for details of these times, refer to table 14-2 conversion time se lection in normal conversion mode (ada0hs1 bit = 0) and table 14-3 conversion time sele ction in high-sp eed conversion mode (ada0hs1 bit = 1) ). during a/d conversion in the normal conversion mo de, if the ada0m0, ada0m2 , ada0s, ada0pfm, and ada0pft registers are written or a trigger is input, reco nversion is carried out. however, if the stabilization time end timing conflicts with writing to these registers, or if the stabilizat ion time end timing conflicts with the trigger input, the stabilization time of 64 clocks is reinserted. if a conflict occurs again with the reinserted stabilization ti me end timing, the stabilization time is reinserted. therefore do not set the trigger input interval and cont rol register write interval to 64 clocks or lower. (12) variation of a/d conversion results the results of the a/d conversion may vary depending on the fluctuation of the s upply voltage, or may be affected by noise. to reduce the variation, take c ountermeasures in the progr am such as averaging the a/d conversion results.
v850es/jg3-l chapter 14 a/d converter r01uh0165ej0700 rev.7.00 page 540 of 1113 sep 22, 2011 (13) a/d conversion result hysteresis characteristics the successive comparison type a/d converter holds the a nalog input voltage in the internal sample & hold capacitor and then performs a/d conversion. after a/ d conversion has finished, the analog input voltage remains in the internal sample & hold capacitor. as a result, the following phenomena may occur. ? when the same channel is used for a/d conversions, if the voltage is higher or lower than the previous a/d conversion, then hysteresis characteristics may appear where the conversion result is affected by the previous value. thus, even if the conversion is performed at the same potential, the result may vary. ? when switching the analog input channel, hysteresis characteristics may appear where the conversion result is affected by the previous channel value. this is because on e a/d converter is used for the a/d conversions. thus, even if the conversion is perfo rmed at the same potential, the result may vary. therefore, to obtain a more accurate conversion resu lt, perform a/d conversion twice successively for the same channel, and discard the first conversion result.
v850es/jg3-l chapter 14 a/d converter r01uh0165ej0700 rev.7.00 page 541 of 1113 sep 22, 2011 14.7 how to read a/d converter characteristics table this section describes the terms related to the a/d converter. (1) resolution the minimum analog input voltage that can be recognized, t hat is, the ratio of an analog input voltage to 1 bit of digital output is called 1 lsb (least significant bit) . the ratio of 1 lsb to the full scale is expressed as %fsr (full-scale range). %fsr is the ratio of a range of convertible analog input voltages expressed as a percentage, and can be expressed as follows, independently of the resolution. 1%fsr = (maximum value of convertible analog input voltage ? minimum value of convertible analog input voltage)/100 = (av ref0 ? 0)/100 = av ref0 /100 when the resolution is 10 bits, 1 lsb is as follows: 1 lsb = 1/2 10 = 1/1,024 = 0.098%fsr the accuracy is determined by the overall error, independently of the resolution. (2) overall error this is the maximum value of the difference between an actually measured value and a theoretical value. it is a total of zero-scale error, full-scale error, linearity error, and a combination of these errors. the overall error in the characteristics ta ble does not include the quantization error. figure 14-16. overall error ideal line overall error 1 ...... 1 0 ...... 0 0av ref0 analog input digital output
v850es/jg3-l chapter 14 a/d converter r01uh0165ej0700 rev.7.00 page 542 of 1113 sep 22, 2011 (3) quantization error this is an error of 1/2 lsb that inevitably occurs when an analog value is converted into a digital value. because the a/d converter converts analog input voltages in a range of 1/2 lsb into the same digital codes, a quantization error is unavoidable. this error is not included in the overall error, zero-sca le error, full-scale error, integral linearity error, or differential linearity error in the characteristics table. figure 14-17. quantization error quantization error 1 ...... 1 0 ...... 0 0av ref0 analog input digital output 1/2 lsb 1/2 lsb (4) zero-scale error this is the difference between the ac tually measured analog input voltage and its theoretical value when the digital output changes from 0?000 to 0?001 (1/2 lsb). figure 14-18. zero-scale error av ref0 analog input (lsb) digital output (lower 3 bits) ideal line 111 ? 10123 100 011 010 001 000 zero-scale error
v850es/jg3-l chapter 14 a/d converter r01uh0165ej0700 rev.7.00 page 543 of 1113 sep 22, 2011 (5) full-scale error this is the difference between the ac tually measured analog input voltage and its theoretical value when the digital output changes from 1?110 to 1?111 (full scale ? 3/2 lsb). figure 14-19. full-scale error av ref0 analog input (lsb) digital output (lower 3 bits) 111 av ref0 ? 3 0 av ref0 ? 2av ref0 ? 1 100 011 010 000 full-scale error (6) differential linearity error ideally, the width to output a specific code is 1 lsb. this error indicates the difference between the actually measured value and its theoretical value when a specific code is out put. this indicates the basic characteristics of the a/d conversion wh en the voltage applied to the analog input pins of the same channel is consistently increased bit by bit from av ss to av ref0 . when the input voltage is increased or decreased, or when two or more channels are used, see 14.7 (2) overall error . figure 14-20. differential linearity error ideal width of 1 lsb differential linearity error 1 ...... 1 0 ...... 0 av ref0 analog input digital output
v850es/jg3-l chapter 14 a/d converter r01uh0165ej0700 rev.7.00 page 544 of 1113 sep 22, 2011 (7) integral linearity error this error indicates the extent to which the conversion ch aracteristics differ from the ideal linear relationship. it indicates the maximum value of the difference bet ween the actually measured value and its theoretical value where the zero-scale error and full-scale error are 0. figure 14-21. integral linearity error 1 ...... 1 0 ...... 0 0av ref0 analog input digital output ideal line integral linearity error (8) conversion time this is the time required to obtain a digital output after sampling has started. the conversion time in the characteristics table includes the sampling time. (9) sampling time this is the time for which the analog switch is on to load an analog voltage to the sample & hold circuit. figure 14-22. relationship between conversion time and sampling time sampling time conversion time
v850es/jg3-l chapter 15 d/a converter r01uh0165ej0700 rev.7.00 page 545 of 1113 sep 22, 2011 chapter 15 d/a converter 15.1 functions in the v850es/jg3-l, two r-2r ladder type d/a c onverter channels are provided (da0cs0 and da0cs1). the d/a converter has the following functions. { 8-bit resolution 2 channels { r-2r ladder method { conversion time: 3 s (max.) (when av ref1 = 2.7 to 3.6 v, external load = 20 pf) { analog output voltage: av ref1 m/256 (m = 0 to 255; value set to da0csn register) { operation modes: normal mo de, real-time output mode remark n = 0, 1
v850es/jg3-l chapter 15 d/a converter r01uh0165ej0700 rev.7.00 page 546 of 1113 sep 22, 2011 15.2 configuration the d/a converter includes the following hardware. table 15-1. d/a converter registers used by software item configuration control registers d/a converter mode register (da0m) d/a conversion value setting registers 0 and 1 (da0cs0, da0cs1) the block diagram of the d/a converter is shown below. figure 15-1. block diag ram of d/a converter da0cs1 write inttp3cc0 signal da0cs0 write inttp2cc0 signal av ref1 av ss d/a conversion value setting register 1 (da0cs1) d/a conversion value setting register 0 (da0cs0) 2r 2r 2r 2r r r ano1 ano0 da0ce1 d/a converter mode register 0 (da0m) internal bus 2r 2r 2r 2r r r da0md1 da0ce0 da0md0 d/a converter mode register 1 (da0m) selector selector internal bus caution da0cs0 and d0acs1 are also used as the av ref1 and av ss pins. the av ss pin is also used by the a/d converter.
v850es/jg3-l chapter 15 d/a converter r01uh0165ej0700 rev.7.00 page 547 of 1113 sep 22, 2011 15.3 registers the registers that control the d/ a converter are as follows. ? d/a converter mode register (da0m) ? d/a conversion value setting registers 0, 1 (da0cs0, da0cs1) (1) d/a converter mode register (da0m) the da0m register controls the operation of the d/a converter. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 normal mode real-time output mode note da0mdn 0 1 selection of d/a converter operation mode (n = 0, 1) da0m 0 da0ce1 da0ce0 0 0 da0md1 da0md0 after reset: 00h r/w address: fffff282h disables operation enables operation da0cen 0 1 d/a converter operation enable/disable (n = 0, 1) < > < > note the output trigger in the real-time outpu t mode (da0mdn bit = 1) is as follows. ? when n = 0: inttp2cc0 signal (see chapter 7 16-bit timer/event counter p (tmp) ) ? when n = 1: inttp3cc0 signal (see chapter 7 16-bit timer/event counter p (tmp) )
v850es/jg3-l chapter 15 d/a converter r01uh0165ej0700 rev.7.00 page 548 of 1113 sep 22, 2011 (2) d/a conversion value setting re gisters 0, 1 (da0cs0, da0cs1) the da0cs0 and da0cs1 registers set the analog volt age value output to the ano0 and ano1 pins. these registers can be read or written in 8-bit units. reset sets these registers to 00h. da0csn7 da0csn da0csn6 da0csn5 da0csn4 da0csn3 da0csn2 da0csn1 da0csn0 after reset: 00h r/w address: da0cs0 fffff280h, da0cs1 fffff281h caution in the real-time output mode (da0m.da0mdn bit = 1), set the da0csn register before the inttp2cc0/inttp3cc0 signal is generated. d/a conversion starts when the inttp2cc0/inttp3cc0 signal is generated. remark n = 0, 1
v850es/jg3-l chapter 15 d/a converter r01uh0165ej0700 rev.7.00 page 549 of 1113 sep 22, 2011 15.4 operation 15.4.1 operation in normal mode d/a conversion is performed using a write operation to the da0csn register as the trigger. the setting method is described below. <1> set the pm1n bit to 1 (input mode). <2> clear the da0m.da0mdn bit to 0 (normal mode). <3> set the analog voltage value to be output to the anon pin to the da0csn register. steps <2> and <3> above constitute the initial settings. <4> set the da0m.da0cen bit to 1 (d/a conversion enable). the d/a converted analog voltage val ue is output from the anon pin when this setting is performed. <5> to change the analog voltage value, write to the da0csn register. the analog voltage value set immediately before is held until the next write oper ation is performed. remarks 1. for the alternate-function pin settings, refer to table 4-15 settings wh en pins are used for alternate functions . 2. n = 0, 1 15.4.2 operation in real-time output mode d/a conversion is performed using the interrupt request signal of tmp2 or tmp3 (i nttp2cc0 or inttp3cc0) as the trigger. the setting method is described below. <1> set the pm1n bit to 1 (input mode). <2> set the da0m.da0mdn bit to 1 (real-time output mode). <3> set the analog voltage value to be output to the anon pin to the da0csn register. <4> set the da0m.da0cen bit to 1 (d/a conversion enable). steps <2> to <4> above constitute the initial settings. <5> operate tmp2 and tmp3. <6> the d/a converted analog voltage value is output from the anon pin when the inttp2cc0 or inttp3cc0 signal is generated. set the analog voltage value to be output to the da 0csn register next, before the next inttp2cc0 or inttp3cc0 signal is generated. <7> after that, the value set to the da0csn register is output from the anon pin every time the inttp2cc0 or inttp3cc0 signal is generated. remarks 1. the output values of the ano0 and ano1 pins up to <6> above are undefined. 2. for the output values of the ano0 and ano1 pi ns in the idle1, idle 2, halt, and stop modes, refer to chapter 23 standby function . 3. n = 0, 1
v850es/jg3-l chapter 15 d/a converter r01uh0165ej0700 rev.7.00 page 550 of 1113 sep 22, 2011 15.4.3 cautions observe the following cautions when using the d/a converter. (1) set the port pins to the input mode (pm1n bit = 1). (2) do not read or write the p1 register during d/a conversion. (3) when using one of the p10/ano0 and p11/ano1 pins as an i/o port pin and the other as a d/a output pin, do so in an application w here the port i/o level does not change duri ng d/a output. (4) in the real-time output mode, avoid a conflict between writing the da0csn register by software and trigger signal output, which can occur by writing the da0csn register while the interrupt requested by the selected trigger signal is being serviced. (5) make sure that av ref1 v dd and av ref1 = 2.7 to 3.6 v. the operation is not guaranteed if ranges other than the above are used. (6) turn on or off av ref1 at the same time as turning on or off av ref0 . (7) because the output impedance of t he d/a converter is high, a current ca nnot be supplied from the anon pin. when connecting a resistor of 2 m or lower, take appropriate measures such as inserting a jfet input type operational amplifier between the resistor and the anon pin. remark n = 0, 1 figure 15-2. example of external pin connection anon av ref0 av ref1 av ss ev dd 2 m + ? output 10 f 0.1 f 10 f 0.1 f jfet input operational amplifier caution the figure shown here is only for refe rence. use it after fully evaluating its appropriateness. (8) because the d/a converter stops operating in th e stop mode, the ano0 and ano1 pins go into a high-impedance state, and the pow er consumption can be reduced. in the idle1, idle2, or subclock operation mode, however, the d/a c onverter continues operating. to lower the power consumption, therefor e, clear the da0m.da0cen bit to 0.
v850es/jg3-l chapter 16 asynchronous serial interface a (uarta) r01uh0165ej0700 rev.7.00 page 551 of 1113 sep 22, 2011 chapter 16 asynchronous serial interface a (uarta) the pd70f3737, 70f3738 have 3-channels uarta. the pd70f3792, 70f3793, 70f3841, 70f3842 have 6-channels uarta. 16.1 features { on-chip dedicated baud rate generator { transfer rate: 300 bps to 625 kbps (using dedicated baud rate generator) { full-duplex communication { double buffer configuration internal uartan receive data register (uanrx) internal uartan transmit data register (uantx) { reception error detection function ? parity error ? framing error ? overrun error { interrupt sources: 2 ? reception complete interrupt (intuanr): this inte rrupt occurs upon transfer of receive data from the receive shift register to the receive data register after serial transfer completion, in the reception enabled status. ? transmission enable interrupt (intuant): this interr upt occurs upon transfer of transmit data from the transmit data register to the transmit shift register in the transmission enabled status. (continuous transmission is possible.) { character length: 7, 8 bits { parity function: odd, even, 0, none { transmission stop bit: 1, 2 bits { msb-/lsb-first transfer selectable { internal digital noise filter { inverted input/output of transmit/receive data possible { sbf (sync break field) transmission/reception in the li n (local interconnect network) communication format ? 13 to 20 bits selectable for sbf transmission ? recognition of 11 bits or more possible for sbf reception ? sbf reception flag provided remark n = 0 to 2 ( pd70f3737, 70f3738) n = 0 to 5 ( pd70f3792, 70f3793, 70f3841, 70f3842)
v850es/jg3-l chapter 16 asynchronous serial interface a (uarta) r01uh0165ej0700 rev.7.00 page 552 of 1113 sep 22, 2011 16.2 configuration uartan includes the following hardware. table 16-1. configuration of uartan item configuration registers uartan control register 0 (uanctl0) uartan control register 1 (uanctl1) uartan control register 2 (uanctl2) uartan option control register 0 (uanopt0) uartan status register (uanstr) uartan receive shift register uartan receive data register (uanrx) uartan transmit shift register uartan transmit data register (uantx) the block diagram of the uartan is shown below. figure 16-1. block diagram of uartan internal bus internal bus uartan receive shift register uanrx filter selector uantx uartan transmit shift register transmission controller reception controller selector baud rate generator baud rate generator intuanr intuant txdan rxdan f xx to f xx /2 10 ascka0 note reception unit transmission unit clock selector uanopt0 uanctl1 uanctl2 uanstr uanctl0 note uarta0 only remarks1. n = 0 to 2 ( pd70f3737, 70f3738) n = 0 to 5 ( pd70f3792, 70f3793, 70f3841, 70f3842) 2. for the configuration of the baud rate generator, see figure 16-17 .
v850es/jg3-l chapter 16 asynchronous serial interface a (uarta) r01uh0165ej0700 rev.7.00 page 553 of 1113 sep 22, 2011 (1) uartan control register 0 (uanctl0) the uanctl0 register is an 8-bit register used to specify the operation of uartan. (2) uartan control register 1 (uanctl1) the uanctl1 register is an 8-bit register used to select the base clock (f uclk ) for uartan. (3) uartan control register 2 (uanctl2) the uanctl2 register is an 8-bit register used with the uanctl1 register to generate the baud rate for uartan. (4) uartan option control register 0 (uanopt0) the uanopt0 register is an 8-bi t register used to control sbf transmission/reception in the lin communication format and the level of the transmission/reception signals for the uartan. (5) uartan status register (uanstr) the uanstr register is an 8-bit register that indicate s the contents of a reception error. each one of the reception error flags is set (to 1) upon the occurrence of a reception error. (6) uartan receive shift register this is a shift register used to convert the serial data input to the rxdan pin into parallel data. upon reception of 1-character data and det ection of the stop bit, the receiv e data is transferred to the uanrx register. this register cannot be manipulated directly. (7) uartan receive data register (uanrx) the uanrx register is an 8-bit buffer register that holds receive data. in the reception enabled status, receive data is transfe rred from the uartan receive shift register to the uanrx register in synchronization with the comple tion of shift-in processing of 1 character. transfer to the uanrx register also causes the recept ion complete interrupt request signal (intuanr) to be output. (8) uartan transmit shift register the transmit shift register is a shift register used to convert the parallel data transferred from the uantx register into serial data. when 1-character data is transferred from the uantx regist er, the shift register data is output from the txdan pin. this register cannot be manipulated directly. (9) uartan transmit data register (uantx) the uantx register is an 8-bit transmit data buffer. transmission starts when transmit data is written to the uantx register. when data can be wri tten to the uantx register (when 1- character data is transferred from the uantx register to the uartan transmit shift regist er), the transmission enable interrupt request signal (intuant) is generated.
v850es/jg3-l chapter 16 asynchronous serial interface a (uarta) r01uh0165ej0700 rev.7.00 page 554 of 1113 sep 22, 2011 16.2.1 pin functions of each channel the rxdan, txdan, and ascka0 pins used by uarta in the v850es/jg3-l are used for other functions as shown in table 16-2. to use these pins for ua rta, set the related registers as described in table 4-15 settings when pins are used for alternate functions . table 16-2. pins used by uarta pin no. channel gf gc f1 port uarta reception input uarta transmission output uarta clock i/o note1 other functions 28 26 k3 p31 rxda0 ? ? intp7/sib4 27 25 l3 p30 ? txda0 ? sob4 uarta0 29 27 l4 p32 ? ? ascka0 note1 sckb4/tip00/top00 46 44 l9 p91 rxda1 ? ? a1/kr7/scl02 uarta1 45 43 h8 p90 ? txda1 ? a0/kr6/sda02 38 36 h7 p39 rxda2 ? ? scl00 uarta2 37 35 h6 p38 ? txda2 ? sda00 ? 32 j6 p37 rxda3 ? ? ? uarta3 note2 ? 31 h5 p36 ? txda3 ? ? ? 46 j9 p93 rxda4 ? ? a3/tip40/top40 uarta4 note2 ? 45 k9 p92 ? txda4 ? a2/tip41/top41 ? 48 k10 p95 rxda5 ? ? a5/tip30/top30 uarta5 note2 ? 47 l10 p94 ? txda5 ? a4/tip31/top31 notes1. the ascka0 function is provided only for uarta0. 2. pd70f3792, 70f3793, 70f 3841, 70f3842 only caution other than alternate function pins above, intua5t interrupt of uart5 and intp3cc1 interrupt of tmp3, and intu a5r interrupt of uart5 and intp3ov interrupt of tmp3 are alternate interrupt signals and therefore cannot be used simultaneously ( pd70f3792, 70f3793, 70f3841, 70f3842 only). remark gf: 100-pin plastic lqfp (14 20) ( pd70f3737, 70f3738 only) gc: 100-pin plastic lqfp (fine pitch) (14 14) f1: 121-pin plastic fbga (8 8)
v850es/jg3-l chapter 16 asynchronous serial interface a (uarta) r01uh0165ej0700 rev.7.00 page 555 of 1113 sep 22, 2011 16.3 mode switching of uarta and other serial interfaces 16.3.1 uarta0 and csib4 mode switching in the v850es/jg3-l, uarta0 and csib4 share pins and therefore cannot be used simultaneously. to use the uarta0 function, specify the uarta0 mode in advanc e by using the pmc3, pfc3, and pfce3 registers. switching the operation mode between ua rta0 and csib4 is described below. caution transmission and reception by uarta0 and csib4 are not guaranteed if these operation modes are switched during transmission or reception. be sure to stop the serial interface that is not being used. figure 16-2. switching uarta0 and csib4 operation modes pmc3 after reset: 0000h r/w address: fffff446h, fffff447h 0 0 pmc35 pmc34 pmc33 pmc32 pmc31 pmc30 0 0 0 0 0 0 pmc39 pmc38 8 9 10 11 12 13 14 15 pfc3 after reset: 0000h r/w address: fffff466h, fffff467h 0 0 0 0 0 0 pfc39 pfc38 0 0 pfc35 pfc34 pfc33 pfc32 pfc31 pfc30 8 9 10 11 12 13 14 15 pfce3l after reset: 00h r/w address: fffff706h 0 0 0 0 0 pfce32 0 0 port i/o mode ascka0 mode sckb4 mode port i/o mode uarta0 mode csib4 mode pmc32 0 1 1 pmc3n 0 1 1 operation mode operation mode pfce32 0 0 pfc32 0 1 pfc3n 0 1 remarks 1. n = 0, 1 2. = don?t care
v850es/jg3-l chapter 16 asynchronous serial interface a (uarta) r01uh0165ej0700 rev.7.00 page 556 of 1113 sep 22, 2011 16.3.2 uarta1 and i 2 c02 mode switching in the v850es/jg3-l, uarta1 and i 2 c02 share pins and therefore cannot be used simultaneously. to use the uarta1 function, specify the uarta1 mode in advance by using the pmc9, pfc9, and pfce9 registers. switching the operation mode between uarta1 and i 2 c02 are described below. caution transmission and reception by uarta1 and i 2 c02 are not guaranteed if these operation modes are switched during transmission or reception. be su re to stop the serial interface that is not being used. figure 16-3. switching uarta1 and i 2 c02 operation modes pmc9 after reset: 0000h r/w address: fffff452h, fffff453h pmc97 pmc96 pmc95 pmc94 pmc93 pmc92 pmc91 pmc90 pmc915 pmc914 pmc913 pmc912 pmc911 pmc910 pmc99 pmc98 8 9 10 11 12 13 14 15 pfc9 after reset: 0000h r/w address: fffff472h, fffff473h pfc915 pfc914 pfc913 pfc912 pfc911 pfc910 pfc99 pfc98 pfc97 pfc96 pfc95 pfc94 pfc93 pfc92 pfc91 pfc90 8 9 10 11 12 13 14 15 pfce915 pfce914 0 0 0 0 0 0 pfce97 pfce96 pfce95 pfce94 pfce93 pfce92 pfce91 pfce90 8 9 10 11 12 13 14 15 pfce9 after reset: 0000h r/w address: fffff712h, fffff713h uarta1 mode i 2 c02 mode pmc9n 1 1 operation mode pfce9n 1 1 pfc9n 0 1 remark n = 0, 1
v850es/jg3-l chapter 16 asynchronous serial interface a (uarta) r01uh0165ej0700 rev.7.00 page 557 of 1113 sep 22, 2011 16.3.3 uarta2 and i 2 c00 mode switching in the v850es/jg3-l, uarta2 and i 2 c00 share pins and therefore cannot be used simultaneously. to use the uarta2 function, specify the uarta2 mode in adv ance by using the pmc3 and pfc3 registers. switching the operation mode between uarta2 and i 2 c00 are described below. caution transmission and reception by uarta2 and i 2 c00 are not guaranteed if these operation modes are switched during transmission or reception. be sure to stop the serial interface that is not being used. figure 16-4. switching uarta2 and i 2 c00 operation modes pmc3 after reset: 0000h r/w address: fffff446h, fffff447h 0 0 pmc35 pmc34 pmc33 pmc32 pmc31 pmc30 0 0 0 0 0 0 pmc39 pmc38 8 9 10 11 12 13 14 15 pfc3 after reset: 0000h r/w address: fffff466h, fffff467h 0 0 0 0 0 0 pfc39 pfc38 0 0 pfc35 pfc34 pfc33 pfc32 pfc31 pfc30 8 9 10 11 12 13 14 15 port i/o mode uarta2 mode i 2 c00 mode pmc3n 0 1 1 operation mode pfc3n 0 1 remarks 1. n = 8, 9 2. = don?t care
v850es/jg3-l chapter 16 asynchronous serial interface a (uarta) r01uh0165ej0700 rev.7.00 page 558 of 1113 sep 22, 2011 16.4 registers (1) uartan control register 0 (uanctl0) the uanctl0 register is an 8-bit register that c ontrols the uartan serial transfer operation. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 10h. (1/2) uanpwr disable uartan operation (uartan reset asynchronously) enable uartan operation uanpwr 0 1 uartan operation control uanctl0 (n = 0 to 5) uantxe uanrxe uandir uanps1 uanps0 uancl uansl <6> <5> <4> 3 2 1 after reset: 10h r/w address: ua0ctl0 fffffa00h, ua1ctl0 fffffa10h, ua2ctl0 fffffa20h, ua3ctl0 fffffa30h note , ua4ctl0 fffffa40h note , ua5ctl0 fffffa50h note the uartan operation is controlled by the uanpwr bit. the txdan pin output is fixed to high level by clearing the uanpwr bit to 0 (fixed to low level if uanopt0.uantdl bit = 1). disable transmission operation enable transmission operation uantxe 0 1 transmission operation enable ? to start transmission, set the uanpwr bit to 1 and then set the uantxe bit to 1. to stop transmission, clear the uantxe bit to 0 and then uanpwr bit to 0. ? to initialize the transmission unit, clear the uantxe bit to 0, wait for two cycles of the base clock, and then set the uantxe bit to 1 again. otherwise, initialization may not be executed (for the base clock, see 16.7 (1) (a) base clock ). ? when uartan operation is enabled (uanpwr bit = 1) and the uantxe bit is set to 1, transmission is enabled after at least two cycles of the base clock (f uclk ) have elapsed. disable reception operation enable reception operation uanrxe 0 1 reception operation enable ? to start reception, set the uanpwr bit to 1 and then set the uanrxe bit to 1. to stop reception, clear the uanrxe bit to 0 and then uanpwr bit to 0. ? to initialize the reception unit, clear the uanrxe bit to 0, wait for two cycles of the base clock, and then set the uanrxe bit to 1 again. otherwise, initialization may not be executed (for the base clock, see 16.7 (1) (a) base clock ). ? when uartan operation is enabled (uanpwr bit = 1) and the uanrxe bit is set to 1, reception is enabled after at least two cycles of the base clock (f uclk ) have elapsed. if a start bit is received before reception is enabled, the start bit is ignored. <7> 0 note pd70f3792, 70f3793, 70f 3841, 70f3842 only
v850es/jg3-l chapter 16 asynchronous serial interface a (uarta) r01uh0165ej0700 rev.7.00 page 559 of 1113 sep 22, 2011 (2/2) 7 bits 8 bits uancl 0 1 specification of data character length of 1 frame of transmit/receive data ? this register can be rewritten only when the uanpwr bit is 0 or the uantxe bit and the uanrxe bit are 0. ? when transmission and reception are performed in the lin format, set the uancl bit to 1. 1 bit 2 bits uansl 0 1 specification of length of stop bit for transmit data this register can be rewritten only when the uanpwr bit is 0 or the uantxe bit and the uanrxe bit are 0. ? this register is rewritten only when the uanpwr bit is 0 or the uantxe bit and the uanrxe bit are 0. ? if ?reception with 0 parity? is selected during reception, a parity check is not performed. therefore, the uanstr.uanpe bit is not set. ? when transmission and reception are performed in the lin format, clear the uanps1 and uanps0 bits to 00. no parity output 0 parity output odd parity output even parity output reception with no parity reception with 0 parity odd parity check even parity check uanps1 0 0 1 1 parity selection during transmission parity selection during reception uanps0 0 1 0 1 msb first lsb first uandir 0 1 data transfer order ? this register can be rewritten only when the uanpwr bit is 0 or the uantxe bit and the uanrxe bit are 0. ? when transmission and reception are performed in the lin format, set the uandir bit to 1. remark for details of parity, see 16.6.6 parity types and operations . (2) uartan control register 1 (uanctl1) for details, see 16.7 (2) uartan control register 1 (uanctl1) . (3) uartan control register 2 (uanctl2) for details, see 16.7 (3) uartan control register 2 (uanctl2) .
v850es/jg3-l chapter 16 asynchronous serial interface a (uarta) r01uh0165ej0700 rev.7.00 page 560 of 1113 sep 22, 2011 (4) uartan option control register 0 (uanopt0) the uanopt0 register is an 8-bi t register used to control sbf transmission/reception in the lin communication format and the level of the transmission/reception signals for the uartan. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 14h. (1/2) uansrf the uanctl0.uanpwr bit or the uanctl0.uanrxe bit is set to 0, or sbf reception ends normally. during sbf reception uansrf 0 1 sbf reception flag uanopt0 (n = 0 to 5) uansrt uanstt uansls2 uansls1 uansls0 uantdl uanrdl 654321 after reset: 14h r/w address: ua0opt0 fffffa03h, ua1opt0 fffffa13h, ua2opt0 fffffa23h, ua3opt0 fffffa33h note , ua4opt0 fffffa43h note , ua5opt0 fffffa53h note sbf reception trigger uansrt 0 1 sbf reception trigger ? this bit indicates whether sbf (sync brake field) is received in lin communication. ? when an sbf reception error occurs, the uansrf bit remains 1 and sbf reception is started again. ? the uansrf bit is a read-only bit. ? this is the sbf reception trigger bit during lin communication, and is always 0 when read . ? for sbf reception, set the uansrt bit (to 1) to enable sbf reception. ? set the uansrt bit after setting the uanpwr bit and uanrxe bit to 1. ? this is the sbf transmission trigger bit during lin communication, and is always 0 when read. ? setting this bit to 1 triggers sbf transmission. ? set the uanstt bit after setting the uanpwr bit and uantxe bit to 1. sbf transmission trigger uanstt 0 1 sbf transmission trigger <7> 0 ? ? note pd70f3792, 70f3793, 70f3841, 70f3842 only caution do not set the uansrt and uanstt bits (to 1) during sbf reception (uansrf bit = 1).
v850es/jg3-l chapter 16 asynchronous serial interface a (uarta) r01uh0165ej0700 rev.7.00 page 561 of 1113 sep 22, 2011 (2/2) uansls2 1 1 1 0 0 0 0 1 uansls1 0 1 1 0 0 1 1 0 uansls0 1 0 1 0 1 0 1 0 13-bit output (initial value) 14-bit output 15-bit output 16-bit output 17-bit output 18-bit output 19-bit output 20-bit output sbf transmit length selection ? the output level of the txdan pin can be inverted by using the uantdl bit. ? this register can be set when the uanpwr bit or the uantxe bit is 0. this register can be set when the uanpwr bit or the uantxe bit is 0. normal output of transfer data inverted output of transfer data uantdl 0 1 transmit data level bit ? the input level of the rxdan pin can be inverted by using the uanrdl bit. ? this register can be set when the uanpwr bit or the uanrxe bit is 0. normal input of transfer data inverted input of transfer data uanrdl 0 1 receive data level bit (5) uartan status register (uanstr) the uanstr register is an 8-bit r egister that displays the uartan transfer status and reception error contents. this register can be read or written in 8-bit or 1-bi t units, but the uantsf bit is a read-only bit, while the uanpe, uanfe, and uanove bits can be both read and written. however, these bits can only be cleared by writing 0; they cannot be set by writing 1 (even if 1 is written to them, the previous value is retained). the conditions for clearing the uanstr register are shown below. table 16-3. conditions for clearing str register register/bit conditions for clearing uanstr register ? reset ? uanctl0.uanpwr = 0 uantsf bit ? uanctl0.uantxe = 0 uanpe, uanfe, uanove bits ? 0 write ? uanctl0.uanrxe = 0
v850es/jg3-l chapter 16 asynchronous serial interface a (uarta) r01uh0165ej0700 rev.7.00 page 562 of 1113 sep 22, 2011 uantsf the transmit shift register does not have data. ? when the uanpwr bit or the uantxe bit has been set to 0. ? when, following transfer completion, there was no next data transfer from uantx register the transmit shift register has data. (write to uantx register) uantsf 0 1 transfer status flag uanstr (n = 0 to 5) 0 0 0 0 uanpe uanfe uanove 6 5 4 3 <2> <1> after reset: 00h r/w address: ua0str fffffa04h, ua1str fffffa14h, ua2str fffffa24h, ua3str fffffa34h note , ua4str fffffa44h note , ua5str fffffa54h note the uantsf bit is always 1 when performing continuous transmission. when initializing the transmission unit, check that the uantsf bit is 0 before performing initialization. the transmit data is not guaranteed when initialization is performed while the uantsf bit is 1. ? when the uanpwr bit or the uanrxe bit has been set to 0. ? when 0 has been written the received parity bit does not match the specified parity. uanpe 0 1 parity error flag ? the operation of the uanpe bit is controlled by the settings of the uanctl0.uanps1 and uanctl0.uanps0 bits. ? once the uanpe bit is set (1), the value is retained until the bit is cleared (0). ? the uanpe bit can be read and written, but it can only be cleared by writing 0 to it; it cannot be set by writing 1 to it. when 1 is written to this bit, the previous value is retained. <7> <0> ? when the uanpwr bit or the uanrxe bit has been set to 0 ? when 0 has been written when no stop bit is detected during reception uanfe 0 1 framing error flag ? only the first bit of the receive data stop bits is checked, regardless of the value of the uanctl0.uansl bit. ? once the uanfe bit is set (1), the value is retained until the bit is cleared (0). ? the uanfe bit can be both read and written, but it can only be cleared by writing 0 to it; it cannot be set by writing 1 to it. when 1 is written to this bit, the previous value is retained. ? when the uanpwr bit or the uanrxe bit has been set to 0. ? when 0 has been written when receive data has been set to the uanrx register and the next receive operation is completed before that receive data has been read uanove 0 1 overrun error flag ? when an overrun error occurs, the data is discarded without the next receive data being written to the receive buffer. ? once the uanove bit is set (1), the value is retained until the bit is cleared (0). ? the uanove bit can be both read and written, but it can only be cleared by writing 0 to it; it cannot be set by writing 1 to it. when 1 is written to this bit, the previous value is retained. note pd70f3792, 70f3793, 70f3841, 70f3842only
v850es/jg3-l chapter 16 asynchronous serial interface a (uarta) r01uh0165ej0700 rev.7.00 page 563 of 1113 sep 22, 2011 (6) uartan receive data register (uanrx) the uanrx register is an 8-bit buffer r egister that stores paralle l data converted by the receive shift register. the data stored in the receive shift register is transfe rred to the uanrx register upon completion of reception of 1-character data. during lsb-first reception when the data length has been specified as 7 bits, the receive data is transferred to bits 6 to 0 of the uanrx register and the msb always becomes 0. during msb-first reception, the receive data is transferred to bits 7 to 1 of the ua nrx register and the lsb always becomes 0. when an overrun error (uanove) occurs, the receive data at this time is not transferred to the uanrx register and is discarded. this register is read-only, in 8-bit units. in addition to reset input, the uanrx register can be set to ffh by clearing the uanctl0.uanpwr bit to 0. uanrx (n = 0 to 5) 654321 after reset: ffh r address: ua0rx fffffa06h, ua1rx fffffa16h, ua2rx fffffa26h, ua3rx fffffa36h note , ua4rx fffffa46h note , ua5rx fffffa56h note 7 0 note pd70f3792, 70f3793, 70f3841, 70f3842 only
v850es/jg3-l chapter 16 asynchronous serial interface a (uarta) r01uh0165ej0700 rev.7.00 page 564 of 1113 sep 22, 2011 (7) uartan transmit data register (uantx) the uantx register is an 8-bit register used to set transmit data. writing transmit data to the uantx register with transmission enabled (uanctl0.uantxe bit = 1) triggers transmission. when transfer of the uantx register data to the uartan transmit shift register is complete, the transmission enable interrupt reques t signal (intuant) is generated. when 7-bit data is transmitted lsb-first, the data is transfe rred to bits 6 to 0 of the uantx register. when the data is transmitted msb-first, it is transferred to bits 7 to 1 of the uantx register. this register can be read or written in 8-bit units. reset sets this register to ffh. caution writing the uantx register with transmission enabled (uanpwr bit = 1 and uantxe bit = 1) triggers transmission. if the same value as the one immediately before is written, therefore, the same data is transmitted twice. to write new transmit data during processing of the preceding one, wait until the transmission enable interrupt request signal (intuant) has been generated. even if transmission is enabled after data is written to the uantx register with transmission disabled (uanpwr bit = 0 or uantxe bit = 0), transmission does not start. uantx (n = 0 to 5) 654321 after reset: ffh r/w address: ua0tx fffffa07h, ua1tx fffffa17h, ua2tx fffffa27h, ua3tx fffffa37h note , ua4tx fffffa47h note , ua5tx fffffa57h note 7 0 note pd70f3792, 70f3793, 70f3841, 70f3842 only
v850es/jg3-l chapter 16 asynchronous serial interface a (uarta) r01uh0165ej0700 rev.7.00 page 565 of 1113 sep 22, 2011 16.5 interrupt request signals the following two interrupt request signals are generated from uartan. ? reception complete interrupt request signal (intuanr) ? transmission enable interrupt request signal (intuant) the default priority for these two interrupt request signa ls is reception complete interrupt request signal then transmission enable interrupt request signal. table 16-4. interrupts and their default priorities interrupt request signal priority reception complete high transmission enable low (1) reception complete interrupt request signal (intuanr) when the data stored in the receive shi ft register is transferred to the ua nrx register with reception enabled, the reception complete interrupt request signal is generated. a reception complete interrupt request signal is also out put when a reception error occurs. therefore, when a reception complete interrupt request signal is acknowledged and the data is read, read the uanstr register and check that the rec eption result is not an error. no reception complete interrupt request signal is generated in the reception disabled status. (2) transmission enable interr upt request signal (intuant) if transmit data is transferred from the uantx register to the uartan transmit shift register with transmission enabled, the transmission enable interrupt request signal is generated.
v850es/jg3-l chapter 16 asynchronous serial interface a (uarta) r01uh0165ej0700 rev.7.00 page 566 of 1113 sep 22, 2011 16.6 operation 16.6.1 data format as shown in figure 16-5, one frame of transmit/receive data consists of a start bit, character bits, parity bit, and stop bit(s). specification of the character bit lengt h within 1 data frame, parity selection, specification of the stop bit length, and specification of msb-first/lsb-first transfe r are performed using the uanctl0 register. the uanopt0.uantdl bit is used to specify normal output/inverted output fo r the data to be transferred via the txdan pin. the uanopt0.uanrdl bit is used to specify normal input/inverted input for the data to be received via the rxdan pin. ? start bit ..................................... 1 bit ? character bits ........................... 7 bits/8 bits ? parity bit ................................... even parity/odd parity/0 parity/no parity ? stop bit ..................................... 1 bit/2 bits ? input logic ................................. normal input/inverted input ? output logic .............................. normal ou tput/inverted output ? communication direction .......... msb/lsb
v850es/jg3-l chapter 16 asynchronous serial interface a (uarta) r01uh0165ej0700 rev.7.00 page 567 of 1113 sep 22, 2011 figure 16-5. uarta transmit/receive data format (a) 8-bit data length, lsb first, even pa rity, 1 stop bit, transfer data: 55h d0 d1 d2 d3 d4 d5 d6 d7 1 data frame start bit parity bit stop bit (b) 8-bit data length, msb first, even pa rity, 1 stop bit, transfer data: 55h d7 d6 d5 d4 d3 d2 d1 d0 1 data frame start bit parity bit stop bit (c) 8-bit data length, msb first, even parity, 1 stop bit, transfer data : 55h, transmit/receive data inverted d7 d6 d5 d4 d3 d2 d1 d0 1 data frame start bit parity bit stop bit (d) 7-bit data length, lsb first, odd pa rity, 2 stop bits, transfer data: 36h d0 d1 d2 d3 d4 d5 d6 1 data frame start bit parity bit stop bit stop bit (e) 8-bit data length, lsb first, no pa rity, 1 stop bit, transfer data: 87h d0 d1 d2 d3 d4 d5 d6 d7 1 data frame start bit stop bit
v850es/jg3-l chapter 16 asynchronous serial interface a (uarta) r01uh0165ej0700 rev.7.00 page 568 of 1113 sep 22, 2011 16.6.2 uart transmission transmission is enabled by setting the uanctl0.uanpwr and uanctl0.uantxe bits to 1, and transmission is started by writing transmit data to the uantx register. t he start bit, parity bit, and stop bit are automatically added. since the cts (transmit enable signal) input pin is not pr ovided in uartan, use a port to check that reception is enabled at the transmit destination. the data in the uantx register is transferred to the uartan transmit shift register upon the start of transmission. a transmission enable interrupt request signal (intuant ) is generated upon completion of transmission of the data of the uantx register to the uartan transmit shift register, and the contents of the uartan transmit shift register are output to the txdan pin. writing the next transmit data to t he uantx register is enabled after the intuant signal is generated. figure 16-6. uart transmission start bit d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit intuant txdan remark lsb first
v850es/jg3-l chapter 16 asynchronous serial interface a (uarta) r01uh0165ej0700 rev.7.00 page 569 of 1113 sep 22, 2011 16.6.3 continuous transmission procedure writing transmit data to the uantx regi ster with transmission enabled triggers transmission. the data in the uantx register is transferred to the uartan transmit shift register, the transmission e nable interrupt request signal (intuant) is generated, and then shi fting is started. after the transmission enable interrupt request signal (intuant) is generated, the next trans mit data can be written to the uantx register. the timing of uartan transmit shift register transmission can be judged from the tr ansmission enable interrupt request signal (intuant). an efficient communication rate is realized by writing the data to be transmitted next to the uantx register during transfer. caution when initializing transmission during the exe cution of continuous transmission, make sure that the uanstr.uantsf bit is 0, then perform initializatio n. transmit data that is initialized when the uantsf bit is 1 cannot be guaranteed. figure 16-7. continuous transmission processing start register settings uantx write yes yes no no occurrence of transmission interrupt? note required number of writes performed? end note be sure to read the uanstr register after generation of the transmission enable interrupt request signal (intuant) to check whether a transmission error has occurred.
v850es/jg3-l chapter 16 asynchronous serial interface a (uarta) r01uh0165ej0700 rev.7.00 page 570 of 1113 sep 22, 2011 figure 16-8. continuous tran smission operation timing (a) transmission start txdan uantx intuant uantsf transmission shift register start data (1) data (1) data (2) data (2) data (1) data (3) parity stop start data (2) parity stop start (b) transmission end ff txdan uantx intuant uantsf start data (n ? 1) data (n ? 1) data (n ? 1) data (n) data (n) transmission shift register uanpwr or uantxe bit parity stop stop start data (n) parity parity stop
v850es/jg3-l chapter 16 asynchronous serial interface a (uarta) r01uh0165ej0700 rev.7.00 page 571 of 1113 sep 22, 2011 16.6.4 uart reception first, enable reception by executing the following operati ons and monitor the rxdan input to detect the start bit. ? specify the operating clock by using uarta control register 1 (uanctl1). ? specify the baud rate by using uarta control register 2 (uanctl2). ? specify the output logic level by using uarta option control register 0 (uanopt0). ? specify the communication direction, parity, data character length, and stop bit length by using uarta control register 0 (uanctl0). ? set the power bit and reception enable bit (uanpwr = 1 and uanrxe = 1). to change the communication direction, parity, data character lengt h, and/or stop bit length, clear the power bit (uanpwr = 0) or clear both the transmission enable bit and reception enable bit (uantxe = 0 and uanrxe = 0) beforehand. the level input to the rxdan pin is sampled by using the operating clock. if the falling edge is detected, sampling of data input to rxdan is started. if the data is low level half a bit after detection of the falling edge (indicated by v in figure 16-9), it is recognized as a start bit. when the start bit has been recognized, reception is started, and serial data is sequentially st ored in the receive shift register at the specified baud rate. when the stop bit has been received, the reception complete interrupt reque st signal (intuanr) is genera ted and, at the same time, the data stored in the receive shift register is tr ansferred to the receive data register (uanrx). if an overrun error occurs (uanove = 1), however, the receive data is not transferred to uanrx, but is discarded. on the other hand, even if a parity error (uanpe = 1) or fr aming error (uanfe = 1) occurs, reception continues and the receive data is transferred to the uanrx register. no matter which reception error has occurred, the intuanr interrupt is generated afte r reception is complete. figure 16-9. uart reception d0 d1 d2 d3 d4 d5 d6 d7 intuanr uanrx rxdan start bit parity bit stop bit
v850es/jg3-l chapter 16 asynchronous serial interface a (uarta) r01uh0165ej0700 rev.7.00 page 572 of 1113 sep 22, 2011 cautions 1. be sure to read th e uanrx register even when a recep tion error occurs. if the uanrx register is not read, an overr un error occurs during reception of the next data, and reception errors continue occurring indefinitely. 2. reception is performed assuming that ther e is only one stop bit. a second stop bit is ignored. 3. when reception is complete d, read the uanrx register after the reception complete interrupt request signal (intuanr) has been gene rated, and clear the uanrxe bit to 0. if the uanrxe bit is cleared to 0 be fore the intuanr signal is gene rated, the read value of the uanrx register cannot be guaranteed. 4. if the receive completi on processing (intuanr signal genera tion) of uartan conflicts with setting the uanpwr bit or uanrxe bit to 0, the intuanr signal may be generated in spite of there being no data stor ed in the uanrx register. to complete reception without waiting for int uanr signal generation, be sure to clear (0) the interrupt request flag (uanrif) of the uan ric register, after setting (1) the interrupt mask flag (uanrmk) of the interrupt control register (uanric) and then set (1) the uanpwr bit or uanrxe bit to 0.
v850es/jg3-l chapter 16 asynchronous serial interface a (uarta) r01uh0165ej0700 rev.7.00 page 573 of 1113 sep 22, 2011 16.6.5 reception errors three types of errors can occur during reception: parit y errors, framing errors, and overrun errors. the data reception result error flag is set in the uanstr register and a reception complete interrupt request signal (intuanr) is output when an error occurs. it is possible to ascertain which error occurred during reception by reading the contents of the uanstr register. clear the reception error flag by writing 0 to it after reading it. figure 16-10. reading receive data start no intuanr signal generated? error occurs? end yes no yes error processing read uanrx register read uanstr register caution when the intuanr signal is generated, the uanstr register must be read to check for errors.
v850es/jg3-l chapter 16 asynchronous serial interface a (uarta) r01uh0165ej0700 rev.7.00 page 574 of 1113 sep 22, 2011 table 16-5. reception error causes error flag reception error cause uanpe parity error the received parity bit does not match the setting. uanfe framing error the stop bit was not detected. uanove overrun error reception of the next data was completed before data was read from the receive buffer. when a reception error occurs, perform the following procedure according to the kind of error. ? parity error if false data is received due to problems such as noise on the reception line, discard the received data and retransmit. ? framing error a baud rate error may have occurred between the reception side and transmission side or a start bit may have been erroneously detected. since this is a fatal erro r for the communication format, check that operation on the transmission side has stopped, initialize both sides, and then start the communication again. ? overrun error 1 frame of data is discarded because the next reception is completed before data was read from the receive buffer. if this data was needed, retransmit the data. caution in reception, be sure to read the uanstr register before completion of the next reception to check whether an error has occurred. if an error has occurred, perform error processing.
v850es/jg3-l chapter 16 asynchronous serial interface a (uarta) r01uh0165ej0700 rev.7.00 page 575 of 1113 sep 22, 2011 16.6.6 parity types and operations the parity bit is used to detect bit errors in the communi cation data. normally the same parity is used on the transmission side and the reception side. in the case of even parity and odd parity, it is possible to detect odd-count bit errors. in the case of 0 parity and no parity, errors cannot be detected. (a) even parity (i) during transmission the number of bits whose value is ?1? among the transm it data, including the parity bit, is controlled so as to be an even number. the parity bit values are as follows. ? odd number of bits whose value is ?1? among transmit data: 1 ? even number of bits whose value is ?1? among transmit data: 0 (ii) during reception the number of bits whose value is ?1? among the rece ption data, including the parity bit, is counted, and if it is an odd number, a parity error is output. (b) odd parity (i) during transmission opposite to even parity, the number of bits whose value is ?1? among the transmit data, including the parity bit, is controlled so that it is an odd nu mber. the parity bit values are as follows. ? odd number of bits whose value is ?1? among transmit data: 0 ? even number of bits whose value is ?1? among transmit data: 1 (ii) during reception the number of bits whose value is ?1? among the receiv e data, including the parity bit, is counted, and if it is an even number, a parity error is output. (c) 0 parity during transmission, the parity bit is always made 0, regardless of the transmit data. during reception, a parity bit check is not performed. therefore, no parity error occurs, regardless of whether the parity bit is 0 or 1. (d) no parity no parity bit is added to the transmit data. reception is performed assuming that there is no parity bit. no parity error occurs since there is no parity bit. caution when using the lin function, fix the uanps1 and uanps0 bits of the uanctl0 register to 0, 0.
v850es/jg3-l chapter 16 asynchronous serial interface a (uarta) r01uh0165ej0700 rev.7.00 page 576 of 1113 sep 22, 2011 16.6.7 lin transmissi on/reception format the v850es/jg3-l has an sbf (sync break field) transmissi on/reception control function to enable use of the lin function. remark lin stands for local interconnect network and is a low-speed (1 to 20 kbps) serial communication protocol intended to reduce co sts of automotive networks. lin communication is single-master communication, and up to 15 slaves can be connected to the master. the lin slaves are used to control the switches , actuators, and sensors, and these are connected to the lin master via the lin network. normally, the lin master is connected to a network such as can (controller area network). in addition, the lin bus uses a single-wire method and is connected to the nodes via a transceiver that complies with iso9141. in the lin protocol, the master transmits a frame with baud rate information and the slave receives it and corrects the baud rate error. therefore, comm unication is possible when the baud rate error in the slave is 15% or less. figures 16-11 and 16-12 outline the transmission and reception manipulations of lin. figure 16-11. lin transmission format lin bus wake-up signal frame sync break field (sbf) sync field id field data field data field check sum field intuant interrupt txdan (output) note 3 8 bits note 1 note 2 13 bits sbf transmission note 4 55h transmission data transmission data transmission data transmission data transmission notes 1. the interval between each field is controlled by software. 2. sbf output is performed by hardware. the output width is the bit length set by the uanopt0.uansbl2 to uanopt0.uansbl0 bits. if even finer output width adjustments are required, such adjustments can be performed using the uanctln.uanbrs7 to uanctln.uanbrs0 bits. 3. 80h transfer in the 8-bit mode is substituted for the wakeup signal frame. 4. a transmission enable interrupt request signal (intuant ) is output at the star t of each transmission. the intuant signal is also output at the start of each sbf transmission.
v850es/jg3-l chapter 16 asynchronous serial interface a (uarta) r01uh0165ej0700 rev.7.00 page 577 of 1113 sep 22, 2011 figure 16-12. lin reception format reception interrupt (intuanr) edge detection capture timer disable disable enable rxdan (input) enable note 2 sbf reception note 3 note 4 note 1 sf reception id reception data reception data reception note 5 data reception lin bus wake-up signal frame sync break field (sbf) sync field id field data field data field check sum field notes 1. the wakeup signal is detected by the pin edge detec tor, uartan is enabled, and the sbf reception mode is set. 2. reception is performed until detec tion of the stop bit. upon detection of sbf reception of 11 or more bits, it is judged as normal sbf reception end, and an interrupt signal is output. upon detection of sbf reception of less than 11 bits, it is judged as an sbf reception error, no interrupt signal is output, and the mode returns to the sbf reception mode. 3. if sbf reception ends normally, an interrupt request signal is output. the timer is enabled by an sbf reception complete interrupt. moreover, error detection for the uanstr.uanove, uanstr.uanpe, and uanstr.uanfe bits is suppressed and uart communication error detection processing and data transfer of the uartan receive shift register and uanrx register is not performed. the uartan receive shift register holds the initial value, ffh. 4. the rxdan pin is connected to ti (capture input) of the timer and the transfer rate is calculated. the value of the uanctl2 register obtained by correctin g the baud rate error after uarta enable goes low is set again, causing the status to become the reception status. 5. a check-sum field is identified by software. uartan is initialized following reception of the check-sum field, and the processing for re-specifying the sbf reception mode is performed, also by software.
v850es/jg3-l chapter 16 asynchronous serial interface a (uarta) r01uh0165ej0700 rev.7.00 page 578 of 1113 sep 22, 2011 16.6.8 sbf transmission when the uanctl0.uanpwr bit and uanctl0.uantxe bit are 1, the transmission en abled status is entered, and sbf transmission is started by setting the sbf tr ansmission trigger (uanopt0.uanstt bit) to 1. thereafter, a low level signal having a length of 13 to 20 bits, as specified by the uanopt0.uansls2 to anopt0.uansls0 bits, is output. a transmission enable in terrupt request signal (intuant) is generated upon the start of sbf transmission. following the end of sbf tr ansmission, the uanstt bit is automatically cleared. transmission is suspended until the data to be transmitted ne xt is written to the uantx register, or until the sbf transmission trigger (uanstt bit) is set. figure 16-13. example of sbf transmission intuant interrupt 12345678910111213 setting of uanstt bit txdan stop bit
v850es/jg3-l chapter 16 asynchronous serial interface a (uarta) r01uh0165ej0700 rev.7.00 page 579 of 1113 sep 22, 2011 16.6.9 sbf reception the reception enabled status is entered by setting the uanctl0.ua npwr bit to 1 and then setting the uanctl0.uanrxe bit to 1. the sbf reception wait status is set by setting the sbf reception trigger (uanopt0.uanstr bit) to 1. in the sbf reception wait status, sim ilarly to the uart reception wait stat us, the rxdan pin is monitored and start bit detection is performed. following detection of the start bit, rec eption is started and the internal count er increments according to the set baud rate. when a stop bit is received, if the sbf width is 11 or more bits, it is judged as normal processing and a reception complete interrupt request signal (i ntuanr) is output. the uanopt0.uans rf bit is automatically cleared and sbf reception ends. error detection for the uanstr.uanove, uanstr.uanpe, and uanstr.uanfe bits is suppressed and uart communication error detection processing is not performed. moreover, data transfer of the uartan reception shift register and uanrx register is not performed and ffh, the initial value, is held. if the sbf width is 10 or fewer bits, reception is terminated as an er ror, an interrupt is not generated, and the sbf reception mode is restored. the uansrf bit is not cleared at this time. cautions 1. if sbf is tran smitted during data reception, a framing error occurs. 2. do not set the sbf reception trigger bi t (uansrt) and sbf transmission trigger bit (uanstt) to 1 during sbf reception (uansrf = 1). figure 16-14. sbf reception (a) normal sbf reception (detection of st op bit after more than 10.5 bits) uansrf rxdan 123456 11.5 7 8 9 10 11 intuanr interrupt (b) sbf reception error (detection of st op bit after 10.5 or fewer bits) uansrf rxdan 123456 10.5 78910 intuanr interrupt
v850es/jg3-l chapter 16 asynchronous serial interface a (uarta) r01uh0165ej0700 rev.7.00 page 580 of 1113 sep 22, 2011 16.6.10 receive data noise filter this filter samples signals received via the rxdan pi n using the base clock supplied by the dedicated baud rate generator. when the same sampling value is read twice, the match detector output changes and the rxdan signal is sampled as the input data. therefore, data not exceeding 1 clock cycle width is judged to be noise and is not delivered to the internal circuit (see figure 16-16 ). see 16.7 (1) (a) base clock for details of the base clock. moreover, since the circuit is as shown in figure 16-15, the processing that goes on withi n the receive operation is delayed by 3 clocks in relation to the external signal status. figure 16-15. noise filter circuit match detector in base clock (f uclk ) rxdan qin ld_en q internal signal c internal signal b in q internal signal a figure 16-16. timing of rxdan signal judged as noise internal signal b base clock rxdan (input) internal signal c mismatch (judged as noise) internal signal a mismatch (judged as noise) match match
v850es/jg3-l chapter 16 asynchronous serial interface a (uarta) r01uh0165ej0700 rev.7.00 page 581 of 1113 sep 22, 2011 16.7 dedicated baud rate generator the dedicated baud rate generator consists of a source clock selector block and an 8-bit programmable counter block, and generates a serial clock during transmission and reception using uartan. regarding the serial clock, a dedicated baud rate generator output can be selected for each channel. there is an 8-bit counter for transmissi on and another one for reception. (1) baud rate generato r configuration figure 16-17. configuration of baud rate generator f uclk selector uanpwr 8-bit counter match detector baud rate uanctl2: uanbrs7 to uanbrs0 1/2 uanpwr, uantxen bus (or uanrxe bit) uanctl1: uancks3 to uancks0 f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 f xx /512 f xx /1024 ascka0 note f uclk /k note only uarta0 is valid; setting uarta1 to uarta5 are prohibited. remarks 1. n = 0 to 5 2. f xx : main clock frequency 3. f uclk : base clock frequency 4. f uclk /k: serial clock (k: brgcn register value) (a) base clock when the uanctl0.uanpwr bit is 1, the cl ock selected by the uanctl1.uancks3 to uanctl1.uancks0 bits is supplied to the 8-bit counter. this clock is called the base clock (f uclk ). (b) serial clock generation a serial clock can be generated by setting the uanctl1 register and the uanctl2 register (n = 0 to 2). the base clock is selected by uanctl1. uancks3 to uanctl1.uancks0 bits. the frequency division value for the 8-bit counter can be set using the uanctl2.uanbrs7 to uanctl2.uanbrs0 bits. the baud rate clock is generated by dividing the serial clock by two.
v850es/jg3-l chapter 16 asynchronous serial interface a (uarta) r01uh0165ej0700 rev.7.00 page 582 of 1113 sep 22, 2011 (2) uartan control register 1 (uanctl1) the uanctl1 register is an 8-bit register that selects the uartan base clock. this register can be read or written in 8-bit units. reset sets this register to 00h. caution clear the uanctl0.uanpwr bit to 0 before rewriting the uanctl1 register. 0 uanctl1 (n = 0 to 5) 0 0 0 uancks3 uancks2 uancks1 uancks0 654321 after reset: 00h r/w address: ua0ctl1 fffffa01h, ua1ctl1 fffffa11h, ua2ctl1 fffffa21h, ua3ctl1 fffffa31h note1 , ua4ctl1 fffffa41h note1 , ua5ctl1 fffffa51h note1 7 0 f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 f xx /512 f xx /1,024 external clock note2 (ascka0 pin) setting prohibited uancks2 0 0 0 0 1 1 1 1 0 0 0 0 uancks3 0 0 0 0 0 0 0 0 1 1 1 1 base clock (f uclk ) selection uancks1 0 0 1 1 0 0 1 1 0 0 1 1 uancks0 0 1 0 1 0 1 0 1 0 1 0 1 other than above notes1. pd70f3792, 70f3793, 70f3841, 70f3842 only 2. only uarta0 is valid; setting uarta1 to uarta5 are prohibited. remark f xx : main clock frequency
v850es/jg3-l chapter 16 asynchronous serial interface a (uarta) r01uh0165ej0700 rev.7.00 page 583 of 1113 sep 22, 2011 (3) uartan control register 2 (uanctl2) the uanctl2 register is an 8-bit register that selects the baud rate (serial transfer speed) clock of uartan. the baud rate clock is generated by dividing the se rial clock specified by this register by two. this register can be read or written in 8-bit units. reset sets this register to ffh. caution either clear the uanctl0.uanpwr bit to 0, or clear the uantxe and uanrxe bits to 0, 0, before rewriting the uanctl2 register. uanbrs7 uanctl2 (n = 0 to 5) uanbrs6 uanbrs5 uanbrs4 uanbrs3 uanbrs2 uanbrs1 uanbrs0 654321 after reset ffh r/w address: ua0ctl2 fffffa02h, ua1ctl2 fffffa12h, ua2ctl2 fffffa22h, ua3ctl2 fffffa32h note , ua4ctl2 fffffa42h note , ua5ctl2 fffffa52h note 7 0 uan brs7 0 0 0 0 : 1 1 1 1 uan brs6 0 0 0 0 : 1 1 1 1 uan brs5 0 0 0 0 : 1 1 1 1 uan brs4 0 0 0 0 : 1 1 1 1 uan brs3 0 0 0 0 : 1 1 1 1 uan brs2 0 1 1 1 : 1 1 1 1 uan brs1 0 0 1 : 0 0 1 1 uan brs0 0 1 0 : 0 1 0 1 default (k) 4 5 6 : 252 253 254 255 serial clock f uclk /4 f uclk /5 f uclk /6 : f uclk /252 f uclk /253 f uclk /254 f uclk /255 setting prohibited note pd70f3792, 70f3793, 70f 3841, 70f3842 only remark f uclk : clock frequency selected by the uanctl1.uancks3 to uanctl1.uancks0 bits
v850es/jg3-l chapter 16 asynchronous serial interface a (uarta) r01uh0165ej0700 rev.7.00 page 584 of 1113 sep 22, 2011 (4) baud rate the baud rate is obtained by the following equation. baud rate = [bps] when using the internal clock, the equation will be as follows (when using the ascka0 pin input as the clock for uarta0, calculate using the above equation). baud rate = [bps] remark f uclk = frequency of base clock selected by the uanctl1.uancks3 to uanctl1.uancks0 bits f xx : main clock frequency m = value set using the uanctl1.uancks3 to uanctl1.uancks0 bits (m = 0 to 10) k = value set using the uanctl2.uanbrs7 to uanctl2.uanbrs0 bits (k = 4 to 255) the baud rate error is obtained by the following equation. error (%) = ? 1 100 [%] = ? 1 100 [%] when using the internal clock, the equation will be as follows (when using the ascka0 pin input as the clock for uarta0, calculate the baud rate error using the above equation). error (%) = ? 1 100 [%] cautions 1. the baud rate erro r during transmission must be with in the error tolerance on the receiving side. 2. the baud rate error during reception must satisfy the range indicated in (5) allowable baud rate range dur ing reception. f uclk 2 k actual baud rate (baud rate with error) target baud rate (correct baud rate) f xx 2 m+1 k f uclk 2 k target baud rate f xx 2 m+1 k target baud rate
v850es/jg3-l chapter 16 asynchronous serial interface a (uarta) r01uh0165ej0700 rev.7.00 page 585 of 1113 sep 22, 2011 to set the baud rate, perform the following calculatio n for setting the uanctl1 and uanctl2 registers (when using the internal clock). <1> set k to fxx/(2 target baud rate) and m to 0. <2> if k is 256 or greater (k 256), reduce k to half (k/2) and increment m by 1 (m + 1). <3> repeat step <2> until k becomes less than 256 (k < 256). <4> round off the first decimal point of k to the nearest whole number. if k is 256 after round-off, reduce k to half (k/2) and increment m by 1 (m + 1) to obtain k = 128. <5> set the value of m to the uanctl1 register and the value of k to the uanctl2 register. example: when f xx = 20 mhz and target baud rate = 153,600 bps <1> k = 20,000,000/(2 153,600) = 65.10?, m = 0 <2>, <3> k = 65.10? < 256, m = 0 <4> set value of uanctl2 register: k = 65 = 41h, set value of uanctl1 register: m = 0 actual baud rate = 20,000,000/(2 65) = 153,846 [bps] baud rate error = {20,000,000/(2 65 153,600) ? 1} 100 = 0.160 [%] representative examples of baud rate settings are shown below. table 16-6. baud rate generator setting data f xx = 20 mhz f xx = 16 mhz f xx = 10 mhz baud rate (bps) uanctl1 uanctl2 err (%) uanctl1 uanctl2 err (%) uanctl1 uanctl2 err (%) 300 08h 82h 0.16 07h d0h 0.16 07h 82h 0.16 600 07h 82h 0.16 06h d0h 0.16 06h 82h 0.16 1200 06h 82h 0.16 05h d0h 0.16 05h 82h 0.16 2400 05h 82h 0.16 04h d0h 0.16 04h 82h 0.16 4800 04h 82h 0.16 03h d0h 0.16 03h 82h 0.16 9600 03h 82h 0.16 02h d0h 0.16 02h 82h 0.16 19200 02h 82h 0.16 01h d0h 0.16 01h 82h 0.16 31250 01h a0h 0 01h 80h 0 00h a0h 0 38400 01h 82h 0.16 00h d0h 0.16 00h 82h 0.16 76800 00h 82h 0.16 00h 68h 0.16 00h 41h 0.16 153600 00h 41h 0.16 00h 34h 0.16 00h 21h ? 1.36 312500 00h 20h 0 00h 1ah ? 1.54 00h 10h 0 625000 00h 10h 0 00h 0dh ? 1.54 00h 08h 0 remark f xx : main clock frequency err: baud rate error (%)
v850es/jg3-l chapter 16 asynchronous serial interface a (uarta) r01uh0165ej0700 rev.7.00 page 586 of 1113 sep 22, 2011 (5) allowable baud rate ra nge during reception the baud rate error range at the destination that is allowable during reception is shown below. caution the baud rate error indicated below is a th eoretical value. in practice, the signal might be distorted, or communication might not be performed normally even if the error is within the allowable range. therefore, th e error must be minimized. figure 16-18. allowable baud rate range during reception bl 1 data frame (11 bl = fl) flmin flmax uartn data frame length start bit bit 0 bit 1 bit 7 parity bit minimum allowable data frame length maximum allowable data frame length stop bit start bit bit 0 bit 1 bit 7 parity bit latch timing stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit remark n = 0 to 5 as shown in figure 16-18, the receive data latch timi ng is determined by the counter set using the uanctl2 register following start bit detection. the transmit data can be received normally if up to the last data (stop bit) can be received in time for this latch timing. when this is applied to 11-bit reception, t he following is the theoretical result. bl = (brate) ? 1 brate: uartan baud rate (n = 0 to 2) k: setting value of uanctl2.uanbrs7 to uanctl2.uanbrs0 bits (n = 0 to 2) bl: 1-bit data length fl: length of 1 data frame latch timing margin: 2 clock cycles minimum allowable data frame length: flmin = 11 bl ? bl = bl k ? 2 2k 21k + 2 2k
v850es/jg3-l chapter 16 asynchronous serial interface a (uarta) r01uh0165ej0700 rev.7.00 page 587 of 1113 sep 22, 2011 therefore, the maximum baud rate that can be re ceived by the destination is as follows. brmax = (flmin/11) ? 1 = brate similarly, obtaining the maximum allowable data frame length yields the following. flmax = 11 bl ? bl = bl flmax = bl 11 therefore, the minimum baud rate that can be received by the destination is as follows. brmin = (flmax/11) ? 1 = brate obtaining the allowable baud rate error for uartan and the destination from the above-described equations yields the following. table 16-7. maximum/minimum allowa ble baud rate error (11-bit length) division ratio (k) maximum allowable baud rate error minimum allowable baud rate error 4 +2.32% ? 2.43% 8 +3.53% ? 3.61% 20 +4.26% ? 4.31% 50 +4.56% ? 4.58% 100 +4.66% ? 4.67% 255 +4.72% ? 4.73% remarks 1. the reception accuracy depends on the bit count in 1 frame, the base clock frequency (f uclk ), and the division ratio (k). the higher the base clock frequency (f uclk ) and the larger the division ratio (k), the higher the accuracy. 2. k: setting value of uanctl2.uanbrs7 to uanctl2.uanbrs0 bits (n = 0 to 2) 10 11 k + 2 2 k 21k ? 2 2 k 21k ? 2 20 k 22k 21k + 2 20k 21k ? 2
v850es/jg3-l chapter 16 asynchronous serial interface a (uarta) r01uh0165ej0700 rev.7.00 page 588 of 1113 sep 22, 2011 (6) data frame length durin g continuous transmission in continuous transmission, the data frame length from t he stop bit to the next start bit is 2 base clock cycles longer than usual. however, timing initialization is per formed via start bit detection by the receiving side, so this has no influence on the transfer result. figure 16-19. data frame length during continuous transmission start bit bit 0 bit 1 bit 7 parity bit stop bit bl 1 data frame (fl) bl bl bl bl bl bl blstp start bit of 2nd byte start bit bit 0 assuming a 1 bit data length of bl; a stop bit l ength of blstp; and a base clock frequency of f uclk , we obtain the following equation. blstp = bl + 2/f uclk therefore, the transfer rate during continuous transmission is as follows. data frame length = 11 bl + (2/f uclk )
v850es/jg3-l chapter 16 asynchronous serial interface a (uarta) r01uh0165ej0700 rev.7.00 page 589 of 1113 sep 22, 2011 16.8 cautions (1) when the clock supply to uartan is stopped (for example, in idle1, id le2, or stop mode), the operation stops with each register retaining the value it had im mediately before the clock supply was stopped. the txdan pin output also holds and outputs the value it h ad immediately before the clock supply was stopped. however, the operation is not guaranteed after the cloc k supply is resumed. therefore, after the clock supply is resumed, the circuits should be initia lized by setting the uanctl0.uanpwr, uanctl0.uanrxen, and uanctl0.uantxen bits to 0, 0, 0. (2) the rxda1 and kr7 pins must not be used at the same time. when using the rxda1 pin, do not use the kr7 pin. when using the kr7 pin, do not use the rxda1 pin. (it is recommended to set the pfc91 bit to 1 and clear pfce91 bit to 0.) (3) in uartan, the interrupt caused by a communicati on error does not occur. when transferring transmit data and receive data using dma transfer, error processing ca nnot be performed even if e rrors (parity, overrun, framing) occur during transfer. either read the uans tr register after dma transfer has been completed to make sure that there are no errors, or read the uanstr register during communication to check for errors. (4) rxda0 and intp7 use the same pin. to use the pin for the rxda0 function, disable edge detection for intp7 (intf3.intf31 bit = 0, intr3.intr31 bit = 0). (5) start up uartan in the following sequence. <1> set the uanctl0.uanpwr bit to 1. <2> set the ports. <3> set the uanctl0.uantxe bit to 1 and the uanctl0.uanrxe bit to 1. (6) stop uartan in the following sequence. <1> set the uanctl0.uantxe bit to 0 and the uanctl0.uanrxe bit to 0. <2> set the ports and set the uanctl0.uanpwr bit to 0 (it is not a problem if the port settings are not changed). (7) in transmit mode (uanctl0.uanpwr bit = 1 and ua nctl0.uantxe bit = 1), do not overwrite the same value to the uantx register by software because transmis sion starts by writing to this register. to transmit the same value continuously, overwrite the same value. (8) in continuous transmission, the period from the stop bit to the next start bit is 2 base clock cycles longer than usual. however, the reception side initializes the timing by detecting the start bit, so the reception result is not affected. (9) uarta cannot identify the start bit if low level signals are continuously input to the rxdan pin.
v850es/jg3-l chapter 17 asynchronous serial interface c (uartc) ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 590 of 1113 sep 22, 2011 chapter 17 asynchronous serial interface c (uartc) ( pd70f3792, 70f3793, 70f3841, 70f3842) the pd70f3792, 70f3793, 70f3841, 70f3842 have a 1-channel uartc. 17.1 features { on-chip dedicated baud rate generator { transfer rate: 300 bps to 625 kbps (using dedicated baud rate generator) { full-duplex communication { double buffer configuration internal uartc0 receive data register (uc0rx) internal uartc0 transmit data register (uc0tx) { reception error detection function ? parity error ? framing error ? overrun error { interrupt sources: 2 ? reception complete interrupt (intuc0r): this inte rrupt occurs upon transfer of receive data from the receive shift register to the receive data register after serial transfer completion, in the reception enabled status. ? transmission enable interrupt (intuc0t): this interrupt occurs upon transfer of transmit data from the transmit data register to the transmit shift register in the transmission enabled status. (continuous transmission is possible.) { character length: 7 to 9 bits { parity function: odd, even, 0, none { transmission stop bit: 1, 2 bits { msb-/lsb-first transfer selectable { internal digital noise filter { inverted input/output of transmit/receive data possible { sbf (sync break field) transmission/reception in the li n (local interconnect network) communication format ? 13 to 20 bits selectable for sbf transmission ? recognition of 11 bits or more possible for sbf reception ? sbf reception flag provided
v850es/jg3-l chapter 17 asynchronous serial interface c (uartc) ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 591 of 1113 sep 22, 2011 17.2 configuration uartc0 includes the following hardware. table 17-1. configuration of uartc0 item configuration registers uartc0 control register 0 (uc0ctl0) uartc0 control register 1 (uc0ctl1) uartc0 control register 2 (uc0ctl2) uartc0 option control register 0 (uc0opt0) uartc0 option control register 1 (uc0opt1) uartc0 status register (uc0str) uartc0 receive shift register uartc0 receive data register (uc0rx) uartc0 transmit shift register uartc0 transmit data register (uc0tx) the block diagram of the uartc0 is shown below. figure 17-1. block diagram of uartc0 internal bus internal bus uartc0 receive shift register uc0rx filter selector uc0tx uartc0 transmit shift register transmission controller reception controller selector baud rate generator baud rate generator intuc0r intuc0t txdc0 rxdc0 f xx to f xx /2 10 reception unit transmission unit clock selector uc0opt0 uc0ctl1 uc0ctl2 uc0str uc0ctl0 remark for the configuration of t he baud rate generator, see figure 17-15 .
v850es/jg3-l chapter 17 asynchronous serial interface c (uartc) ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 592 of 1113 sep 22, 2011 (1) uartc0 control register 0 (uc0ctl0) the uc0ctl0 register is an 8-bit register used to specify the operation of uartc0. (2) uartc0 control register 1 (uc0ctl1) the uc0ctl1 register is an 8-bit regi ster used to select the base clock (f uclk ) for uartc0. (3) uartc0 control register 2 (uc0ctl2) the uc0ctl2 register is an 8-bit register used with the uc0ctl1 register to generate the baud rate for uartc0. (4) uartc0 option control register 0 (uc0opt0) the uc0opt0 register is an 8-bit register used to control sbf transmission/reception in the lin communication format and the level of the transmission/reception signals for the uartc0. (5) uartc0 option control register 1 (uc0opt1) the uc0opt1 register is an 8-bit register used to c ontrol 9-bit length serial transfer for the uartc0. (6) uartc0 status register (uc0str) the uc0str register is an 8-bit regist er that indicates the contents of a reception error. each one of the reception error flags is set (to 1) upon the occurrence of a reception error. (7) uartc0 receive shift register this is a shift register used to convert the serial data input to the rxdc0 pin into parallel data. upon reception of 1-character data and dete ction of the stop bit, the receive data is transferred to the uc0rx register. this register cannot be manipulated directly. (8) uartc0 receive data register (uc0rx) the uc0rx register is an 8-bit buffer register that holds receive data. in the reception enabled status, receive data is transfe rred from the uartc0 receive shift register to the uc0rx register in synchronization with the comple tion of shift-in processing of 1 character. transfer to the uc0rx register also causes the recept ion complete interrupt request signal (intuc0r) to be output. (9) uartc0 transmit shift register the transmit shift register is a shift register used to convert the parallel data transferred from the uc0tx register into serial data. when 1-character data is transferred from the uc0tx regi ster, the shift register data is output from the txdc0 pin. this register cannot be manipulated directly. (10) uartc0 transmit data register (uc0tx) the uc0tx register is an 8-bit transmit data buffer. transmission starts when transmit data is written to the uc0tx register. when data can be wri tten to the uc0tx register (when 1- character data is transferred from the uc0tx register to the uartc0 transmit shift regi ster), the transmission enable interrupt request signal (intuc0t) is generated.
v850es/jg3-l chapter 17 asynchronous serial interface c (uartc) ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 593 of 1113 sep 22, 2011 17.2.1 pin functions of each channel the rxdc0 andtxdc0 pins used by uartc in the pd70f3792, 70f3793, 70f38 41, 70f3842 are used for other functions as shown in table 17-2. to use these pi ns for uartc, set the related registers as described in table 4-15 settings when pins ar e used for alternate functions . table 17-2. pins used by uartc pin no. channel gc f1 port uartc reception input uartc transmission output other functions 50 j11 p97 rxdc0 ? a7/sib7/tip20/top20 uartc0 49 k11 p96 ? txdc0 a6/tip21/top21 remark gc: 100-pin plastic lqfp (fine pitch) (14 14) f1: 121-pin plastic fbga (8 8)
v850es/jg3-l chapter 17 asynchronous serial interface c (uartc) ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 594 of 1113 sep 22, 2011 17.3 mode switching of uartc and other serial interfaces 17.3.1 uartc0 and csib1 mode switching in the pd70f3792, 70f3793, 70f3841 and 70f 3842, csib1 and uartc0 share t he same pins and therefore cannot be used simultaneously. set uartc0 in advance, using the pmc9 and pfc9 registers, before use. caution the transmit/receive operation of csif4 and uartc0 is not guaranteed if these functions are switched during transmission or reception. be sure to disable the one that is not used. figure 17-2. csif4 and uartc0 mode switch settings pmc9 after reset: 00h r/w address: fffff462h pmc97 pmc96 pmc95 pmc94 pmc93 pmc92 pmc91 pmc90 pfc9 after reset: 00h r/w address: fffff472h pfc97 pfc96 pfc95 pfc94 pfc93 pfc92 pfc91 pfc90 pfce97 pfce96 pfce95 pfce94 pfce93 pfce92 pfce91 pfce90 pfce9 after reset: 00h r/w address: fffff712h port i/o mode sib1 (csib1)/rxdc0 (uartc) note pmc97 0 1 operation mode pfce97 0 0 pfc97 0 1 note sib1 and rxdc0 are alternate functions. wh en using the pin as the sib1 pin, disable rxdc0 pin detection, which is the alternate function. (clear the uc0ctl0.uc0pwr bit to 0.) also, when us ing the pin as the rxdc0 pin, disable sib1 pin, which is the alternate function . (clear the cb1ctl0.cb1pwr bit to 0.) remark = don?t care
v850es/jg3-l chapter 17 asynchronous serial interface c (uartc) ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 595 of 1113 sep 22, 2011 17.4 registers (1) uartc0 control register 0 (uc0ctl0) the uc0ctl0 register is an 8-bit register that c ontrols the uartc0 serial transfer operation. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 10h. (1/2) uc0pwr disable uartc0 operation (uartc0 reset asynchronously) enable uartc0 operation uc0pwr 0 1 uartc0 operation control uc0ctl0 uc0txe uc0rxe uc0dir uc0ps1 uc0ps0 uc0cl uc0sl <6> <5> <4> 3 2 1 after reset: 10h r/w address: fffffaa0h the uartc0 operation is controlled by the uc0pwr bit. the txdc0 pin output is fixed to high level by clearing the uc0pwr bit to 0 (fixed to low level if uc0opt0.uc0tdl bit = 1). disable transmission operation enable transmission operation uc0txe 0 1 transmission operation enable ? to start transmission, set the uc0pwr bit to 1 and then set the uc0txe bit to 1. to stop transmission, clear the uc0txe bit to 0 and then uc0pwr bit to 0. ? to initialize the transmission unit, clear the uc0txe bit to 0, wait for two cycles of the base clock, and then set the uc0txe bit to 1 again. otherwise, initialization may not be executed (for the base clock, see 17.7 (1) (a) base clock ). ? when uartc0 operation is enabled (uc0pwr bit = 1) and the uc0txe bit is set to 1, transmission is enabled after at least two cycles of the base clock (f uclk ) have elapsed. disable reception operation enable reception operation uc0rxe 0 1 reception operation enable ? to start reception, set the uc0pwr bit to 1 and then set the uc0rxe bit to 1. to stop reception, clear the uc0rxe bit to 0 and then uc0pwr bit to 0. ? to initialize the reception unit, clear the uc0rxe bit to 0, wait for two cycles of the base clock, and then set the uc0rxe bit to 1 again. otherwise, initialization may not be executed (for the base clock, see 17.7 (1) (a) base clock ). ? when uartc0 operation is enabled (uc0pwr bit = 1) and the uc0rxe bit is set to 1, reception is enabled after at least two cycles of the base clock (f uclk ) have elapsed. if a start bit is received before reception is enabled, the start bit is ignored. <7> 0
v850es/jg3-l chapter 17 asynchronous serial interface c (uartc) ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 596 of 1113 sep 22, 2011 (2/2) 7 bits 8 bits uc0cl 0 1 specification of data character length of 1 frame of transmit/receive data ? this register can be rewritten only when the uc0pwr bit is 0 or the uc0txe bit and the uc0rxe bit are 0. ? when transmission and reception are performed in the lin format, set the uc0cl bit to 1. 1 bit 2 bits uc0sl 0 1 specification of length of stop bit for transmit data this register can be rewritten only when the uc0pwr bit is 0 or the uc0txe bit and the uc0rxe bit are 0. ? this register is rewritten only when the uc0pwr bit is 0 or the uc0txe bit and the uc0rxe bit are 0. ? if ?reception with 0 parity? is selected during reception, a parity check is not performed. therefore, the uc0str.uc0pe bit is not set. ? when transmission and reception are performed in the lin format, clear the uc0ps1 and uc0ps0 bits to 00. no parity output 0 parity output odd parity output even parity output reception with no parity reception with 0 parity odd parity check even parity check uc0ps1 0 0 1 1 parity selection during transmission parity selection during reception uc0ps0 0 1 0 1 msb first lsb first uc0dir 0 1 data transfer order ? this register can be rewritten only when the uc0pwr bit is 0 or the uc0txe bit and the uc0rxe bit are 0. ? when transmission and reception are performed in the lin format, set the uc0dir bit to 1. remark for details of parity, see 17.6.6 parity types and operations . (2) uartc0 control register 1 (uc0ctl1) for details, see 17.7 (2) uartc0 control register 1 (uc0ctl1) . (3) uartc0 control register 2 (uc0ctl2) for details, see 17.7 (3) uartc0 control register 2 (uc0ctl2) .
v850es/jg3-l chapter 17 asynchronous serial interface c (uartc) ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 597 of 1113 sep 22, 2011 (4) uartc0 option control register 0 (uc0opt0) the uc0opt0 register is an 8-bit register used to control sbf transmission/reception in the lin communication format and the level of the transmission/reception signals for the uartc0. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 14h. (1/2) uc0srf the uc0ctl0.uc0pwr bit or the uc0ctl0.uc0rxe bit is set to 0, or sbf reception ends normally. during sbf reception uc0srf 0 1 sbf reception flag uc0opt0 uc0srt uc0stt uc0sls2 uc0sls1 uc0sls0 uc0tdl uc0rdl 654321 after reset: 14h r/w address: fffffaa3h sbf reception trigger uc0srt 0 1 sbf reception trigger ? this bit indicates whether sbf (sync brake field) is received in lin communication. ? when an sbf reception error occurs, the uc0srf bit remains 1 and sbf reception is started again. ? the uc0srf bit is a read-only bit. ? this is the sbf reception trigger bit during lin communication, and is always 0 when read . ? for sbf reception, set the uc0srt bit (to 1) to enable sbf reception. ? set the uc0srt bit after setting the uc0pwr bit and uc0rxe bit to 1. ? this is the sbf transmission trigger bit during lin communication, and is always 0 when read. ? setting this bit to 1 triggers sbf transmission. ? set the uc0stt bit after setting the uc0pwr bit and uc0txe bit to 1. sbf transmission trigger uc0stt 0 1 sbf transmission trigger <7> 0 ? ? caution do not set the uc0srt and uc0stt bits (to 1) during sbf reception (uc0srf bit = 1).
v850es/jg3-l chapter 17 asynchronous serial interface c (uartc) ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 598 of 1113 sep 22, 2011 (2/2) uc0sls2 1 1 1 0 0 0 0 1 uc0sls1 0 1 1 0 0 1 1 0 uc0sls0 1 0 1 0 1 0 1 0 13-bit output (initial value) 14-bit output 15-bit output 16-bit output 17-bit output 18-bit output 19-bit output 20-bit output sbf transmit length selection ? the output level of the txdc0 pin can be inverted by using the uc0tdl bit. ? this register can be set when the uc0pwr bit or the uc0txe bit is 0. this register can be set when the uc0pwr bit or the uc0txe bit is 0. normal output of transfer data inverted output of transfer data uc0tdl 0 1 transmit data level bit ? the input level of the rxdc0 pin can be inverted by using the uc0rdl bit. ? this register can be set when the uc0pwr bit or the uc0rxe bit is 0. normal input of transfer data inverted input of transfer data uc0rdl 0 1 receive data level bit
v850es/jg3-l chapter 17 asynchronous serial interface c (uartc) ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 599 of 1113 sep 22, 2011 (5) uartc0 option control register 1 (uc0opt1) the uc0opt1 register is an 8-bit register that cont rols the serial transfer operation of uartc0. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. caution set the uc0ebe bit while the operation of uartc is disabled (uc0ctl0.uc0pwr = 0). 0 uc0opt1 0 0 0 0 0 0 uc0ebe 654321 after reset: 00h r/w address: uc0opt1 fffffaaah 0 7 extension-bit operation is prohibited. transmission/reception is performed in the data length set by the uc0ctl0.uc0cl bit. extension-bit operation enabled. transmission/reception can be performed in 9-bit character length. uc0ebe 0 1 extension bit enable/disable ? when setting the uc0ebe bit to 1, and transmitting in 9-bit data length, be sure to set the following. if this setting is not performed, the setting of uc0ebe bit is invalid. ? uc0ctl0.uc0ps1, uc0ps0 = 00 (no parity) ? c0ctl0.uc0cl = 1 (8-bit character length) ? if transmitting or receiving in the lin communication format, set the uc0ebe to 0. the following shows the relationship between t he register setting value and the data format.
v850es/jg3-l chapter 17 asynchronous serial interface c (uartc) ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 600 of 1113 sep 22, 2011 table 17-2. relationship between register setting and data format register setting data format uc0ctl0 uc0opt1 uc0cl uc0ps1 uc0ps0 uc0sl uc0ebe d0 to d6 d7 d8 d9 d10 0 0 0 data stop ? ? ? 0 other than 00 data parity stop ? ? 1 0 0 data data stop ? ? 1 other than 00 0 0 data data parity stop ? 0 0 0 data stop stop ? ? 0 other than 00 data parity stop stop ? 1 0 0 data data stop stop ? 1 other than 00 1 0 data data parity stop stop 0 0 0 data stop ? ? ? 0 other than 00 data parity stop ? ? 1 0 0 data data data stop ? 1 other than 00 0 1 data data parity stop ? 0 0 0 data stop stop ? ? 0 other than 00 data parity stop stop ? 1 0 0 data data data stop stop 1 other than 00 1 1 data data parity stop stop remark data: data bit stop: stop bit parity: parity bit (6) uartc0 status register (uc0str) the uc0str register is an 8-bit re gister that displays the uartc0 tr ansfer status and reception error contents. this register can be read or written in 8-bit or 1-bit units, but the uc0tsf bit is a read-only bit, while the uc0pe, uc0fe, and uc0ove bits can be both read and wr itten. however, these bits can only be cleared by writing 0; they cannot be set by writing 1 (even if 1 is written to them, the previous value is retained). the conditions for clearing the uc0str register are shown below. table 17-3. conditions for clearing str register register/bit conditions for clearing uc0str register ? reset ? uc0ctl0.uc0pwr = 0 uc0tsf bit ? uc0ctl0.uc0txe = 0 uc0pe, uc0fe, uc0ove bits ? 0 write ? uc0ctl0.uc0rxe = 0
v850es/jg3-l chapter 17 asynchronous serial interface c (uartc) ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 601 of 1113 sep 22, 2011 uc0tsf the transmit shift register does not have data. ? when the uc0pwr bit or the uc0txe bit has been set to 0. ? when, following transfer completion, there was no next data transfer from uc0tx register the transmit shift register has data. (write to uc0tx register) uc0tsf 0 1 transfer status flag uc0str 0 0 0 0 uc0pe uc0fe uc0ove 6 5 4 3 <2> <1> after reset: 00h r/w address: fffffaa4h the uc0tsf bit is always 1 when performing continuous transmission. when initializing the transmission unit, check that the uc0tsf bit is 0 before performing initialization. the transmit data is not guaranteed when initialization is performed while the uc0tsf bit is 1. ? when the uc0pwr bit or the uc0rxe bit has been set to 0. ? when 0 has been written the received parity bit does not match the specified parity. uc0pe 0 1 parity error flag ? the operation of the uc0pe bit is controlled by the settings of the uc0ctl0.uc0ps1 and uc0ctl0.uc0ps0 bits. ? once the uc0pe bit is set (1), the value is retained until the bit is cleared (0). ? the uc0pe bit can be read and written, but it can only be cleared by writing 0 to it; it cannot be set by writing 1 to it. when 1 is written to this bit, the previous value is retained. <7> <0> ? when the uc0pwr bit or the uc0rxe bit has been set to 0 ? when 0 has been written when no stop bit is detected during reception uc0fe 0 1 framing error flag ? only the first bit of the receive data stop bits is checked, regardless of the value of the uc0ctl0.uc0sl bit. ? once the uc0fe bit is set (1), the value is retained until the bit is cleared (0). ? the uc0fe bit can be both read and written, but it can only be cleared by writing 0 to it; it cannot be set by writing 1 to it. when 1 is written to this bit, the previous value is retained. ? when the uc0pwr bit or the uc0rxe bit has been set to 0. ? when 0 has been written when receive data has been set to the uc0rx register and the next receive operation is completed before that receive data has been read uc0ove 0 1 overrun error flag ? when an overrun error occurs, the data is discarded without the next receive data being written to the receive buffer. ? once the uc0ove bit is set (1), the value is retained until the bit is cleared (0). ? the uc0ove bit can be both read and written, but it can only be cleared by writing 0 to it; it cannot be set by writing 1 to it. when 1 is written to this bit, the previous value is retained.
v850es/jg3-l chapter 17 asynchronous serial interface c (uartc) ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 602 of 1113 sep 22, 2011 (7) uartc0 receive data register l (uc0rxl) and uartc0 receive data register (uc0rx) the uc0rxl and uc0rx register are an 8- bit or 9-bit bu ffer register that stores parallel data converted by the receive shift register. the data stored in the receive shi ft register is transferred to the uc0rxl and uc0rx register upon completion of reception of 1 byte of data. during lsb-first reception when the data length has been specified as 7 bits, the receive data is transferred to bits 6 to 0 of the uc0rxl register and the msb always becomes 0. during msb-first reception, the receive data is transferred to bits 7 to 1 of the uc0 rxl register and the lsb always becomes 0. when an overrun error (uc0ove) occurs, the receive data at this time is not transferred to the uc0rxl and uc0rx register and is discarded. the access unit or reset value differs depending on the character length. ? character length 7/8-bit (uc0opt1.uc0ebe = 0) this register is read-only, in 8-bit units. reset or uc0ctl0.uc0pwr bit = 0 sets this register to ffh. ? character length 9-bit (uc0opt1.uc0ebe = 0) this register is read-only, in 16-bit units. reset or uc0ctl0.uc0pwr bit = 0 sets this register to 01ffh. (a) character length 7/8-bit (uc0opt1.uc0ebe = 0) uc0rxl 654321 after reset: ffh r address: uc0rxl fffffaa6h 7 0 (b) character length 9-bit (uc0opt1.uc0ebe = 1) after reset: 01ffh r address: uc0rx fffffaa6h uc0rx 654321 70 0000000 14 13 12 11 10 9 15 8
v850es/jg3-l chapter 17 asynchronous serial interface c (uartc) ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 603 of 1113 sep 22, 2011 (8) uartc0 transmit data register l (uc0tx l), uartc0 transmit data register (uc0tx) the uc0txl and uc0tx register is an 8-bit or 9-bit register used to set transmit data. during lsb-first transmission when the data length has been specified as 7 bits, the transmit data is transferred to bits 6 to 0 of the uc0rx register. duri ng msb-first transmission, the receive data is transferred to bits 7 to 1 of the uc0rx register. the access unit or reset value differs depending on the character length. ? character length 7/8-bit (uc0opt1.uc0ebe = 0) this register can be read or written in 8-bit units. reset sets this register to ffh. ? character length 9-bit (uc0opt1.uc0ebe = 0) this register can be read or written in 16-bit units. reset sets this register to 01ffh. cautions 1. in the transmission operation enable status (uc0pwr = 1 and uc0txe = 1), writing to the uc0txl, uc0tx register, as operate as tri gger of transmission st ar, if writing the value of as soon as before and save value, befo re the intuc0t interr upt is occurred, the same data is transferred at twice. 2. data writing for consecutive transmission, after be generated the intuc0t interrupt. if writing the next data before the int uc0t interrupt is occurred, transmission start processing and source of conf lict writing the uc0txl, uc0 tx register, unexpected operations may occur. 3. if perform to write the uc0txl, uc0txli n the disable transmission operation register, can not be used as transmission start tri gger. consequently, even if transmission enable status after perform to write th e uc0txl, uc0tx regist er in the disable transmission operation status, can not be started transmission. (a) character length 7/8-bit (uc0opt1.uc0ebe = 0) uc0txl 654321 after reset: ffh r/w address: uc0txl fffffaa8h 7 0 (b) character length 9-bit (uc0opt1.uc0ebe = 1) after reset: 01ffh r/w address: uc0tx fffffaa8h uc0tx 654321 70 0000000 14 13 12 11 10 9 15 8
v850es/jg3-l chapter 17 asynchronous serial interface c (uartc) ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 604 of 1113 sep 22, 2011 17.5 interrupt request signals the following two interrupt request signals are generated from uartc0. ? reception complete interrupt request signal (intuc0r) ? transmission enable interrupt request signal (intuc0t) the default priority for these two interrupt request signa ls is reception complete interrupt request signal then transmission enable interrupt request signal. table 17-4. interrupts and their default priorities interrupt request signal priority reception complete high transmission enable low (1) reception complete interrupt request signal (intuc0r) when the data stored in the receive shift register is tr ansferred to the uc0rx regist er with reception enabled, the reception complete interrupt request signal is generated. a reception complete interrupt request signal is also out put when a reception error occurs. therefore, when a reception complete interrupt request signal is acknowledged and the data is read, read the uc0str register and check that the rec eption result is not an error. no reception complete interrupt request signal is generated in the reception disabled status. (2) transmission enable interr upt request signal (intuc0t) if transmit data is transferred from the uc0tx register to the uartc0 transmit shift register with transmission enabled, the transmission enable interrupt request signal is generated.
v850es/jg3-l chapter 17 asynchronous serial interface c (uartc) ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 605 of 1113 sep 22, 2011 17.6 operation 17.6.1 data format as shown in figure 17-5, one frame of transmit/receive data consists of a start bit, character bits, parity bit, and stop bit(s). specification of the character bit lengt h within 1 data frame, parity selection, specification of the stop bit length, and specification of msb-first/lsb-first transfe r are performed using the uc0ctl0 register. specification of 9-bit character length is performed using the uc0opt1 register. the uc0opt0.uc0tdl bit is used to specify normal outpu t/inverted output for the data to be transferred via the txdc0 pin. the uc0opt0.uc0rdl bit is used to specify normal input/inverted input for the data to be received via the rxdc0 pin. ? start bit ..................................... 1 bit ? character bi ts ........................... 7 bits/8 bits/9 bits ? parity bit ................................... even parity/odd parity/0 parity/no parity ? stop bit ..................................... 1 bit/2 bits ? input logic ................................. normal input/inverted input ? output logic .............................. normal ou tput/inverted output ? communication direction .......... msb/lsb
v850es/jg3-l chapter 17 asynchronous serial interface c (uartc) ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 606 of 1113 sep 22, 2011 figure 17-3. uartc transmit/receive data format (a) 8-bit data length, lsb first, even pa rity, 1 stop bit, transfer data: 55h d0 d1 d2 d3 d4 d5 d6 d7 1 data frame start bit parity bit stop bit (b) 8-bit data length, msb first, even pa rity, 1 stop bit, transfer data: 55h d7 d6 d5 d4 d3 d2 d1 d0 1 data frame start bit parity bit stop bit (c) 8-bit data length, msb first, even parity, 1 stop bit, transfer data : 55h, transmit/receive data inverted d7 d6 d5 d4 d3 d2 d1 d0 1 data frame start bit parity bit stop bit (d) 7-bit data length, lsb first, odd pa rity, 2 stop bits, transfer data: 36h d0 d1 d2 d3 d4 d5 d6 1 data frame start bit parity bit stop bit stop bit (e) 8-bit data length, lsb first, no pa rity, 1 stop bit, transfer data: 87h d0 d1 d2 d3 d4 d5 d6 d7 1 data frame start bit stop bit
v850es/jg3-l chapter 17 asynchronous serial interface c (uartc) ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 607 of 1113 sep 22, 2011 17.6.2 uart transmission transmission is enabled by setting the uc0ctl0.uc0pwr and uc0ctl0.uc0txe bits to 1, and transmission is started by writing transmit data to the uc0tx register. th e start bit, parity bit, and stop bit are automatically added. since the cts (transmit enable signal) in put pin is not provided in uartc0, us e a port to check that reception is enabled at the transmit destination. the data in the uc0tx register is transf erred to the uartc0 transmit shift regi ster upon the start of transmission. a transmission enable interrupt request signal (intuc0t) is generated upon completion of transmission of the data of the uc0tx register to the uartc0 transmit shift register, and the contents of the uartc0 transmit shift register are output to the txdc0 pin. writing the next transmit data to the uc0tx register is enabled after the intuc0t signal is generated. figure 17-4. uart transmission start bit d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit intuc0t txdc0 remark lsb first
v850es/jg3-l chapter 17 asynchronous serial interface c (uartc) ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 608 of 1113 sep 22, 2011 17.6.3 continuous transmission procedure writing transmit data to the uc0tx regi ster with transmission enabled triggers transmission. the data in the uc0tx register is transferred to the uartc0 transmit shift register, the transmission enable interrupt request signal (intuc0t) is generated, and then shifti ng is started. after the transmission enable interrupt request signal (intuc0t) is generated, the next transmit data can be wr itten to the uc0tx register. the timing of uartc0 transmit shift register transmission can be judged from the transmission enable interrupt request signal (intuc0t). an efficient communication rate is realized by writing t he data to be transmitted next to the uc0tx register during transfer. caution when initializing transmission during the exe cution of continuous transmission, make sure that the uc0str.uc0tsf bit is 0, then pe rform initialization. transmit da ta that is initialized when the uc0tsf bit is 1 cannot be guaranteed. figure 17-5. continuous transmission processing start register settings uc0tx write yes yes no no occurrence of transmission interrupt? note required number of writes performed? end note be sure to read the uc0str register after g eneration of the transmission enable interrupt request signal (intuc0t) to check whether a transmission error has occurred.
v850es/jg3-l chapter 17 asynchronous serial interface c (uartc) ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 609 of 1113 sep 22, 2011 figure 17-6. continuous tran smission operation timing (a) transmission start txdc0 uc0tx intuc0t uc0tsf transmission shift register start data (1) data (1) data (2) data (2) data (1) data (3) parity stop start data (2) parity stop start (b) transmission end ff txdc0 uc0tx intuc0t uc0tsf start data (n ? 1) data (n ? 1) data (n ? 1) data (n) data (n) transmission shift register uc0pwr or uc0txe bit parity stop stop start data (n) parity parity stop
v850es/jg3-l chapter 17 asynchronous serial interface c (uartc) ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 610 of 1113 sep 22, 2011 17.6.4 uart reception first, enable reception by executing the following operati ons and monitor the rxdc0 input to detect the start bit. ? specify the operating clock by using uartc control register 1 (uc0ctl1). ? specify the baud rate by using ua rtc control register 2 (uc0ctl2). ? specify the output logic level by using uartc option control register 0 (uc0opt0). ? specify the communication direction, parity, data character length, and stop bit length by using uartc control register 0 (uc0ctl0). ? set the power bit and reception enable bit (uc0pwr = 1 and uc0rxe = 1). to change the communication direction, parity, data character lengt h, and/or stop bit length, clear the power bit (uc0pwr = 0) or clear both the transmission enable bit and reception enable bit (uc0txe = 0 and uc0rxe = 0) beforehand. the level input to the rxdc0 pin is sampled by using the operating clock. if the falling edge is detected, sampling of data input to rxdc0 is started. if the data is low level ha lf a bit after detection of the falling edge (indicated by v in figure 17-9), it is recognized as a start bit. when the start bit has been recognized, reception is started, and serial data is sequentially st ored in the receive shift register at the specified baud rate. when the stop bit has been received, the reception complete interrupt re quest signal (intuc0r) is gene rated and, at the same time, the data stored in the receive shift register is tr ansferred to the receive data register (uc0rx). if an overrun error occurs (uc0ove = 1), however, the receive data is not transferred to uc0rx, but is discarded. on the other hand, even if a parity er ror (uc0pe = 1) or framing error (uc0fe = 1) occurs, reception continues and the receive data is transferred to the uc0rx register. no matter which reception error has occurred, the intuc0r interrupt is generated afte r reception is complete. figure 17-7. uart reception d0 d1 d2 d3 d4 d5 d6 d7 intuc0r uc0rx rxdc0 start bit parity bit stop bit
v850es/jg3-l chapter 17 asynchronous serial interface c (uartc) ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 611 of 1113 sep 22, 2011 cautions 1. be sure to read th e uc0rx register even when a recep tion error occurs. if the uc0rx register is not read, an overr un error occurs during reception of the next data, and reception errors continue occurring indefinitely. 2. reception is performed assuming that ther e is only one stop bit. a second stop bit is ignored. 3. when reception is comple ted, read the uc0rx register after the reception complete interrupt request signal (intuc0r) has been gene rated, and clear the uc0rxe bit to 0. if the uc0rxe bit is cleared to 0 be fore the intuc0r signal is gene rated, the read value of the uc0rx register cannot be guaranteed. 4. if the receive completion processing (intuc0r signal generati on) of uartc0 conflicts with setting the uc0pwr bit or uc0rxe bit to 0, the intuc0r signal may be ge nerated in spite of there being no data stored in the uc0rx register. to complete reception without waiting for intuc0r si gnal generation, be sure to clear (0) the interrupt request flag (uc0rif) of the uc0 ric register, after setting (1) the interrupt mask flag (uc0rmk) of the interrupt control register (uc0ric) and then set (1) the uc0pwr bit or uc0rxe bit to 0.
v850es/jg3-l chapter 17 asynchronous serial interface c (uartc) ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 612 of 1113 sep 22, 2011 17.6.5 reception errors three types of errors can occur during reception: parit y errors, framing errors, and overrun errors. the data reception result error flag is set in the uc0str register and a reception complete interrupt request signal (intuc0r) is output when an error occurs. it is possible to ascertain which error occurred during rec eption by reading the contents of the uc0str register. clear the reception error flag by writing 0 to it after reading it. figure 17-8. reading receive data start no intuc0r signal generated? error occurs? end yes no yes error processing read uc0rx register read uc0str register caution when the intuc0r signal is generated, the uc0str register must be read to check for errors.
v850es/jg3-l chapter 17 asynchronous serial interface c (uartc) ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 613 of 1113 sep 22, 2011 table 17-5. reception error causes error flag reception error cause uc0pe parity error the received parity bit does not match the setting. uc0fe framing error the stop bit was not detected. uc0ove overrun error reception of the next data was completed before data was read from the receive buffer. when a reception error occurs, perform the following procedure according to the kind of error. ? parity error if false data is received due to problems such as noise on the reception line, discard the received data and retransmit. ? framing error a baud rate error may have occurred between the reception side and transmission side or a start bit may have been erroneously detected. since this is a fatal erro r for the communication format, check that operation on the transmission side has stopped, initialize both sides, and then start the communication again. ? overrun error 1 frame of data is discarded because the next reception is completed before data was read from the receive buffer. if this data was needed, retransmit the data. caution in reception, be sure to read the uc0str register before completion of the next reception to check whether an error has occurred. if an error has occurred, perform error processing.
v850es/jg3-l chapter 17 asynchronous serial interface c (uartc) ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 614 of 1113 sep 22, 2011 17.6.6 parity types and operations the parity bit is used to detect bit errors in the communi cation data. normally the same parity is used on the transmission side and the reception side. in the case of even parity and odd parity, it is possible to detect odd-count bit errors. in the case of 0 parity and no parity, errors cannot be detected. (a) even parity (i) during transmission the number of bits whose value is ?1? among the transm it data, including the parity bit, is controlled so as to be an even number. the parity bit values are as follows. ? odd number of bits whose value is ?1? among transmit data: 1 ? even number of bits whose value is ?1? among transmit data: 0 (ii) during reception the number of bits whose value is ?1? among the rece ption data, including the parity bit, is counted, and if it is an odd number, a parity error is output. (b) odd parity (i) during transmission opposite to even parity, the number of bits whose value is ?1? among the transmit data, including the parity bit, is controlled so that it is an odd nu mber. the parity bit values are as follows. ? odd number of bits whose value is ?1? among transmit data: 0 ? even number of bits whose value is ?1? among transmit data: 1 (ii) during reception the number of bits whose value is ?1? among the receiv e data, including the parity bit, is counted, and if it is an even number, a parity error is output. (c) 0 parity during transmission, the parity bit is always made 0, regardless of the transmit data. during reception, a parity bit check is not performed. therefore, no parity error occurs, regardless of whether the parity bit is 0 or 1. (d) no parity no parity bit is added to the transmit data. reception is performed assuming that there is no parity bit. no parity error occurs since there is no parity bit. caution when using the lin function, fix the uc0ps1 and uc0ps0 bits of the uc0ctl0 register to 0, 0.
v850es/jg3-l chapter 17 asynchronous serial interface c (uartc) ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 615 of 1113 sep 22, 2011 17.6.7 lin transmissi on/reception format the pd70f3792, 70f3793, 70f3841, 70f3842 have an sbf (sync break fi eld) transmission/reception control function to enable use of the lin function. remark lin stands for local interconnect network and is a low-speed (1 to 20 kbps) serial communication protocol intended to reduce co sts of automotive networks. lin communication is single-master communication, and up to 15 slaves can be connected to the master. the lin slaves are used to control the switches , actuators, and sensors, and these are connected to the lin master via the lin network. normally, the lin master is connected to a network such as can (controller area network). in addition, the lin bus uses a single-wire method and is connected to the nodes via a transceiver that complies with iso9141. in the lin protocol, the master transmits a frame with baud rate information and the slave receives it and corrects the baud rate error. therefore, comm unication is possible when the baud rate error in the slave is 15% or less. figures 17-9 and 17-10 outline the transmissi on and reception manipulations of lin. figure 17-9. lin transmission format lin bus wake-up signal frame sync break field (sbf) sync field id field data field data field check sum field intuc0t interrupt txdc0 (output) note 3 8 bits note 1 note 2 13 bits sbf transmission note 4 55h transmission data transmission data transmission data transmission data transmission notes 1. the interval between each field is controlled by software. 2. sbf output is performed by hardware. the output width is the bit length set by the uc0opt0.uc0sbl2 to uc0opt0.uc0sbl0 bits. if ev en finer output width adj ustments are required, such adjustments can be performed using the uc0ctln.uc0brs7 to uc0ctln.uc0brs0 bits. 3. 80h transfer in the 8-bit mode is substituted for the wakeup signal frame. 4. a transmission enable interrupt request signal (intuc0t) is output at the star t of each transmission. the intuc0t signal is also output at the start of each sbf transmission.
v850es/jg3-l chapter 17 asynchronous serial interface c (uartc) ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 616 of 1113 sep 22, 2011 figure 17-10. lin reception format reception interrupt (intuc0r) edge detection capture timer disable disable enable rxdc0 (input) enable note 2 sbf reception note 3 note 4 note 1 sf reception id reception data reception data reception note 5 data reception lin bus wake-up signal frame sync break field (sbf) sync field id field data field data field check sum field notes 1. the wakeup signal is detected by the pin edge detec tor, uartc0 is enabled, and the sbf reception mode is set. 2. reception is performed until detec tion of the stop bit. upon detection of sbf reception of 11 or more bits, it is judged as normal sbf reception end, and an interrupt signal is output. upon detection of sbf reception of less than 11 bits, it is judged as an sbf reception error, no interrupt signal is output, and the mode returns to the sbf reception mode. 3. if sbf reception ends normally, an interrupt request signal is output. the timer is enabled by an sbf reception complete interrupt. moreover, erro r detection for the uc0st r.uc0ove, uc0str.uc0pe, and uc0str.uc0fe bits is suppressed and uart communication error detection processing and data transfer of the uartc0 receive shift register and uc0rx register is not pe rformed. the uartc0 receive shift register holds the initial value, ffh. 4. the rxdc0 pin is connected to ti (capture input) of the timer and the transfer rate is calculated. the value of the uc0ctl2 register obtained by correct ing the baud rate error after uartc enable goes low is set again, causing the status to become the reception status. 5. a check-sum field is identified by software. uartc0 is initialized following reception of the check-sum field, and the processing for re-specifying the sbf reception mode is performed, also by software.
v850es/jg3-l chapter 17 asynchronous serial interface c (uartc) ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 617 of 1113 sep 22, 2011 17.6.8 sbf transmission when the uc0ctl0.uc0pwr bit and uc0ctl0.uc0txe bit are 1, the transmission enab led status is entered, and sbf transmission is started by setting the sbf transmission trigger (uc0opt0.uc0stt bit) to 1. thereafter, a low level signal having a length of 13 to 20 bits, as specified by the uc0opt0.uc0sls2 to anopt0.uc0sls0 bits, is output. a transmission enable interrupt request signal (intuc0t) is generated upon the start of sbf transmission. following the end of sbf tr ansmission, the uc0stt bit is automatically cleared. transmission is suspended until the data to be transmitted next is written to the uc0tx register, or until the sbf transmission trigger (uc0stt bit) is set. figure 17-11. example of sbf transmission intuc0t interrupt 12345678910111213 setting of uc0stt bit txdc0 stop bit
v850es/jg3-l chapter 17 asynchronous serial interface c (uartc) ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 618 of 1113 sep 22, 2011 17.6.9 sbf reception the reception enabled status is entered by setting the uc0ctl0.uc0pwr bit to 1 and then setting the uc0ctl0.uc0rxe bit to 1. the sbf reception wait status is set by setting the sbf reception trigger (uc0op t0.uc0str bit) to 1. in the sbf reception wait status, similarly to the uart reception wait status, the rx dc0 pin is monitored and start bit detection is performed. following detection of the start bit, rec eption is started and the internal count er increments according to the set baud rate. when a stop bit is received, if the sbf width is 11 or more bits, it is judged as normal processing and a reception complete interrupt request signal (i ntuc0r) is output. the uc0opt0.uc0sr f bit is automatically cleared and sbf reception ends. error detection for the uc0st r.uc0ove, uc0str.uc0pe, an d uc0str.uc0fe bits is suppressed and uart communication error detection processing is not performed. moreover, data transfer of the uartc0 reception shift register and uc0rx register is not performed and ffh, the initial value, is held. if the sbf width is 10 or fewer bits, reception is terminated as an er ror, an interrupt is not generated, and the sbf reception mode is restored. the uc0srf bit is not cleared at this time. cautions 1. if sbf is tran smitted during data reception, a framing error occurs. 2. do not set the sbf reception trigger bi t (uc0srt) and sbf transmission trigger bit (uc0stt) to 1 during sbf reception (uc0srf = 1). figure 17-12. sbf reception (a) normal sbf reception (detection of st op bit after more than 10.5 bits) uc0srf rxdc0 123456 11.5 7 8 9 10 11 intuc0r interrupt (b) sbf reception error (detection of st op bit after 10.5 or fewer bits) uc0srf rxdc0 123456 10.5 78910 intuc0r interrupt
v850es/jg3-l chapter 17 asynchronous serial interface c (uartc) ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 619 of 1113 sep 22, 2011 17.6.10 receive data noise filter this filter samples signals received via the rxdc0 pin using the base clock supplied by the dedicated baud rate generator. when the same sampling value is read twice, the ma tch detector output changes and the rxdc0 signal is sampled as the input data. therefore, data not exceeding 1 clock cycle width is judged to be noise and is not delivered to the internal circuit (see figure 17-13 ). see 17.7 (1) (a) base clock for details of the base clock. moreover, since the circuit is as shown in figure 17-15, the processing that goes on withi n the receive operation is delayed by 3 clocks in relation to the external signal status. figure 17-13. noise filter circuit match detector in base clock (f uclk ) rxdc0 qin ld_en q internal signal c internal signal b in q internal signal a figure 17-14. timing of rxdc0 signal judged as noise internal signal b base clock rxdc0 (input) internal signal c mismatch (judged as noise) internal signal a mismatch (judged as noise) match match
v850es/jg3-l chapter 17 asynchronous serial interface c (uartc) ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 620 of 1113 sep 22, 2011 17.7 dedicated baud rate generator the dedicated baud rate generator consists of a source clock selector block and an 8-bit programmable counter block, and generates a serial clock during transmission and reception using uartc0. regarding the serial clock, a dedicated baud rate generator output can be selected for each channel. there is an 8-bit counter for transmissi on and another one for reception. (1) baud rate generato r configuration figure 17-15. configuration of baud rate generator f uclk selector uc0pwr 8-bit counter match detector baud rate uc0ctl2: uc0brs7 to uc0brs0 1/2 uc0pwr, uc0txen bus (or uc0rxe bit) uc0ctl1: uc0cks3 to uc0cks0 f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 f xx /512 f xx /1024 f uclk /k remarks 1. f xx : main clock frequency 2 . f uclk : base clock frequency 3. f uclk /k: serial clock (k: brgcn register value) (a) base clock when the uc0ctl0.uc0pwr bit is 1, the cl ock selected by the uc0ctl1.uc0cks3 to uc0ctl1.uc0cks0 bits is supplied to the 8-bit counter. this clock is called the base clock (f uclk ). (b) serial clock generation a serial clock can be generated by setting the uc0ctl1 register and the uc0ctl2 register (n = 0 to 2). the base clock is selected by uc0ctl1.uc0cks3 to uc0ctl1.uc0cks0 bits. the frequency division value for the 8-bit count er can be set using the uc0ctl2.uc0brs7 to uc0ctl2.uc0brs0 bits. the baud rate clock is generated by dividing the serial clock by two.
v850es/jg3-l chapter 17 asynchronous serial interface c (uartc) ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 621 of 1113 sep 22, 2011 (2) uartc0 control register 1 (uc0ctl1) the uc0ctl1 register is an 8-bit register that selects the uartc0 base clock. this register can be read or written in 8-bit units. reset sets this register to 00h. caution clear the uc0ctl0.uc0pwr bit to 0 before rewriting the uc0ctl1 register. 0 uc0ctl1 0 0 0 uc0cks3uc0cks2 uc0cks1 uc0cks0 654321 after reset: 00h r/w address: fffffaa1h 7 0 f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 f xx /512 f xx /1,024 setting prohibited uc0cks2 0 0 0 0 1 1 1 1 0 0 0 uc0cks3 0 0 0 0 0 0 0 0 1 1 1 base clock (f uclk ) selection uc0cks1 0 0 1 1 0 0 1 1 0 0 1 uc0cks0 0 1 0 1 0 1 0 1 0 1 0 other than above remark f xx : main clock frequency
v850es/jg3-l chapter 17 asynchronous serial interface c (uartc) ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 622 of 1113 sep 22, 2011 (3) uartc0 control register 2 (uc0ctl2) the uc0ctl2 register is an 8-bit register that selects the baud rate (serial transfer speed) clock of uartc0. the baud rate clock is generated by dividing the se rial clock specified by this register by two. this register can be read or written in 8-bit units. reset sets this register to ffh. caution either clear the uc0ctl0.uc0pwr bit to 0, or clear the uc0txe and uc0rxe bits to 0, 0, before rewriting the uc0ctl2 register. uc0brs7 uc0ctl2 uc0brs6 uc0brs5uc0brs4 uc0brs3uc0brs2 uc0brs1 uc0brs0 654321 after reset ffh r/w address: fffffaa2h 7 0 uc0 brs7 0 0 0 0 : 1 1 1 1 uc0 brs6 0 0 0 0 : 1 1 1 1 uc0 brs5 0 0 0 0 : 1 1 1 1 uc0 brs4 0 0 0 0 : 1 1 1 1 uc0 brs3 0 0 0 0 : 1 1 1 1 uc0 brs2 0 1 1 1 : 1 1 1 1 uc0 brs1 0 0 1 : 0 0 1 1 uc0 brs0 0 1 0 : 0 1 0 1 default (k) 4 5 6 : 252 253 254 255 serial clock f uclk /4 f uclk /5 f uclk /6 : f uclk /252 f uclk /253 f uclk /254 f uclk /255 setting prohibited remark f uclk : clock frequency selected by the uc0ctl1.uc0cks3 to uc0ctl1.uc0cks0 bits
v850es/jg3-l chapter 17 asynchronous serial interface c (uartc) ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 623 of 1113 sep 22, 2011 (4) baud rate the baud rate is obtained by the following equation. baud rate = [bps] remark f uclk = frequency of base clock selected by the uc0ctl1.uc0cks3 to uc0ctl1.uc0cks0 bits f xx : main clock frequency m = value set using the uc0ctl1.uc0cks3 to uc0ctl1.uc0cks0 bits (m = 0 to 10) k = value set using the uc0ctl2.uc0brs7 to uc0ctl2.uc0brs0 bits (k = 4 to 255) the baud rate error is obtained by the following equation. error (%) = ? 1 100 [%] cautions 1. the baud rate erro r during transmission must be with in the error tolerance on the receiving side. 2. the baud rate error during reception must satisfy the range indicated in (5) allowable baud rate range dur ing reception. f xx 2 m+1 k f xx 2 m+1 k target baud rate
v850es/jg3-l chapter 17 asynchronous serial interface c (uartc) ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 624 of 1113 sep 22, 2011 to set the baud rate, perform the following calculat ion for setting the uc0ctl1 and uc0ctl2 registers (when using the internal clock). <1> set k to fxx/(2 target baud rate) and m to 0. <2> if k is 256 or greater (k 256), reduce k to half (k/2) and increment m by 1 (m + 1). <3> repeat step <2> until k becomes less than 256 (k < 256). <4> round off the first decimal point of k to the nearest whole number. if k is 256 after round-off, reduce k to half (k/2) and increment m by 1 (m + 1) to obtain k = 128. <5> set the value of m to the uc0ctl1 register and the value of k to the uc0ctl2 register. example: when f xx = 20 mhz and target baud rate = 153,600 bps <1> k = 20,000,000/(2 153,600) = 65.10?, m = 0 <2>, <3> k = 65.10? < 256, m = 0 <4> set value of uc0ctl2 register: k = 65 = 41h, set value of uc0ctl1 register: m = 0 actual baud rate = 20,000,000/(2 65) = 153,846 [bps] baud rate error = {20,000,000/(2 65 153,600) ? 1} 100 = 0.160 [%] representative examples of baud rate settings are shown below. table 17-6. baud rate generator setting data f xx = 20 mhz f xx = 16 mhz f xx = 10 mhz baud rate (bps) uc0ctl1 uc0ctl2 err (%) uc0ctl1 uc0ctl2 err (%) uc0ctl1 uc0ctl2 err (%) 300 08h 82h 0.16 07h d0h 0.16 07h 82h 0.16 600 07h 82h 0.16 06h d0h 0.16 06h 82h 0.16 1200 06h 82h 0.16 05h d0h 0.16 05h 82h 0.16 2400 05h 82h 0.16 04h d0h 0.16 04h 82h 0.16 4800 04h 82h 0.16 03h d0h 0.16 03h 82h 0.16 9600 03h 82h 0.16 02h d0h 0.16 02h 82h 0.16 19200 02h 82h 0.16 01h d0h 0.16 01h 82h 0.16 31250 01h a0h 0 01h 80h 0 00h a0h 0 38400 01h 82h 0.16 00h d0h 0.16 00h 82h 0.16 76800 00h 82h 0.16 00h 68h 0.16 00h 41h 0.16 153600 00h 41h 0.16 00h 34h 0.16 00h 21h ? 1.36 312500 00h 20h 0 00h 1ah ? 1.54 00h 10h 0 625000 00h 10h 0 00h 0dh ? 1.54 00h 08h 0 remark f xx : main clock frequency err: baud rate error (%)
v850es/jg3-l chapter 17 asynchronous serial interface c (uartc) ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 625 of 1113 sep 22, 2011 (5) allowable baud rate ra nge during reception the baud rate error range at the destination that is allowable during reception is shown below. caution the baud rate error indicated below is a th eoretical value. in practice, the signal might be distorted, or communication might not be performed normally even if the error is within the allowable range. therefore, th e error must be minimized. figure 17-16. allowable baud rate range during reception bl 1 data frame (11 bl = fl) flmin flmax uartc0 data frame length start bit bit 0 bit 1 bit 7 parity bit minimum allowable data frame length maximum allowable data frame length stop bit start bit bit 0 bit 1 bit 7 parity bit latch timing stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit as shown in figure 17-16, the receive data latch timi ng is determined by the counter set using the uc0ctl2 register following start bit detection. the transmit data can be received normally if up to the last data (stop bit) can be received in time for this latch timing. when this is applied to 11-bit reception, t he following is the theoretical result. bl = (brate) ? 1 brate: uartc0 baud rate (n = 0 to 2) k: setting value of uc0ctl2.uc0brs7 to uc0ctl2.uc0brs0 bits (n = 0 to 2) bl: 1-bit data length fl: length of 1 data frame latch timing margin: 2 clock cycles minimum allowable data frame length: flmin = 11 bl ? bl = bl k ? 2 2k 21k + 2 2k
v850es/jg3-l chapter 17 asynchronous serial interface c (uartc) ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 626 of 1113 sep 22, 2011 therefore, the maximum baud rate that can be re ceived by the destination is as follows. brmax = (flmin/11) ? 1 = brate similarly, obtaining the maximum allowable data frame length yields the following. flmax = 11 bl ? bl = bl flmax = bl 11 therefore, the minimum baud rate that can be received by the destination is as follows. brmin = (flmax/11) ? 1 = brate obtaining the allowable baud rate error for uartc0 and the destination from the above-described equations yields the following. table 17-7. maximum/minimum allowa ble baud rate error (11-bit length) division ratio (k) maximum allowable baud rate error minimum allowable baud rate error 4 +2.32% ? 2.43% 8 +3.53% ? 3.61% 20 +4.26% ? 4.31% 50 +4.56% ? 4.58% 100 +4.66% ? 4.67% 255 +4.72% ? 4.73% remarks 1. the reception accuracy depends on the bit count in 1 frame, the base clock frequency (f uclk ), and the division ratio (k). the higher the base clock frequency (f uclk ) and the larger the division ratio (k), the higher the accuracy. 2. k: setting value of uc0ctl2.uc0brs7 to uc0ctl2.uc0brs0 bits (n = 0 to 2) 10 11 k + 2 2 k 21k ? 2 2 k 21k ? 2 20 k 22k 21k + 2 20k 21k ? 2
v850es/jg3-l chapter 17 asynchronous serial interface c (uartc) ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 627 of 1113 sep 22, 2011 (6) data frame length durin g continuous transmission in continuous transmission, the data frame length from t he stop bit to the next start bit is 2 base clock cycles longer than usual. however, timing initialization is per formed via start bit detection by the receiving side, so this has no influence on the transfer result. figure 17-17. data frame length during continuous transmission start bit bit 0 bit 1 bit 7 parity bit stop bit bl 1 data frame (fl) bl bl bl bl bl bl blstp start bit of 2nd byte start bit bit 0 assuming a 1 bit data length of bl; a stop bit l ength of blstp; and a base clock frequency of f uclk , we obtain the following equation. blstp = bl + 2/f uclk therefore, the transfer rate during continuous transmission is as follows. data frame length = 11 bl + (2/f uclk )
v850es/jg3-l chapter 17 asynchronous serial interface c (uartc) ( pd70f3792, 70f3793, 70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 628 of 1113 sep 22, 2011 17.8 cautions (1) when the clock supply to uartc0 is stopped (for exam ple, in idle1, idle2, or stop mode), the operation stops with each register retaining the value it had im mediately before the clock supply was stopped. the txdc0 pin output also holds and out puts the value it had immediately bef ore the clock supply was stopped. however, the operation is not guaranteed after the cloc k supply is resumed. therefore, after the clock supply is resumed, the circuits should be initialized by setting t he uc0ctl0.uc0pwr, uc0ctl0.uc0rxen, and uc0ctl0.uc0txen bits to 0, 0, 0. (2) in uartc0, the interrupt caused by a communicati on error does not occur. when transferring transmit data and receive data using dma transfer, error processing ca nnot be performed even if e rrors (parity, overrun, framing) occur during transfer. either read the uc0st r register after dma transfer has been completed to make sure that there are no errors, or read the uc0st r register during communication to check for errors. (3) start up uartc0 in the following sequence. <1> set the uc0ctl0.uc0pwr bit to 1. <2> set the ports. <3> set the uc0ctl0.uc0txe bit to 1 and the uc0ctl0.uc0rxe bit to 1. (4) stop uartc0 in the following sequence. <1> set the uc0ctl0.uc0txe bit to 0 and the uc0ctl0.uc0rxe bit to 0. <2> set the ports and set the uc0ctl0.uc0pwr bit to 0 (it is not a problem if the port settings are not changed). (5) in transmit mode (uc0ctl0.uc0pwr bit = 1 and uc0 ctl0.uc0txe bit = 1), do not overwrite the same value to the uc0tx register by softwar e because transmission starts by writ ing to this register. to transmit the same value continuously, overwrite the same value. (6) in continuous transmission, the period from the stop bit to the next start bit is 2 base clock cycles longer than usual. however, the reception side initializes the timing by detecting the start bit, so the reception result is not affected. (7) uartc cannot identify the start bit if low level signals are continuously input to the rxdc0 pin. (8) the rxdc0 and sib1 pins cannot be used at the same time. when using the pin for rxdc0, stop csib0 reception. (clear the cb1ctl0.cb1rxe bit to 0.) w hen using the pin for sib1 , stop uartc0 reception. (clear the uc0ctl0.uc0rxe bit to 0.)
v850es/jg3-l chapter 18 clocked serial interface b (csib) r01uh0165ej0700 rev.7.00 page 629 of 1113 sep 22, 2011 chapter 18 clocked serial interface b (csib) 18.1 features { 3-wire serial interface sobn: serial data output sibn: serial data input sckbn: serial clock i/o transmission mode, reception mode, and tr ansmission/reception mode can be specified. { transfer rate: 8 mbps max { master mode and slave mode can be selected. { two interrupt request signals: ? reception complete interrupt (intcbnr): this inte rrupt occurs when receive data is transferred to the cbnrx register with reception enabled, or when an overrun error occurs. in the single trans fer mode, this interrupt occurs upon completion of transmission, even when only transmission is executed. ? transmission enable interrupt (intcb nt): in continuous transmission or continuous transmission/reception mode, this interrupt occurs when transmit data is transferred from the cbntx register and it bec omes possible to write data to cbntx. { timing of data reception/transmission via sckbn can be specified { transfer data length can be selected in 1-bit units from between 8 and 16 bits { transfer data can be switched between msb-first and lsb-first { double buffers for both transmission and reception { overrun error detection remark n = 0 to 4
v850es/jg3-l chapter 18 clocked serial interface b (csib) r01uh0165ej0700 rev.7.00 page 630 of 1113 sep 22, 2011 18.2 configuration csibn includes the following hardware. table 18-1. configuration of csibn item configuration registers csibn receive data register (cbnrx) csibn transmit data register (cbntx) csibn control register 0 (cbnctl0) csibn control register 1 (cbnctl1) csibn control register 2 (cbnctl2) csibn status register (cbnstr) the following shows the block diagram of csibn. figure 18-1. block diagram of csibn cbnctl2 cbnctl0 cbnstr intcbnr sobn intcbnt cbntx so latch cbnrx cbnctl1 sibn f brgm f cclk f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 sckbn internal bus controller phase control shift register phase control selector remarks f cclk : communication clock f xx : main clock frequency f brgm : brgm count clock n = 0 to 4 m = 1 (n = 0, 1) m = 2 (n = 2, 3) m = 3 (n = 4)
v850es/jg3-l chapter 18 clocked serial interface b (csib) r01uh0165ej0700 rev.7.00 page 631 of 1113 sep 22, 2011 18.2.1 pin functions of each channel the sibn, sobn, and sckbn pins used by csib in the v 850es/jg3-l are used for other functions as shown in table 18-2. to use these pins for csib, set the related registers as described in table 4-15 settings when pins are used for alternate functions . table 18-2. pins used by csib pin no. channel gf gc f1 port csib reception input csib transmission output csib clock i/o other functions 24 22 k1 p40 sib0 ? ? sda01 25 23 k2 p41 ? sob0 ? scl01 csib0 26 24 l2 p42 ? ? sckb0 ? 52 50 j11 p97 sib1 ? ? a7(/rxdc0) note /tip20/top20 53 51 j10 p98 ? sob1 ? a8 csib1 54 52 h11 p99 ? ? sckb1 a9 42 40 l8 p53 sib2 ? ? kr3/tiq00/toq00/rtp03/ddo 43 41 k8 p54 ? sob2 ? kr4/rtp04/dck csib2 44 42 j8 p55 ? ? sckb2 kr5/rtp05/dms 55 53 h10 p910 sib3 ? ? a10 56 54 h9 p911 ? sob3 ? a11 csib3 57 55 g11 p912 ? ? sckb3 a12 28 26 k4 p31 sib4 ? ? rxda0/intp7 27 25 l3 p30 ? sob4 ? txda0 csib4 29 27 l4 p32 ? ? sckb4 ascka0/tip00/top00 note pd70f3792, 70f3793, 70f 3841, 70f3842 only remark gf: 100-pin plastic lqfp (14 20) ( pd70f3737, 70f3738 only) gc: 100-pin plastic lqfp (fine-pitch) (14 14) f1: 121-pin plastic fbga (8 8)
v850es/jg3-l chapter 18 clocked serial interface b (csib) r01uh0165ej0700 rev.7.00 page 632 of 1113 sep 22, 2011 18.3 mode switching of csib and other serial interfaces 18.3.1 csib0 and i 2 c01 mode switching in the v850es/jg3-l, csib0 and i 2 c01 share pins and therefore cannot be used simultaneously. to use the csib0 function, specify the csib0 mode in advan ce by using the pmc4 and pfc4 registers. switching the operation mode between csib0 and i 2 c01 is described below. caution transmission and reception by csib0 and i 2 c01 are not guaranteed if these operation modes are switched during transmission or reception. be su re to disable the serial interface that is not being used. figure 18-2. switching csib0 and i 2 c01 operation modes port i/o mode csib0 mode i 2 c01 mode pmc4n 0 1 1 operation mode pfc4n 0 1 0 pmc4 0 0 0 0 pmc42 pmc41 pmc40 after reset: 00h r/w address: fffff448h pfc4 after reset: 00h r/w address: fffff468h 0 0 0 0 0 0 pfc41 pfc40 remarks 1. n = 0, 1 2. = don?t care
v850es/jg3-l chapter 18 clocked serial interface b (csib) r01uh0165ej0700 rev.7.00 page 633 of 1113 sep 22, 2011 18.3.2 csib4 and uarta0 mode switching in the v850es/jg3-l, csib4 and uarta0 share pins and therefore cannot be used simultaneously. to use the csib4 function, specify the csib4 mode in advance by using the pmc3, pfc3, and pfce3l registers. switching the operation mode between csib4 and uarta0 is described below. caution transmission and reception by csib4 and uarta0 are not guaranteed if these operation modes are switched during transmission or reception. be sure to disable the serial interface that is not being used. figure 18-3. switching csib4 and uarta0 operation modes pmc3 after reset: 0000h r/w address: fffff446h, fffff447h 0 0 pmc35 pmc34 pmc33 pmc32 pmc31 pmc30 0 0 0 0 0 0 pmc39 pmc38 8 9 10 11 12 13 14 15 pfc3 after reset: 0000h r/w address: fffff466h, fffff467h 0 0 0 0 0 0 pfc39 pfc38 0 0 pfc35 pfc34 pfc33 pfc32 pfc31 pfc30 8 9 10 11 12 13 14 15 pfce3l after reset: 00h r/w address: fffff706h 0 0 0 0 0 pfce32 0 0 port i/o mode ascka0 mode sckb4 mode port i/o mode uarta0 mode csib4 mode pmc32 0 1 1 pmc3n 0 1 1 operation mode operation mode pfce32 0 0 pfc32 0 1 pfc3n 0 1 remarks 1. n = 0, 1 2. = don?t care
v850es/jg3-l chapter 18 clocked serial interface b (csib) r01uh0165ej0700 rev.7.00 page 634 of 1113 sep 22, 2011 18.4 registers the following registers are used to control csibn. ? csibn receive data register (cbnrx) ? csibn transmit data register (cbntx) ? csibn control register 0 (cbnctl0) ? csibn control register 1 (cbnctl1) ? csibn control register 2 (cbnctl2) ? csibn status register (cbnstr) (1) csibn receive data register (cbnrx) the cbnrx register is a 16-bit buffer register that holds receive data. this register is read-only, in 16-bit units. the receive operation is started by readin g the cbnrx register in reception mode. if the transfer data length is 8 bits, the lower 8 bits of this register are read-only in 8-bit units as the cbnrxl register. reset sets this register to 0000h. in addition to reset input, the cbnrx register can be initialized by clearing (to 0) the cbnpwr bit of the cbnctl0 register. after reset: 0000h r address: cb0rx fffffd04h, cb1rx fffffd14h, cb2rx fffffd24h, cb3rx fffffd34h, cb4rx fffffd44h cbnrx (n = 0 to 4)
v850es/jg3-l chapter 18 clocked serial interface b (csib) r01uh0165ej0700 rev.7.00 page 635 of 1113 sep 22, 2011 (2) csibn transmit data register (cbntx) the cbntx register is a 16-bit buffer regist er used to write the csibn transfer data. this register can be read or written in 16-bit units. the transmit operation is started by writing data to the cbntx register when transmission is enabled. if the transfer data length is 8 bits, the lower 8 bits of this register are read-only in 8-bit units as the cbntxl register. reset sets this register to 0000h. after reset 0000h r/w address: cb0tx fffffd06h, cb1tx fffffd16h, cb2tx fffffd26h, cb3tx fffffd36h, cb4tx fffffd46h cbntx (n = 0 to 4) remark the communication start conditions are shown below. transmission mode (cbntxe bit = 1, cbnrxe bit = 0): write to cbntx register transmission/reception mode (cbntxe bit = 1, cbnrxe bit = 1): write to cbntx register reception mode (cbntxe bit = 0, cbnrxe bit = 1): read from cbnrx register
v850es/jg3-l chapter 18 clocked serial interface b (csib) r01uh0165ej0700 rev.7.00 page 636 of 1113 sep 22, 2011 (3) csibn control register 0 (cbnctl0) cbnctl0 is an 8-bit register that controls csibn serial transfer. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 01h. (1/3) cbnpwr disable csibn operation and reset the cbnstr register enable csibn operation cbnpwr 0 1 specification of csibn operation disable/enable cbnctl0 (n = 0 to 4) cbntxe note cbnrxe note cbndir note 00 cbntms note cbnsce after reset: 01h r/w address: cb0ctl0 fffffd00h, cb1ctl0 fffffd10h, cb2ctl0 fffffd20h, cb3ctl0 fffffd30h, cb4ctl0 fffffd40h ? the cbnpwr bit controls the csibn operation and resets the internal circuit. disable transmit operation enable transmit operation cbntxe note 0 1 specification of transmit operation disable/enable ? the sobn output is low level when the cbntxe bit is 0. ? when the cbnrxe bit is 0, no reception complete interrupt is output even when the specified data is transferred, and the receive data (in the cbnrx register) is not updated. disable receive operation enable receive operation cbnrxe note 0 1 specification of receive operation disable/enable < > < > < > < > < > note these bits can only be rewritten when the cbnpwr bit is 0. however, the values of these bits can be changed to 0 or 1 at the same time the cbnpwr bit is set. caution to forcibly suspend transmission/reception, clear the cbnpwr bit to 0 instead of the cbnrxe and cbntxe bits. at this time, the clock output is stopped.
v850es/jg3-l chapter 18 clocked serial interface b (csib) r01uh0165ej0700 rev.7.00 page 637 of 1113 sep 22, 2011 (2/3) single transfer mode continuous transfer mode cbntms note 0 1 transfer mode specification [in single transfer mode] ? in this mode, the reception complete interrupt (intcbnr) occurs upon completion of communication. the transmission enable interrupt (intcbnt) does not occur even if transmission is enabled (cbntxe bit = 1). ? after the reception complete interrupt (intcbnr) occurs, writing/reading the next transmit/receive data triggers the next communication. ? the next communication does not start even if the next transmit/receive data is written/read during the preceding communication (cbnstr.cbntsf bit = 1). [in continuous transfer mode] ? in this mode and with transmission enabled (cbntxe bit = 1), the transmission enable interrupt (intcbnt) occurs when writing the next transmit data becomes possible. with reception enabled (cbnrxe bit = 1), the reception complete interrupt (intcbnr) occurs upon completion of transfer. ? writing the next transmit data becomes possible after intcbnt occurs. if new data is written at this time, continuous transfer can be performed. ? if reception-only is specified (cbntxe bit = 0, cbnrxe bit = 1), the next transmission starts immediately after intcbnr has occurred, regardless of the progress of reading the cbnrx register. be sure to read receive data immediately after intcbnr has occurred. if receive data is not read before the next intcbnr occurs, an overrun error will occur (cbnstr.cbnove bit = 1). cbndir note 0 1 specification of transfer direction mode (msb/lsb) msb-first transfer lsb-first transfer note these bits can only be rewritten when the cbnpwr bit is 0. however, the values of these bits can be changed to 0 or 1 at the same time the cbnpwr bit is set.
v850es/jg3-l chapter 18 clocked serial interface b (csib) r01uh0165ej0700 rev.7.00 page 638 of 1113 sep 22, 2011 (3/3) communication start trigger invalid communication start trigger valid cbnsce 0 1 specification of start transfer disable/enable this bit enables or disables the communication start trigger in reception mode. ? in master mode (a) in single transmission or transmission/reception mode, or continuous transmission or continuous transmission/reception mode: the setting of the cbnsce bit has no effect on communication. (b) in single reception mode: clear the cbnsce bit to 0 before reading the last receive data to disable the start of reception because reception is started by reading the receive data (cbnrx register) note 1 . (c) in continuous reception mode clear the cbnsce bit to 0 one communication clock cycle before reception of the last data is completed to disable the start of reception after the last data is received note 2 . ? in slave mode set the cbnsce bit to 1. [usage of cbnsce bit] ? in single reception mode <1>when reception of the last data is completed by intcbnr interrupt servicing, clear the cbnsce bit to 0 before reading the cbnrx register. <2> after confirming that the cbnstr.cbntsf bit is 0, clear the cbnpwr and cbnrxe bits to 0 to disable reception. to receive data again, set the cbnsce bit to 1 to start the next reception by dummy-reading the cbnrx register. ? in continuous reception mode <1> clear the cbnsce bit to 0 in the intcbnr interrupt servicing for the receive data immediately before the last one. <2>read the cbnrx register. <3>read the last reception data by reading the cbnrx register after acknowledging the cbntir interrupt. <4> after confirming that the cbnstr.cbntsf bit is 0, clear the cbnpwr and cbnrxe bits to 0 to disable reception. to receive data again, set the cbnsce bit to 1 to wait for the next reception by dummy-reading the cbnrx register. notes 1. if the cbnrx register is read with the cbnsce bit set to 1, the next communication is started. 2. if the cbnsce bit is not cleared to 0, one communication clock cycle before reception of the last data is completed, the next communication is automatically started. caution be sure to clear bits 3 and 2 to ?0?.
v850es/jg3-l chapter 18 clocked serial interface b (csib) r01uh0165ej0700 rev.7.00 page 639 of 1113 sep 22, 2011 (4) csibn control register 1 (cbnctl1) cbnctl1 is an 8-bit register that is used to specify the csibn serial transfer operation mode. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. caution the cbnctl1 register can be rewritten only when the cbnctl0.cbnpwr bit is 0. 0 cbnckp 0 0 1 1 specification of data transmission/ reception timing in relation to sckbn cbnctl1 (n = 0 to 4) 0 cbndap 0 1 0 1 0 cbnckp cbndap cbncks2 cbncks1 cbncks0 after reset 00h r/w address: cb0ctl1 fffffd01h, cb1ctl1 fffffd11h, cb2ctl1 fffffd21h, cb3ctl1 fffffd31h, cb4ctl1 fffffd41h cbncks2 0 0 0 0 1 1 1 1 cbncks1 0 0 1 1 0 0 1 1 cbncks0 0 1 0 1 0 1 0 1 communication clock (f cclk ) note f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f brgm external clock (sckbn) master mode master mode master mode master mode master mode master mode master mode slave mode mode d7 d6 d5 d4 d3 d2 d1 d0 sckbn (i/o) sibn capture sobn (output) d7 d6 d5 d4 d3 d2 d1 d0 sckbn (i/o) sibn capture sobn (output) d7 d6 d5 d4 d3 d2 d1 d0 sckbn (i/o) sibn capture (output) d7 d6 d5 d4 d3 d2 d1 d0 sckbn (i/o) sibn capture (output) communication type 1 communication type 2 communication type 3 communication type 4 note set the communication clock (f cclk ) to 8 mhz or lower. remark when n = 0, 1, m = 1 when n = 2, 3, m = 2 when n = 4, m = 3 for details of fbrgm, see 18.8 baud rate generator .
v850es/jg3-l chapter 18 clocked serial interface b (csib) r01uh0165ej0700 rev.7.00 page 640 of 1113 sep 22, 2011 (5) csibn control register 2 (cbnctl2) cbnctl2 is an 8-bit register that is used to specify the csibn serial transfer data length. this register can be read or written in 8-bit units. reset sets this register to 00h. caution the cbnctl2 register can be rewritten only when the cbnctl0.cbnpwr bit is 0 or when both the cbntxe and cbnrxe bits are 0. after reset: 00h r/w address: cb0ctl2 fffffd02h, cb1ctl2 fffffd12h, cb2ctl2 fffffd22h, cb3ctl2 fffffd32h, cb4ctl2 fffffd42h 0 cbnctl2 (n = 0 to 4) 0 0 0 cbncl3 cbncl2 cbncl1 cbncl0 8 bits 9 bits 10 bits 11 bits 12 bits 13 bits 14 bits 15 bits 16 bits cbncl3 0 0 0 0 0 0 0 0 1 cbncl2 0 0 0 0 1 1 1 1 cbncl1 0 0 1 1 0 0 1 1 cbncl0 0 1 0 1 0 1 0 1 transfer data length remarks 1. if the transfer data length is other than 8 or 16 bits, set the data to the cbntx or cbnrx regist er starting from the lsb. 2. : don?t care
v850es/jg3-l chapter 18 clocked serial interface b (csib) r01uh0165ej0700 rev.7.00 page 641 of 1113 sep 22, 2011 (a) changing the transfer data length the csibn transfer data length can be set in 1-bit units between 8 and 16 bits using the cbnctl2.cbncl3 to cbnctl2.cbncl0 bits. when the transfer data length is set to a value other than 16 bits, the data must be set to the cbntx or cbnrx register starting from the lsb, regardless of whether the transfer start bit is the msb or lsb. any data can be set for the higher bi ts that are not used, but the received data becomes 0 following serial transfer. figure 18-4. example of operation with tran sfer data length set to other than 16 bits (i) transfer data length = 10 bits, msb first 15 10 9 0 sobn sibn insertion of 0 (ii) transfer data length = 12 bits, lsb first 0 sobn 11 12 15 sibn insertion of 0
v850es/jg3-l chapter 18 clocked serial interface b (csib) r01uh0165ej0700 rev.7.00 page 642 of 1113 sep 22, 2011 (6) csibn status register (cbnstr) cbnstr is an 8-bit register t hat displays the csibn status. this register can be read or written in 8-bit or 1-bit units, but the cbntsf flag is read-only. reset sets this register to 00h. in addition to reset input, the cbnstr register can be initialized by clearing (0) the cbnctl0.cbnpwr bit. cbntsf communication stopped communicating cbntsf 0 1 communication status flag cbnstr (n = 0 to 4) 00 0 00 0 cbnove after reset 00h r/w address: cb0str fffffd03h, cb1str fffffd13h, cb2str fffffd23h, cb3str fffffd33h, cb4str fffffd43h ? during transmission, this register is set when data is prepared in the cbntx register, and during reception, it is set when a dummy read of the cbnrx register is performed. when transfer ends, this flag is cleared to 0 at the last edge of the clock cycle. no overrun overrun cbnove 0 1 overrun error flag ? an overrun error occurs when the next reception is completed without the cpu reading the value of the receive buffer, during reception or upon completion of a receive operation. the cbnove flag displays the overrun error occurrence status in this case. ? the cbnove bit is valid also in the single transfer mode. therefore, when only using transmission, note the following. ? do not check the cbnove flag. ? read this bit even if reading the receive data is not required. ? the cbnove flag is cleared by writing 0 to it. it cannot be set even by writing 1 to it. < > < >
v850es/jg3-l chapter 18 clocked serial interface b (csib) r01uh0165ej0700 rev.7.00 page 643 of 1113 sep 22, 2011 18.5 interrupt request signals csibn can generate the following two interrupt request signals. ? reception complete interrupt request signal (intcbnr) ? transmission enable interrupt request signal (intcbnt) of these two interrupt request signals, the reception complete interrupt request signal has the higher priority by default, and the priority of the transmission enable interrupt request signal is lower. table 18-3. interrupts and their default priority interrupt request signal priority reception complete high transmission enable low (1) reception complete interrupt request signal (intcbnr) when receive data is transferred to the cbnrx register while reception is enabled, the reception complete interrupt request signal is generated. this interrupt request signal can also be generated if an overrun error occurs. when the reception complete interrupt request signa l is acknowledged and the data is read, read the cbnstr register to check that the re sult of reception is not an error. in the single transfer mode, the intcbnr interrupt request signal is generated upon completion of transmission, even when only transmission is executed. (2) transmission enable interr upt request signal (intcbnt) in the continuous transmission or continuous transmissi on/reception mode, transmit data is transferred from the cbntx register and, as soon as writing to cbntx has been enab led, the transmission enable interrupt request signal is generated. in the single transmission and single transmission/receptio n modes, the intcbnt interrupt is not generated.
v850es/jg3-l chapter 18 clocked serial interface b (csib) r01uh0165ej0700 rev.7.00 page 644 of 1113 sep 22, 2011 18.6 operation 18.6.1 single transfer mode (mast er mode, transmission mode) msb first (cbnctl0.cbndir bit = 0), communication type 1 (cbnctl1.cbnckp and cbnctl1.cbndap bits = 00), communication clock (f cclk ) = f xx /2 (cbnctl1.cbncks2 to cbnctl1. cbncks0 bits = 000), transfer data length = 8 bits (cbnctl2.cbncl3 to cbnctl2.cbncl0 bits = 0000) figure 18-5. single transfer mode oper ation (master mode, transmission mode) start no (1), (2), (3) (4) (5) (6) (8) no (7) intcbnr interrupt generated? transmission completed? end yes yes cbnctl1 register 00h cbnctl2 register 00h cbnctl0 register c1h write cbntx register start transmission cbnctl0 register 00h remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in figure 18-6 . 3. n = 0 to 4
v850es/jg3-l chapter 18 clocked serial interface b (csib) r01uh0165ej0700 rev.7.00 page 645 of 1113 sep 22, 2011 figure 18-6. single transfer mode operati on timing (master mode, transmission mode) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sckbn pin cbntsf bit (1) (2) (3) (4) (5) (6) (7) (8) sobn pin intcbnr signal (1) write 00h to the cbnctl1 register, and sele ct communication type 1, communication clock (f cclk ) = f xx /2, and master mode. (2) write 00h to the cbnctl2 register, and set the transfer data length to 8 bits. (3) write c1h to the cbnctl0 register, and select t he transmission mode and msb first at the same time as enabling the operation of the communication clock (f cclk ). (4) the cbnstr.cbntsf bit is set to 1 by writing t he transmit data to the cbntx register, and transmission is started. (5) when transmission is started, output the serial clock to the sc kbn pin, and output the transmit data from the sobn pin in synchronization with the serial clock. (6) when transmission of data of the transfer data l ength set by the cbnctl2 register is completed, stop the serial clock output and transm it data output, generate the reception complete interrupt request signal (intcbnr) at the last edge of the serial clock cycle, and clear the cbntsf bit to 0. (7) to continue transmission, repeat the above steps from (4) after the intcbnr signal is generated. (8) to end transmission, clear the cbnctl0. cbnpwr and cbnctl0.cbntxe bits to 0. remark n = 0 to 4
v850es/jg3-l chapter 18 clocked serial interface b (csib) r01uh0165ej0700 rev.7.00 page 646 of 1113 sep 22, 2011 18.6.2 single transfer mode (m aster mode, reception mode) msb first (cbnctl0.cbndir bit = 0), communication type 1 (cbnctl1.cbnckp and cbnctl1.cbndap bits = 00), communication clock (f cclk ) = f xx /2 (cbnctl1.cbncks2 to cbnctl1. cbncks0 bits = 000), transfer data length = 8 bits (cbnctl2.cbncl3 to cbnctl2.cbncl0 bits = 0000) figure 18-7. single transfer mode op eration (master mode, reception mode) start no intcbnr interrupt generated? reception completed? end yes yes no (7) cbnrx register dummy read cbnsce bit = 0 (cbnctl0) cbnctl0 register 00h read cbnrx register read cbnrx register cbnctl1 register 00h cbnctl2 register 00h cbnctl0 register a1h start reception (1), (2), (3) (4) (5) (6) (8) (9) (10) remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in figure 18-8 . 3. n = 0 to 4
v850es/jg3-l chapter 18 clocked serial interface b (csib) r01uh0165ej0700 rev.7.00 page 647 of 1113 sep 22, 2011 figure 18-8. single transfer mode operat ion timing (master mode, reception mode) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 sckbn pin cbntsf bit (1) (2) (3) (4) (5) (6) (7) (10) (8) (9) sibn pin sibn pin capture timing intcbnr signal (1) write 00h to the cbnctl1 register, and select communication type 1, communication clock (f cclk ) = f xx /2, and master mode. (2) write 00h to the cbnctl2 register, and set the transfer data length to 8 bits. (3) write a1h to the cbnctl0 register, and select t he reception mode and msb first at the same time as enabling the operation of the communication clock (f cclk ). (4) the cbnstr.cbntsf bit is set to 1 by performi ng a dummy read of the cbnrx register, and reception is started. (5) when reception is started, output the serial clock to the sckbn pin, and capture the receive data of the sibn pin in synchronization with the serial clock. (6) when reception of data of the transfer data length set by the cbnctl 2 register is co mpleted, stop the serial clock output and data capt uring, generate the reception comp lete interrupt request signal (intcbnr) at the last edge of the serial clock cycle, and clear the cbntsf bit to 0. (7) to continue reception, read the cbnrx regist er with the cbnctl0.cbnsce bit set to 1 after the intcbnr signal is generated. (8) to read the cbnrx register without starting t he next reception, clear the cbnsce bit to 0. (9) read the cbnrx register. (10) to end reception, clear the cbnct l0.cbnpwr and cbnctl0.cbnrxe bits to 0. remark n = 0 to 4
v850es/jg3-l chapter 18 clocked serial interface b (csib) r01uh0165ej0700 rev.7.00 page 648 of 1113 sep 22, 2011 18.6.3 single transfer mode (master mode, transmission/reception mode) msb first (cbnctl0.cbndir bit = 0), communication type 1 (cbnctl1.cbnckp and cbnctl1.cbndap bits = 00), communication clock (f cclk ) = f xx /2 (cbnctl1.cbncks2 to cbnctl1. cbncks0 bits = 000), transfer data length = 8 bits (cbnctl2.cbncl3 to cbnctl2.cbncl0 bits = 0000) figure 18-9. single transfer mode operati on (master mode, transmission/reception mode) start (1), (2), (3) (4) (7), (9) (5) (6) (10) no (8) transmission/reception completed? end yes cbnctl1 register 00h cbnctl2 register 00h cbnctl0 register e1h write cbntx register read cbnrx register start transmission/reception cbnctl0 00h no intcbnr interrupt generated? yes remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in figure 18-10 . 3. n = 0 to 4
v850es/jg3-l chapter 18 clocked serial interface b (csib) r01uh0165ej0700 rev.7.00 page 649 of 1113 sep 22, 2011 figure 18-10. single transfer mode operation timing (master mode, transmission/reception mode) sckbn pin cbntsf bit (1) (2) (3) (4) (5) (6) (8) (7) (10) (9) sibn pin bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 sobn pin sibn pin capture timing intcbnr signal (1) write 00h to the cbnctl1 register, and sele ct communication type 1, communication clock (f cclk ) = f xx /2, and master mode. (2) write 00h to the cbnctl2 register, and set the transfer data length to 8 bits. (3) write e1h to the cbnctl0 register, and select the transmission/reception mode and msb first at the same time as enabling the operation of the communication clock (f cclk ). (4) the cbnstr.cbntsf bit is set to 1 by writ ing the transmit data to the cbntx register, and transmission/reception is started. (5) when transmission/reception is st arted, output the serial clock to the sckbn pin, output the transmit data to the sobn pin in synchronization with the seri al clock, and capture the re ceive data of the sibn pin. (6) when transmission/reception of data of the trans fer data length set by t he cbnctl2 register is completed, stop the serial clock output, transmit dat a output, and data capturing, generate the reception complete interrupt request signal (intcbnr) at the last edge of the serial clo ck cycle, and clear the cbntsf bit to 0. (7) read the cbnrx register. (8) to continue transmission/reception, repeat the above steps from (4). (9) read the cbnrx register. (10) to end transmission/reception, clear the cbnctl0.cbnpwr, cbnctl0.cbntxe, and cbnctl0.cbnrxe bits to 0. remark n = 0 to 4
v850es/jg3-l chapter 18 clocked serial interface b (csib) r01uh0165ej0700 rev.7.00 page 650 of 1113 sep 22, 2011 18.6.4 single transfer mode (s lave mode, transmission mode) msb first (cbnctl0.cbndir bit = 0), communication type 1 (cbnctl1.cbnckp and cbnctl1.cbndap bits = 00), communication clock (f cclk ) = external clock (sckbn) (cbnctl1.cbncks2 to cbnctl1.cbncks0 bits = 111), transfer data length = 8 bits (cbnctl2. cbncl3 to cbnctl2.cbncl0 bits = 0000) figure 18-11. single transfer mode op eration (slave mode, transmission mode) start no (1), (2), (3) (4) (5) (4) (6) (8) no (7) intcbnr interrupt generated? transmission completed? end yes yes cbnctl1 register 07h cbnctl2 register 00h cbnctl0 register c1h write cbntx register note start transmission cbnctl0 00h no yes sckbn pin input started? note if the serial clock is input via the sckbn pin of t he master before the cbntx re gister is written, data cannot be transmitted normally. in this case , initialize both the master and the slave. remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in figure 18-12 . 3. n = 0 to 4
v850es/jg3-l chapter 18 clocked serial interface b (csib) r01uh0165ej0700 rev.7.00 page 651 of 1113 sep 22, 2011 figure 18-12. single transfer mode oper ation timing (slave mode, transmission mode) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 sckbn pin cbntsf bit (1) (2) (3) (4) (5) (6) (7) (8) sobn pin intcbnr signal (1) write 07h to the cbnctl1 register, and sele ct communication type 1, communication clock (f cclk ) = external clock (sckbn), and slave mode. (2) write 00h to the cbnctl2 register, and set the transfer data length to 8 bits. (3) write c1h to the cbnctl0 register, and select t he transmission mode and msb first at the same time as enabling the operation of the communication clock (f cclk ). (4) the cbnstr.cbntsf bit is set to 1 by writing the transmit data to the cb ntx register, and the device waits for serial clock input. (5) when the serial clock is input, output the transmit data from the sobn pin in synchronization with the serial clock. (6) when transmission of data of the transfer data length specified by the cbnctl2 register is completed, generate the reception complete interrupt request sign al (intcbnr) at the last edge of the serial clock cycle, stop the serial clock input and transmit dat a output, and then clear the cbntsf bit to 0. (7) to continue transmission, repeat the above steps from (4) after the intcbnr signal is generated. (8) to end transmission, clear the cbnctl0. cbnpwr and cbnctl0.cbntxe bits to 0. remark n = 0 to 4
v850es/jg3-l chapter 18 clocked serial interface b (csib) r01uh0165ej0700 rev.7.00 page 652 of 1113 sep 22, 2011 18.6.5 single transfer mode (slave mode, reception mode) msb first (cbnctl0.cbndir bit = 0), communication type 1 (cbnctl1.cbnckp and cbnctl1.cbndap bits = 00), communication clock (f cclk ) = external clock (sckbn) (cbnctl1.cbncks2 to cbnctl1.cbncks0 bits = 111), transfer data length = 8 bits (cbnctl2. cbncl3 to cbnctl2.cbncl0 bits = 0000)
v850es/jg3-l chapter 18 clocked serial interface b (csib) r01uh0165ej0700 rev.7.00 page 653 of 1113 sep 22, 2011 figure 18-13. single transfer mode operation (slave mode, reception mode) start reception completed? end yes no (7) cbnrx register dummy read note cbnsce bit = 0 (cbnctl0) cbnctl0 register 00h read cbnrx register read cbnrx register cbnctl1 register 07h cbnctl2 register 00h cbnctl0 register a1h start reception no intcbnr interrupt generated? yes no yes (1), (2), (3) (4) (5) (4) (6) (6) (8) (9) (10) sckbn pin input started? note if the serial clock is input via the sckbn pi n of the master before a dummy-read of the cbnrx register is executed, data cannot be received normally. in this case, initialize both the master and the slave. remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in figure 18-14 . 3. n = 0 to 4
v850es/jg3-l chapter 18 clocked serial interface b (csib) r01uh0165ej0700 rev.7.00 page 654 of 1113 sep 22, 2011 figure 18-14. single transfer mode op eration timing (slave mode, reception mode) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sckbn pin cbntsf bit (1) (2) (3) (4) (5) (6) (7) (10) (8) (9) sibn pin sibn pin capture timing intcbnr signal (1) write 07h to the cbnctl1 register, and select communication type 1, communication clock (f cclk ) = external clock (sckbn), and slave mode. (2) write 00h to the cbnctl2 register, and set the transfer data length to 8 bits. (3) write a1h to the cbnctl0 register, and select t he reception mode and msb first at the same time as enabling the operation of the communication clock (f cclk ). (4) the cbnstr.cbntsf bit is set to 1 by perf orming a dummy read of the cbnrx register, and the device waits for serial clock input. (5) when the serial clock is input, capture the receive data of the sibn pin in synchronization with the serial clock. (6) when reception of the data of transfer data length set by the cbnctl 2 register is co mpleted, stop the serial clock input and data captur ing, generate the reception complete interrupt request signal (intcbnr) at the last edge of the serial clock, and clear the cbntsf bit to 0. (7) to continue reception, read the cbnrx regist er with the cbnctl0.cbnsce bit set to 1 after the intcbnr signal is generated, and wait for serial clock input. (8) to end reception, clear the cbnsce bit to 0. (9) read the cbnrx register. (10) clear the cbnctl0.cbnpwr and cbnctl0.cbnrxe bits to 0. remark n = 0 to 4
v850es/jg3-l chapter 18 clocked serial interface b (csib) r01uh0165ej0700 rev.7.00 page 655 of 1113 sep 22, 2011 18.6.6 single transfer mode (slave mode, transmission/reception mode) msb first (cbnctl0.cbndir bit = 0), communication type 1 (cbnctl1.cbnckp and cbnctl1.cbndap bits = 00), communication clock (f cclk ) = external clock (sckbn) (cbnctl1.cbncks2 to cbnctl1.cbncks0 bits = 111), transfer data length = 8 bits (cbnctl2. cbncl3 to cbnctl2.cbncl0 bits = 0000) figure 18-15. single transfer mode operat ion (slave mode, transmission/reception mode) start (1), (2), (3) (4) (7), (9) (5) (4) (6) (10) no (8) transmission/reception completed? end yes cbnctl1 register 07h cbnctl2 register 00h cbnctl0 register e1h write cbntx register note read cbnrx register start transmission/reception cbnctl0 00h no intcbnr interrupt generated? yes no yes sckbn pin input started? note if the serial clock is input via the sckbn pin of t he master before the cbntx re gister is written, data cannot be transmitted/received normally. in th is case, initialize both t he master and the slave. remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in figure 18-16 . 3. n = 0 to 4
v850es/jg3-l chapter 18 clocked serial interface b (csib) r01uh0165ej0700 rev.7.00 page 656 of 1113 sep 22, 2011 figure 18-16. single transfer mode operati on timing (slave mode, tran smission/reception mode) sckbn pin cbntsf bit (1) (2) (3) (4) (5) (6) (8) (7) (10) (9) sibn pin bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sobn pin sibn pin capture timing intcbnr signal (1) write 07h to the cbnctl1 register, and select communication type 1, communication clock (f cclk ) = external clock (sckbn), and slave mode. (2) write 00h to the cbnctl2 register, and set the transfer data length to 8 bits. (3) write e1h to the cbnctl0 register, and select the transmission/reception mode and msb first at the same time as enabling the operation of the communication clock (f cclk ). (4) the cbnstr.cbntsf bit is set to 1 by writing the transmit data to the cb ntx register, and the device waits for serial clock input. (5) when the serial clock is input, output the transmi t data to the sobn pin in synchronization with the serial clock, and capture the receive data of the sibn pin. (6) when transmission/reception of dat a of the transfer data length set by the cbnctl2 register is completed, stop the serial clock input, transmit dat a output, and data capturing, generate the reception complete interrupt request signal (intcbnr) at the last edge of the serial clo ck cycle, and clear the cbntsf bit to 0. (7) read the cbnrx register. (8) to continue transmission/reception, repeat the above steps from (4). (9) read the cbnrx register. (10) to end transmission/reception, clear the cbnctl0.cbnpwr, cbnctl0.cbntxe, and cbnctl0.cbnrxe bits to 0. remark n = 0 to 4
v850es/jg3-l chapter 18 clocked serial interface b (csib) r01uh0165ej0700 rev.7.00 page 657 of 1113 sep 22, 2011 18.6.7 continuous transfer mode (master mode, transmission mode) msb first (cbnctl0.cbndir bit = 0), communication type 1 (cbnctl1.cbnckp and cbnctl1.cbndap bits = 00), communication clock (f cclk ) = f xx /2 (cbnctl1.cbncks2 to cbnctl1. cbncks0 bits = 000), transfer data length = 8 bits (cbnctl2.cbncl3 to cbnctl2.cbncl0 bits = 0000) figure 18-17. continuous transfer mode op eration (master mode, transmission mode) start (1), (2), (3) (4) (5), (8) (11) no (7) transmission completed? end yes cbnctl1 register 00h cbnctl2 register 00h cbnctl0 register c3h write cbntx register start transmission cbnctl0 00h no (6), (9) intcbnt interrupt generated? yes no (10) yes cbntsf bit = 0? (cbnstr register) remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in figure 18-18 . 3. n = 0 to 4
v850es/jg3-l chapter 18 clocked serial interface b (csib) r01uh0165ej0700 rev.7.00 page 658 of 1113 sep 22, 2011 figure 18-18. continuous transfer mode oper ation timing (master mode, transmission mode) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sckbn pin cbntsf bit (1) (2) (3) (4) (5) (6) (7) (8) (9) (11) (10) sobn pin intcbnt signal intcbnr signal l bit 0 (1) write 00h to the cbnctl1 register, and select communication type 1, communication clock (f cclk ) = f xx /2, and master mode. (2) write 00h to the cbnctl2 register, and set the transfer data length to 8 bits. (3) write c3h to the cbnctl0 register, and select the transmission mode, msb first, and continuous transfer mode at the same time as enablin g the operation of the communication clock (f cclk ). (4) the cbnstr.cbntsf bit is se t to 1 by writing the transmit data to the cbntx register, and transmission is started. (5) when transmission is started, output the serial clock to the sc kbn pin, and output the transmit data from the sobn pin in synchronization with the serial clock. (6) when transfer of the transmit data from the cbntx register to the shi ft register is completed and writing to the cbntx register is enabled, the transmission enable interrupt request signal (intcbnt) is generated. (7) to continue transmission, repeat the above steps from (4) after the intcbnt signal is generated. (8) when new transmit data is written to the cbntx register before communication is complete, the next communication is started following the completion of communication. (9) the transfer of the transmit data from the cbntx register to the shift register is completed and the intcbnt signal is generated. to end continuous transmission with the current transmission, do not write to the cbntx register. (10) if the next transmit data is not written to the cbnt x register before transfer is complete, wait for the cbntsf bit to be cleared to 0 after completion of transfer. (11) to disable transmission, clear the cbnct l0.cbnpwr and cbnctl0.cbntxe bits to 0 after confirming that the cbntsf bit is set to 0. caution in continuous transm ission mode, the reception comple te interrupt request signal (intcbnr) is not generated. remark n = 0 to 4
v850es/jg3-l chapter 18 clocked serial interface b (csib) r01uh0165ej0700 rev.7.00 page 659 of 1113 sep 22, 2011 18.6.8 continuous transfer mode (master mode, reception mode) msb first (cbnctl0.cbndir bit = 0), communication type 1 (cbnctl1.cbnckp and cbnctl1.cbndap bits = 00), communication clock (f cclk ) = f xx /2 (cbnctl1.cbncks2 to cbnctl1. cbncks0 bits = 000), transfer data length = 8 bits (cbnctl2.cbncl3 to cbnctl2.cbncl0 bits = 0000) the flowchart in figure 18-19 shows the operation where a specified number of data items are received in the master mode. operations ar e repeated until all the specif ied data items are received. if an overrun error occurs, however, transfer ends. perform error processing as necessary. for details about the overrun error, see 18.6.13 reception errors . the operation timing in figure 18-20 shows a case where no error occurred.
v850es/jg3-l chapter 18 clocked serial interface b (csib) r01uh0165ej0700 rev.7.00 page 660 of 1113 sep 22, 2011 figure 18-19. continuous transfer mode operation (master mode, reception mode) start no end yes no yes overrun error occurred. yes (6) (12) (12) no (9) (7) no yes no yes (9) (10) (11) (8) error processing intcbnr interrupt generated? cbnove bit = 0 (cbnstr) cbnrx register dummy read cbnsce bit = 0 (cbnctl0) cbnove bit = 1? (cbnstr) read cbnrx register is data being received last data? cbnsce bit = 0 (cbnctl0) read cbnrx register cbnctl1 register 00h cbnctl2 register 00h cbnctl0 register a3h start reception (1), (2), (3) (4) (5) read cbnrx register read cbnrx register cbnctl0 register 00h cbntsf bit = 0? (cbnstr) intcbnr interrupt generated? remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in figure 18-20 . 3. n = 0 to 4
v850es/jg3-l chapter 18 clocked serial interface b (csib) r01uh0165ej0700 rev.7.00 page 661 of 1113 sep 22, 2011 figure 18-20. continuous transfer mode oper ation timing (master mode, reception mode) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sckbn pin cbntsf bit (1) (2) (4) (3) (5) (6) (7) (8) (9) (11) (12) (10) sibn pin intcbnr signal cbnsce bit sobn pin l sibn pin capture timing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (1) write 00h to the cbnctl1 register, and select communication type 1, communication clock (f cclk ) = f xx /2, and master mode. (2) write 00h to the cbnctl2 register, and set the transfer data length to 8 bits. (3) write a3h to the cbnctl0 register, and select t he reception mode, msb first, and continuous transfer mode at the same time as enabling the operation of the communication clock (f cclk ). (4) the cbnstr.cbntsf bit is set to 1 by performi ng a dummy read of the cbnrx register, and reception is started. (5) when reception is started, output the serial clock to the sckbn pin, and capture the receive data of the sibn pin in synchronization with the serial clock. (6) when reception is completed, the reception comple te interrupt request signal (intcbnr) is generated, and reading receive data from the cbnrx register is enabled. (7) because the cbnctl0.cbnsce bit was 1 when communication ended, the next communication is started immediately. (8) to end continuous reception with the current reception, clear the cbnsce bit to 0. (9) read the cbnrx register. (10) when reception is completed, the intcbnr signa l is generated and reading receive data from the cbnrx register is enabled. if the cbnsce bit is set to 0 before communica tion is complete, stop the serial clock output to the sckbn pin and clear t he cbntsf bit to 0 to end the receive operation. (11) read the cbnrx register. (12) to disable reception, clear the cbnctl0.cbnpwr and cbnctl0.cbnrxe bits to 0 after confirming that the cbntsf bit is 0. remark n = 0 to 4
v850es/jg3-l chapter 18 clocked serial interface b (csib) r01uh0165ej0700 rev.7.00 page 662 of 1113 sep 22, 2011 18.6.9 continuous transfer mode (mast er mode, transmissi on/reception mode) msb first (cbnctl0.cbndir bit = 0), communication type 1 (cbnctl1.cbnckp and cbnctl1.cbndap bits = 00), communication clock (f cclk ) = f xx /2 (cbnctl1.cbncks2 to cbnctl1. cbncks0 bits = 000), transfer data length = 8 bits (cbnctl2.cbncl3 to cbnctl2.cbncl0 bits = 0000) the flowchart in figure 18-21 shows the operation where th e specified number of transmit/receive data items are transmitted are received in the master mode. operations are repeated until all the specified data items are transmitted/received. if an overrun error occurs, however, transfer ends. perform error processing as necessary. for details about the overrun error, see 18.6.13 reception errors . the operation timing in figure 18-22 shows a case where no error occurred.
v850es/jg3-l chapter 18 clocked serial interface b (csib) r01uh0165ej0700 rev.7.00 page 663 of 1113 sep 22, 2011 figure 18-21. continuous transfer mode operat ion (master mode, transmission/reception mode) start end yes no no no yes (4) (5) (7) (7) (6), (11) (8) (14) (14) (10) no yes no yes yes (11) no is receive data last data? write cbntx register cbnove bit = 0 (cbnstr) read cbnrx register read cbnrx register cbnctl1 register 00h cbnctl2 register 00h cbnctl0 register e3h (1), (2), (3) intcbnt interrupt generated? cbntsf bit = 0? (cbnstr) write cbntx register is data being transmitted last data? start transmission/reception cbnctl0 register 00h cbnove bit = 1? (cbnstr) intcbnr interrupt generated? yes (12) overrun error occurred. error processing (9) remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in figure 18-22 . 3. n = 0 to 4
v850es/jg3-l chapter 18 clocked serial interface b (csib) r01uh0165ej0700 rev.7.00 page 664 of 1113 sep 22, 2011 figure 18-22. continuous transfer mode operation timing (master mode, transmission/reception mode) (1/2) sckbn pin cbntsf bit (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (13) (14) (12) sibn pin bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sobn pin intcbnt signal intcbnr signal sibn pin capture timing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (1) write 00h to the cbnctl1 register, and select communication type 1, communication clock (f cclk ) = f xx /2, and master mode. (2) write 00h to the cbnctl2 register, and set the transfer data length to 8 bits. (3) write e3h to the cbnctl0 register, and select the transmission/reception mode, msb first, and continuous transfer mode at the same time as enabling the operation of the communication clock (f cclk ). (4) the cbnstr.cbntsf bit is se t to 1 by writing the transmit data to the cbntx register, and transmission/reception is started. (5) when transmission/reception is st arted, output the serial clock to the sckbn pin, output the transmit data to the sobn pin in synchronization with the seri al clock, and capture the receive data of the sibn pin. (6) when transfer of the transmit data fr om the cbntx register to the shift register is completed and writing to the cbntx register is enabled, the transmission enable interrupt request signal (intcbnt) is generated. (7) to continue transmission/receptio n, write the transmit data to the cbnrx register again after the intcbnt signal is generated. (8) when one transmission/reception is completed, the reception complete interrupt request signal (intcbnr) is generated, and reading of the cbnrx register is enabled. (9) when new transmit data is written to the cbntx r egister before communication is complete, the next communication is started following completion of communication. (10) read the cbnrx register. remark n = 0 to 4
v850es/jg3-l chapter 18 clocked serial interface b (csib) r01uh0165ej0700 rev.7.00 page 665 of 1113 sep 22, 2011 figure 18-22. continuous transfer mode operation timing (master mode, transmission/reception mode) (2/2) (11) the transfer of the transmit data from the cbntx register to the shift register is completed and the intcbnt signal is generated. to end cont inuous transmission/reception with the current transmission/reception, do not wr ite to the cbntx register. (12) if the next transmit data is not written to the cbnt x register before transfer is complete, stop outputting the serial clock to the sckbn pin and wait for the cbntsf bit to be cleared to 0 after completion of transfer. (13) when the reception complete interrupt req uest signal (intcbnr) is generated, read the cbnrx register. (14) to disable transmission/reception, cl ear the cbnctl0.cbnpwr , cbnctl0.cbntxe, and cbnctl0.cbnrxe bits to 0 after confirmi ng that the cbntsf bit is set to 0. remark n = 0 to 4
v850es/jg3-l chapter 18 clocked serial interface b (csib) r01uh0165ej0700 rev.7.00 page 666 of 1113 sep 22, 2011 18.6.10 continuous transfer mode (slave mode, transmission mode) msb first (cbnctl0.cbndir bit = 0), communication type 1 (cbnctl1.cbnckp and cbnctl1.cbndap bits = 00), communication clock (f cclk ) = external clock (sckbn) (cbnctl1.cbncks2 to cbnctl1.cbncks0 bits = 111), transfer data length = 8 bits (cbnctl2. cbncl3 to cbnctl2.cbncl0 bits = 0000) figure 18-23. continuous transfer mode operation (slave mode, transmission mode) start (1), (2), (3) (4) (4) (5), (8) (11) no (7) transmission completed? end yes cbnctl1 register 07h cbnctl2 register 00h cbnctl0 register c3h write cbntx register note start transmission cbnctl0 register 00h no (10) yes cbntsf bit = 0? (cbnstr register) no (6), (9) intcbnt interrupt generated? yes no (9) yes sckbn pin input started? note if the serial clock is input via the sckbn pin of t he master before the cbntx re gister is written, data cannot be transmitted normally. in this case , initialize both the master and the slave. remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in figure 18-24 . 3. n = 0 to 4
v850es/jg3-l chapter 18 clocked serial interface b (csib) r01uh0165ej0700 rev.7.00 page 667 of 1113 sep 22, 2011 figure 18-24. continuous transfer mode oper ation timing (slave mode, transmission mode) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sckbn pin cbntsf bit (1) (2) (3) (4) (5) (6) (7) (8) (9) (11) (10) sobn pin intcbnt signal bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (1) write 07h to the cbnctl1 register, and select communication type 1, communication clock (f cclk ) = external clock (sckbn), and slave mode. (2) write 00h to the cbnctl2 register, and set the transfer data length to 8 bits. (3) write c3h to the cbnctl0 register, and select the transmission mode, msb first, and continuous transfer mode at the same time as enablin g the operation of the communication clock (f cclk ). (4) the cbnstr.cbntsf bit is set to 1 by writing the transmit data to the cb ntx register, and the device waits for serial clock input. (5) when the serial clock is input, output the transmit data from the sobn pin in synchronization with the serial clock. (6) when transfer of the transmit data from the cbntx register to the shi ft register is completed and writing to the cbntx register is enabled, the transmission enable interrupt request signal (intcbnt) is generated. (7) to continue transmission, repeat the above steps from (4) after the intcbnt signal is generated. (8) when the serial clock is input following completion of the transmission of the transfer data length set by the cbnctl2 register, continu ous transmission is started. (9) when transfer of the transmit data from the cbntx register to the shi ft register is completed and writing to the cbntx register is enabled, the intcbnt si gnal is generated. to end continuous transmission with the current transmission, do not write to the cbntx register. (10) when the number of clock cycles of the transfer data length set by the cbnctl2 register is input without writing to the cbntx register, clea r the cbntsf bit to 0 to end transmission. (11) to disable transmission, clear the cbnct l0.cbnpwr and cbnctl0.cbntxe bits to 0 after confirming that the cbntsf bit is set to 0. caution in continuous transmi ssion mode, the reception comple te interrupt request signal (intcbnr) is not generated. remark n = 0 to 4
v850es/jg3-l chapter 18 clocked serial interface b (csib) r01uh0165ej0700 rev.7.00 page 668 of 1113 sep 22, 2011 18.6.11 continuous transfer m ode (slave mode, reception mode) msb first (cbnctl0.cbndir bit = 0), communication type 1 (cbnctl1.cbnckp and cbnctl1.cbndap bits = 00), communication clock (f cclk ) = external clock (sckbn) (cbnctl1.cbncks2 to cbnctl1.cbncks0 bits = 111), transfer data length = 8 bits (cbnctl2. cbncl3 to cbnctl2.cbncl0 bits = 0000) the flowchart in figure 18-25 shows the operation where t he specified number of data items are received in the slave mode. operations are repeated until all the specif ied data items are received. if an overrun error occurs, however, transfer ends. perform error processing as necessary. for details about the overrun error, see 18.6.13 reception errors . the operation timing in figure 18-26 shows a case where no error occurred.
v850es/jg3-l chapter 18 clocked serial interface b (csib) r01uh0165ej0700 rev.7.00 page 669 of 1113 sep 22, 2011 figure 18-25. continuous transfer mode operation (slave mode, reception mode) start no end yes no yes yes (1), (2), (3) (4) (5) (4) (6) (12) (12) no (9) (7) no yes (9) (10) (11) (8) no yes no yes intcbnr interrupt generated? cbnove bit = 0 (cbnstr) cbnrx register dummy read note cbnsce bit = 0 (cbnctl0) cbnove bit = 1? (cbnstr) read cbnrx register is data being received last data? cbnsce bit = 0 (cbnctl0) read cbnrx register cbnctl1 register 07h cbnctl2 register 00h cbnctl0 register a3h reception start read cbnrx register read cbnrx register cbnctl0 register 00h intcbnr interrupt generated? cbntsf bit = 0? (cbnstr) sckbn pin input started? overrun error occurred. error processing note if the serial clock is input via the sckbn pi n of the master before a dummy-read of the cbnrx register is executed, data cannot be received normally. in this case, initialize both the master and the slave. remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in figure 18-26 . 3. n = 0 to 4
v850es/jg3-l chapter 18 clocked serial interface b (csib) r01uh0165ej0700 rev.7.00 page 670 of 1113 sep 22, 2011 figure 18-26. continuous transfer mode op eration timing (slave mode, reception mode) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sckbn pin cbntsf bit (1) (2) (4) (3) (5) (6) (7) (8) (9) (11) (12) (10) sibn pin intcbnr signal cbnsce bit sibn pin capture timing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (1) write 07h to the cbnctl1 register, and select communication type 1, communication clock (f cclk ) = external clock (sckbn), and slave mode. (2) write 00h to the cbnctl2 register, and set the transfer data length to 8 bits. (3) write a3h to the cbnctl0 register, and select t he reception mode, msb first, and continuous transfer mode at the same time as enabling the operation of the communication clock (f cclk ). (4) the cbnstr.cbntsf bit is set to 1 by perf orming a dummy read of the cbnrx register, and the device waits for serial clock input. (5) when the serial clock is input, capture the receive data of the sibn pin in synchronization with the serial clock. (6) when reception is completed, the reception comple te interrupt request signal (intcbnr) is generated, and reading receive data from the cbnrx register is enabled. (7) when the serial clock is input with the cbnctl0.cbns ce bit set to 1, continuous reception is started. (8) to end continuous reception with the current reception, clear the cbnsce bit to 0. (9) read the cbnrx register. (10) when reception is completed, the intcbnr signal is generated, and reading receive data from the cbnrx register is enabled. if the cbnsce bit is se t to 0 before communication is complete, clear the cbntsf bit to 0 to end the receive operation. (11) read the cbnrx register. (12) to disable reception, clear the cbnctl0.cbnpwr and cbnctl0.cbnrxe bits to 0 after confirming that the cbntsf bit is 0. remark n = 0 to 4
v850es/jg3-l chapter 18 clocked serial interface b (csib) r01uh0165ej0700 rev.7.00 page 671 of 1113 sep 22, 2011 18.6.12 continuous transfer mode (s lave mode, transmission/reception mode) msb first (cbnctl0.cbndir bit = 0), communication type 1 (cbnctl1.cbnckp and cbnctl1.cbndap bits = 00), communication clock (f cclk ) = external clock (sckbn) (cbnctl1.cbncks2 to cbnctl1.cbncks0 bits = 111), transfer data length = 8 bits (cbnctl2. cbncl3 to cbnctl2.cbncl0 bits = 0000) the flowchart in figure 18-27 shows the operation where th e specified number of transmit/receive data items are transmitted/received in the slave mode. operations are repeated until all the specified data items are transmitted/received. if an overrun error occurs, however, transfer ends. perform error processing as necessary. for details about the overrun error, see 18.6.13 reception errors . the operation timing in figure 18-28 shows a case where no error occurred.
v850es/jg3-l chapter 18 clocked serial interface b (csib) r01uh0165ej0700 rev.7.00 page 672 of 1113 sep 22, 2011 figure 18-27. continuous transfer mode operat ion (slave mode, transmission/reception mode) start end yes no yes no no yes (1), (2), (3) (4) (5) (7) (7) (8) (10) (10) (9) no yes yes no (6) no yes (4) no yes is receive data last data? write cbntx register note cbnove bit = 1? (cbnstr) read cbnrx register cbnctl1 register 07h cbnctl2 register 00h cbnctl0 register e3h cbntsf bit = 0? (cbnstr) write cbntx register is data being transmitted last data? start transmission/ reception cbnctl0 register 00h cbnove bit = 0 (cbnstr) intcbnr interrupt generated? intcbnt interrupt generated? sckbn pin input started? error processing note if the serial clock is input via the sckbn pin of t he master before the cbntx re gister is written, data cannot be transmitted/received normally. in th is case, initialize both t he master and the slave. remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in figure 18-28 . 3. n = 0 to 4
v850es/jg3-l chapter 18 clocked serial interface b (csib) r01uh0165ej0700 rev.7.00 page 673 of 1113 sep 22, 2011 figure 18-28. continuous transfer mode operati on timing (slave mode, transmission/reception mode) sckbn pin cbntsf bit (1) (2) (3) (4) (5) (6) (7) (8) (9) (6) (9) (10) (8) sibn pin bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sobn pin intcbnt signal intcbnr signal sibn pin capture timing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (7) (1) write 07h to the cbnctl1 register, and select communication type 1, communication clock (f cclk ) = external clock (sckbn), and slave mode. (2) write 00h to the cbnctl2 register, and set the transfer data length to 8 bits. (3) write e3h to the cbnctl0 register, and select the transmission/reception mode, msb first, and continuous transfer mode at the same time as enabling the operation of the communication clock (f cclk ). (4) the cbnstr.cbntsf bit is set to 1 by writing the transmit data to the cb ntx register, and the device waits for serial clock input. (5) when the serial clock is input, output the transmi t data to the sobn pin in synchronization with the serial clock, and capture the receive data of the sibn pin. (6) when transfer of the transmit data from the cbntx register to the shi ft register is completed and writing to the cbntx register is enabled, the transmission enable interrupt request signal (intcbnt) is generated. (7) to continue transmission, write the transmit data to the cbntx register again after the intcbnt signal is generated. when transfer of transmi t data from the cbntx register to the shift register is complete and writing data to the cbntx register is enabled, the intcbnt signal is generated. to end continuous transmission/reception with the current transmission/reception, do not write data to the cbntx register. (8) when reception of data of the transfer data length set by the cbnc tl2 register is completed, the reception complete interrupt request signal (intcbnr ) is generated, and reading of the cbnrx register is enabled. if the next transmit data is written to the cbntx register in (7) and the serial clock is input immediately, new continuous transmi ssion/reception is started. if the next data is not written to the cbntx register, clear the cbntsf bit to 0 to end the transmission/reception. (9) read the cbnrx register. (10) to disable transmission, clear the cbnc tl0.cbnpwr, cbnctl0.cbntxe, and cbnctl0.cbnrxe bits to 0 after confirming that the cbntsf bit is set to 0. remark n = 0 to 4
v850es/jg3-l chapter 18 clocked serial interface b (csib) r01uh0165ej0700 rev.7.00 page 674 of 1113 sep 22, 2011 18.6.13 reception errors when transfer is performed with reception enabled (cbnctl0.cbnrxe bit = 1) in the continuous transfer mode, the reception complete interrupt request signal (intcbnr) is generated again if the next receive operation is completed before the cbnrx register is read after the intcbnr signal is generated, and the overrun error flag (cbnstr.cbnove) is set to 1. if an overrun error occurs, the previous receive data is lost because the cbnrx regist er is updated. even if a reception error occurs, the intcbnr signal is generated aga in upon completion of the ne xt reception if the cbnrx register is not read. an overrun error occurs if reading the cbnrx register has not been completed half a clock cycle before the last bit of the next receive data is sampled after the intcbnr signal is generated. figure 18-29. overrun error timing sckbn pin cbnrx register read signal (1) (2) (4) 01h 02h 05h 0ah 15h 2ah 55h aah 00h 01h 02h 05h 0ah 15h 2ah 55h shift register aah 55h cbnrx register sibn pin intcbnr signal cbnove bit sibn pin capture timing (3) (1) start of continuous transfer (2) completion of the first transfer (3) the cbnrx register cannot be read until half a clock cycle before the completion of the second transfer. (4) an overrun error occurs, the reception complete interrupt request signal (intcbnr) is generated, and the overrun error flag (cbnstr.cbnove) is set to 1. the receive data is overwritten. remark n = 0 to 4
v850es/jg3-l chapter 18 clocked serial interface b (csib) r01uh0165ej0700 rev.7.00 page 675 of 1113 sep 22, 2011 18.6.14 clock timing figure 18-30. clock timing (1/2) (i) communication type 1 (cbnckp and cbndap bits = 00) d6 d5 d4 d3 d2 d1 sckbn pin sibn capture reg-r/w sobn pin intcbnt interrupt note 1 intcbnr interrupt note 2 cbntsf bit d0 d7 (ii) communication type 3 (cbnckp and cbndap bits = 10) d6 d5 d4 d3 d2 d1 d0 d7 sckbn pin sibn capture reg-r/w sobn pin intcbnt interrupt note 1 intcbnr interrupt note 2 cbntsf bit notes 1. the intcbnt interrupt is set when the data written to the cbntx register is transferred to the data shift register in the continuous transmission or contin uous transmission/reception mode. in the single transmission or single transmission/reception mode, the intcbnt interrupt request signal is not generated, but the intcbnr interrupt request si gnal is generated at the end of communication. 2. the intcbnr interrupt occurs if reception is comple te and the next receive dat a is ready in the cbnrx register while reception is enabled. in the si ngle mode, the intcbnr interrupt request signal is generated even in the transmission mode, at the end of communication. caution in single transfer mode, wr iting to the cbntx register with the cbntsf bit set to 1 is ignored. this has no effect on the operation during transfer.
v850es/jg3-l chapter 18 clocked serial interface b (csib) r01uh0165ej0700 rev.7.00 page 676 of 1113 sep 22, 2011 figure 18-30. clock timing (2/2) (iii) communication type 2 (cbnckp and cbndap bits = 01) d6 d5 d4 d3 d2 d1 d0 d7 sckbn pin sibn capture reg-r/w sobn pin intcbnt interrupt note 1 intcbnr interrupt note 2 cbntsf bit (iv) communication type 4 (cbnckp and cbndap bits = 11) d6 d5 d4 d3 d2 d1 d0 d7 sckbn pin sibn capture reg-r/w sobn pin intcbnt interrupt note 1 intcbnr interrupt note 2 cbntsf bit notes 1. the intcbnt interrupt is set when the data written to the cbntx register is transferred to the data shift register in the continuous transmission or continuo us transmission/reception modes. in the single transmission or single transmission/reception modes , the intcbnt interrupt request signal is not generated, but the intcbnr interrupt request si gnal is generated at the end of communication. 2. the intcbnr interrupt occurs if reception is comple te and the next receive dat a is ready in the cbnrx register while reception is enabled. in the si ngle mode, the intcbnr interrupt request signal is generated even in the transmission m ode, at the end of communication. caution in single transfer mode, writing to the cbntx register with the cbntsf bit set to 1 is ignored. this has no effect on the operation during transfer. for example, if the next data is written to the cbntx register when dma is started by generating the intcbnr signal, the written data is not transferred because the cbntsf bit is set to 1. use the continuous transfer mode, not the single transfer mode, for such applications.
v850es/jg3-l chapter 18 clocked serial interface b (csib) r01uh0165ej0700 rev.7.00 page 677 of 1113 sep 22, 2011 18.7 output pins (1) sckbn pin when csibn is disabled (cbnctl0.cbnpwr bit = 0), the sckbn pin output status is as follows. table 18-4. sckbn pin output status with csibn disabled cbnckp cbncks2 cbncks1 cbncks0 sckbn pin output 1 1 1 high impedance 0 other than above high level 1 1 1 high impedance 1 other than above low level remarks 1. the output level of the sckbn pin changes if any of the cbnctl1.cbnckp and cbncks2 to cbncks0 bits is rewritten. 2. n = 0 to 4 (2) sobn pin when csibn is disabled (cbnpwr bit = 0), the sobn pin output status is as follows. table 18-5. sobn pin output status with csibn disabled cbntxe cbndap cbndir sobn pin output 0 low level 0 low level 0 cbntx0 value (msb) 1 1 1 cbntx0 value (lsb) remarks 1. the sobn pin output changes when any one of the cbnctl0.cbntxe, cbnctl0.cb ndir, and cbnctl1.cbndap bits is rewritten. 2. : don?t care 3. n = 0 to 4
v850es/jg3-l chapter 18 clocked serial interface b (csib) r01uh0165ej0700 rev.7.00 page 678 of 1113 sep 22, 2011 18.8 baud rate generator the brg1 to brg3 and csib0 to csib4 baud rate gener ators are connected as shown in the following block diagram. figure 18-31. baud rate generator connection csib0 csib1 csib2 csib3 csib4 brg1 brg2 brg3 f x f x f x f brg1 f brg2 f brg3 (1) prescaler mode registers 1 to 3 (prsm1 to prsm3) the prsm1 to prsm3 registers control generation of the baud rate signal for csibn. these registers can be read or written in 8-bit or 1-bit units. reset sets these registers to 00h. 0 prsmm (m = 1 to 3) 0 0 bgcem 0 0 bgcsm1 bgcsm0 disabled enabled bgcem 0 1 baud rate output f xx f xx /2 f xx /4 f xx /8 setting value (k) 0 1 2 3 bgcsm1 0 0 1 1 bgcsm0 0 1 0 1 input clock selection (f bgcsm ) after reset: 00h r/w address: prsm1 fffff320h, prsm2 fffff324h, prsm3 fffff328h < > cautions 1. do not rewrite the prsmm register during operation. 2. before setting the bgcem bi t to 1, set the bgcsm1 and bgcsm0 bits and prescaler compare registers 1 to 3 (prscm1 to prscm3). 3. be sure to clear bits 7 to 5, 3 and 2 to ?0?.
v850es/jg3-l chapter 18 clocked serial interface b (csib) r01uh0165ej0700 rev.7.00 page 679 of 1113 sep 22, 2011 (2) prescaler compare registers 1 to 3 (prscm1 to prscm3) the prscm1 to prscm3 registers are 8-bit compare registers. these registers can be read or written in 8-bit units. reset sets these registers to 00h. prscmm7 prscmm prscmm6 prscmm5 prscmm4 prscmm3 prscmm2 prscmm1 prscmm0 after reset: 00h r/w address: prscm1 fffff321h, prscm2 fffff325h, prscm3 fffff329h cautions 1. do not rewrite the pr scmm register during operation. 2. set the prscmm register before setting the prsmm.bgcem bit to 1. 18.8.1 baud rate generation the transmission/reception clock is generated by dividi ng the main clock. the baud rate generated from the main clock is obtained by the following equation. f brgm = caution set f brgm to 8 mhz or lower. remark f brgm : brgm count clock f xx : main clock oscillation frequency k: prsmm register setting value = 0 to 3 n: prscmm register setting value = 1 to 256 however, n = 256 only when prscmm register is set to 00h. m = 1 to 3 f xx 2 k+1 n
v850es/jg3-l chapter 18 clocked serial interface b (csib) r01uh0165ej0700 rev.7.00 page 680 of 1113 sep 22, 2011 18.9 cautions (1) when transferring transmit data and receive data using dma transfer, error processing cannot be performed even if an overrun error occurs during serial transfer. check that the no overrun error has occurred by reading the cbnstr.cbnove bit after dma transfer is complete. (2) in regards to registers that are forbidden must not be rewritten during operations (when the cbnctl0.cbnpwr bit is 1), if rewriting has been carr ied out by mistake, set the cbnctl0.cbnpwr bit to 0 once, then initialize csibn. the registers that must no be rewri tten during operation are shown below. ? cbnctl0 register: cbntxe, cbnrxe, cbndir, cbntms bits ? cbnctl1 register: cbnckp, cbndap, cbncks2 to cbncks0 bits ? cbnctl2 register: cbncl3 to cbncl0 bits (3) in communication type 2 or 4 (cbnctl1.cbndap bit = 1), the cbnstr.cbntsf bit is cleared half a sckbn clock cycle after occurrence of a recept ion complete interrupt (intcbnr). in the single transfer mode, writing the next transmi t data is ignored during communication (cbntsf bit = 1), and the next communication is not started. also if reception-only communication (cbnctl0.cbntxe bit = 0, cbnctl0.cbnrxe bit = 1) is set, the next communication is not started even if t he receive data is read during communication (cbntsf bit = 1). therefore, when using the single transfer mode with communication type 2 or 4 (cbndap bit = 1), pay particular attention to the following. ? to start the next transmission, c onfirm that the cbntsf bit is 0 and then write the transmit data to the cbntx register. ? to perform the next reception continuously when reception-only communication (cbntxe bit = 0, cbnrxe bit = 1) is set, confirm that the cbntsf bit is 0 and then read the cbnrx register. or, use the continuous transfer mode instead of the si ngle transfer mode. use of the continuous transfer mode is recommended especially when using dma. (4) the sib1 and rxdc0 pins cannot be used at the same time. when using the pin for sib1, stop uartc0 reception. (clear the uc0ctl0.uc0rxe bit to 0.) when using the pin for rxdc0, stop csib0 reception. (clear the cb1ctl0.cb1rxe bit to 0.) ( ? pd70f3792, 70f3793, 70f 3841, 70f3842 only.) remark n = 0 to 4
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 681 of 1113 sep 22, 2011 chapter 19 i 2 c bus to use the i 2 c bus function, set the p38/sd a00, p39/scl00, p40/sda01, p41/scl01, p90/sda02, and p91/scl02 pins as the serial transmi t/receive data i/o pins (sda00 to sda 02) and serial clock i/o pins (scl00 to scl02), and set them to n-ch open-drain output. 19.1 mode switching of i 2 c bus and other serial interfaces 19.1.1 uarta2 and i 2 c00 mode switching in the v850es/jg3-l, uarta2 and i 2 c00 share pins and therefore cannot be used simultaneously. set the operation mode to i 2 c00 in advance, using the pmc3 and pfc3 registers. caution the transmit/receive operation of uarta2 and i 2 c00 is not guaranteed if these functions are switched during transmission or reception. be sure to disable the one that is not used. figure 19-1. switching uarta2 and i 2 c00 mode pmc3 after reset: 0000h r/w address: fffff446h, fffff447h 0 0 pmc35 pmc34 pmc33 pmc32 pmc31 pmc30 0 0 0 0 0 0 pmc39 pmc38 8 9 10 11 12 13 14 15 pfc3 after reset: 0000h r/w address: fffff466h, fffff467h 0 0 0 0 0 0 pfc39 pfc38 0 0 pfc35 pfc34 pfc33 pfc32 pfc31 pfc30 8 9 10 11 12 13 14 15 port i/o mode uarta2 mode i 2 c00 mode pmc3n 0 1 1 operation mode pfc3n 0 1 remarks 1. n = 8, 9 2. = don?t care
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 682 of 1113 sep 22, 2011 19.1.2 csib0 and i 2 c01 mode switching in the v850es/jg3-l, csib0 and i 2 c01 share pins and therefore can not be used simultaneously. set the operation mode to i 2 c01 in advance, using the pmc4 and pfc4 registers. caution the transmit/receive operation of csib0 and i 2 c01 is not guaranteed if these functions are switched during transmission or reception. be sure to disable the one that is not used. figure 19-2. switching csib0 and i 2 c01 mode port i/o mode csib0 mode i 2 c01 mode pmc4n 0 1 1 operation mode pfc4n 0 1 0 pmc4 0 0 0 0 pmc42 pmc41 pmc40 after reset: 00h r/w address: fffff448h pfc4 after reset: 00h r/w address: fffff468h 0 0 0 0 0 0 pfc41 pfc40 remarks 1. n = 0, 1 2. = don?t care
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 683 of 1113 sep 22, 2011 19.1.3 uarta1 and i 2 c02 mode switching in the v850es/jg3-l, uarta1 and i 2 c02 share pins and therefore cannot be used simultaneously. set the operation mode to i 2 c02 in advance, using the pmc9, pfc9, and pfce9 registers. caution the transmit/receive operation of uarta1 and i 2 c02 is not guaranteed if these functions are switched during transmission or reception. be sure to disable the one that is not used. figure 19-3. switching uarta1 and i 2 c02 mode pmc9 after reset: 0000h r/w address: fffff452h, fffff453h pmc97 pmc96 pmc95 pmc94 pmc93 pmc92 pmc91 pmc90 pmc915 pmc914 pmc913 pmc912 pmc911 pmc910 pmc99 pmc98 8 9 10 11 12 13 14 15 pfc9 after reset: 0000h r/w address: fffff472h, fffff473h pfc915 pfc914 pfc913 pfc912 pfc911 pfc910 pfc99 pfc98 pfc97 pfc96 pfc95 pfc94 pfc93 pfc92 pfc91 pfc90 8 9 10 11 12 13 14 15 pfce915 pfce914 0 0 0 0 0 0 pfce97 pfce96 pfce95 pfce94 pfce93 pfce92 pfce91 pfce90 8 9 10 11 12 13 14 15 pfce9 after reset: 0000h r/w address: fffff712h, fffff713h uarta1 mode i 2 c02 mode pmc9n 1 1 operation mode pfce9n 1 1 pfc9n 0 1 remark n = 0, 1
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 684 of 1113 sep 22, 2011 19.2 features i 2 c00 to i 2 c02 have the following two modes. ? operation stopped mode ? i 2 c (inter ic) bus mode (multimasters supported) (1) operation stopped mode in this mode, serial transfers are not performed, thus enabling a reduction in power consumption. (2) i 2 c bus mode (multimaster support) this mode is used for 8-bit data transfers with several devices via two lines: a serial clock pin (scl0n) and a serial data bus pin (sda0n). this mode complies with the i 2 c bus format and the master device can generate ?start condition?, ?address?, ?transfer direction specif ication?, ?data?, and ?stop condition? data to the slave device via the serial data bus. the slave device automatically de tects the received statuses and data by hardware. this function can simplify the part of an ap plication program t hat controls the i 2 c bus. since scl0n and sda0n pins are used for n-ch open-drain outputs, i 2 c0n requires pull-up resistors for the serial clock line and the serial data bus line. remark n = 0 to 2
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 685 of 1113 sep 22, 2011 19.3 configuration the block diagram of the i 2 c0n is shown below. figure 19-4. block diagram of i 2 c0n internal bus iic status register n (iicsn) iic control register n (iiccn) so latch iicen dq cln1, cln0 trcn dfcn dfcn sda0n scl0n output control intiicn iic shift register n (iicn) iiccn.sttn, sptn iicsn.mstsn, excn, coin iicsn.mstsn, excn, coin lreln wreln spien wtimn acken sttn sptn mstsn aldn excn coin trcn ackdn stdn spdn internal bus cldn dadn smcn dfcn cln1 cln0 clxn iic clock select register n (iiccln) stcfn iicbsyn stcenn iicrsvn iic flag register n (iicfn) iic function expansion register n (iicxn) fxx iic division clock select register m (ocksm) fxx to fxx/5 ocksthm ocksenm ocksm1 ocksm0 clear slave address register n (svan) match signal set noise eliminator iic shift register n (iicn) data retention time correction circuit n-ch open-drain output acknowledge detector acknowledge generator start condition detector stop condition detector serial clock counter serial clock controller noise eliminator n-ch open-drain output start condition generator stop condition generator wakeup controller interrupt request signal generator serial clock wait controller bus status detector prescaler prescaler remark n = 0 to 2 m = 0, 1
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 686 of 1113 sep 22, 2011 a serial bus configuration example is shown below. figure 19-5. serial bus configuration example using i 2 c bus sda scl sda +v dd +v dd scl sda scl slave cpu3 address 3 sda scl slave ic address 4 sda scl slave ic address n master cpu1 slave cpu1 address 1 serial data bus serial clock master cpu2 slave cpu2 address 2
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 687 of 1113 sep 22, 2011 i 2 c0n includes the following hardware (n = 0 to 2). table 19-1. configuration of i 2 c0n item configuration registers iic shift register n (iicn) slave address register n (svan) control registers iic control register n (iiccn) iic status register n (iicsn) iic flag register n (iicf0n) iic clock select register n (iiccln) iic function expansion register n (iicxn) iic division clock select registers 0, 1 (ocks0, ocks1) (1) iic shift register n (iicn) the iicn register converts 8-bit serial data into 8-bit parallel data and vice versa, and can be used for both transmission and reception (n = 0 to 2). write and read operations to the iicn register are used to control the actual transmit and receive operations. this register can be read or written in 8-bit units. reset sets this register to 00h. (2) slave address register n (svan) the svan register sets local addresses w hen in slave mode (n = 0 to 2). this register can be read or written in 8-bit units. reset sets this register to 00h. (3) so latch the so latch is used to retain the output level of the sda0n pin (n = 0 to 2). (4) wakeup controller this circuit generates an interrupt request signal (i ntiicn) when the address received by this register matches the address value set to the svan register or when an extension code is received (n = 0 to 2). (5) prescaler this selects the sampling clock to be used. (6) serial clock counter this counter counts the serial cl ocks that are output and the serial clocks that are input during transmit/receive operations and is used to veri fy that 8-bit data was transmitted or received.
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 688 of 1113 sep 22, 2011 (7) interrupt request signal generator this circuit controls the generation of interrupt request signals (intiicn). an i 2 c interrupt is generated following either of two triggers. ? falling edge of eighth or ninth clock of t he serial clock (set by iiccn.wtimn bit) ? interrupt occurrence due to stop conditio n detection (set by iiccn.spien bit) remark n = 0 to 2 (8) serial clock controller in master mode, this circuit generates the clock output via the scl0n pin from the sampling clock (n = 0 to 2). (9) serial clock wait controller this circuit controls the wait timing. (10) ack generator, stop condition detector, start condition detector, and ack detector these circuits are used to generate and detect various statuses. (11) data hold time correction circuit this circuit generates the hold time for data co rresponding to the falling edge of the scl0n pin. (12) start condition generator a start condition is generated when the iiccn.sttn bit is set. however, in the communication reservation disabled st atus (iicfn.iicrsvn bit = 1), this request is ignored and the iicfn.stcfn bit is set to 1 if the bus is not released ( iicfn.iicbsyn bit = 1). (13) stop condition generator a stop condition is generated when the iiccn.sptn bit is set. (14) bus status detector whether the bus is released or not is ascertained by detecting a start cond ition and stop condition. however, the bus status cannot be detected immediately afte r operation, so set the bus status detector to the initial status by using the iicfn.stcenn bit.
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 689 of 1113 sep 22, 2011 19.4 registers i 2 c00 to i 2 c02 are controlled by t he following registers. ? iic control registers 0 to 2 (iicc0 to iicc2) ? iic status registers 0 to 2 (iics0 to iics2) ? iic flag registers 0 to 2 (iicf0 to iicf2) ? iic clock select registers 0 to 2 (iiccl0 to iiccl2) ? iic function expansion registers 0 to 2 (iicx0 to iicx2) ? iic division clock select r egisters 0, 1 (ocks0, ocks1) the following registers are also used. ? iic shift registers 0 to 2 (iic0 to iic2) ? slave address registers 0 to 2 (sva0 to sva2) remark for the alternate-function pin settings, see table 4-15 settings when pi ns are used for alternate functions . (1) iic control registers 0 to 2 (iicc0 to iicc2) the iiccn register enables/stops i 2 c0n operations, sets the wait timing, and sets other i 2 c operations (n = 0 to 2). these registers can be read or written in 8-bit or 1-bit units. however, set the spien, wtimn, and acken bits when the iicen bit is 0 or during the wait period. when setting the iicen bit from ?0? to ?1?, these bits can also be set at the same time. reset sets these registers to 00h.
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 690 of 1113 sep 22, 2011 (1/4) after reset: 00h r/w address: iicc0 fffffd82h, iicc1 fffffd92h, iicc2 fffffda2h <7> <6> <5> <4> <3> <2> <1> <0> iiccn iicen lreln wreln spien wtimn acken sttn sptn (n = 0 to 2) iicen specification of i 2 cn operation enable/disable 0 operation stopped. iicsn register reset note 1 . internal operation stopped. 1 operation enabled. be sure to set this bit to 1 when the scl0n and sda0n lines are high level. condition for clearing (iicen bit = 0) condition for setting (iicen bit = 1) ? cleared by instruction ? after reset ? set by instruction lreln note 2 exit from communications 0 normal operation 1 this exits from the current communication operation and sets standby mode. this setting is automatically cleared after being executed. its us es include cases in which a locally irrelevant extension code has been received. the scl0n and sda0n lines are set to high impedance. the sttn and sptn bits and the mstsn, excn, coin, trcn, ackdn, and stdn bits of the iicsn register are cleared. the standby mode following exit from communications remains in effect until the following communication entry conditions are met. ? after a stop condition is detected, restart is in master mode. ? an address match occurs or an extension code is received after the start condition. condition for clearing (lreln bit = 0) condition for setting (lreln bit = 1) ? automatically cleared after execution ? after reset ? set by instruction wreln note 2 wait state cancellation control 0 wait state not canceled 1 wait state canceled. this setting is autom atically cleared after wait state is canceled. condition for clearing (wreln bit = 0) condition for setting (wreln bit = 1) ? automatically cleared after execution ? after reset ? set by instruction notes 1. the iicsn register, iicfn.stcfn and iicfn.ii cbsyn bits, and iiccln.cldn and iiccln.dadn bits are reset. 2. this flag?s signal is invalid when the iicen bit = 0. caution if the i 2 cn operation is enabled (iicen bit = 1) when the scl0n line is high level and the sda0n line is low level, the start condition is detected immediately. to avoid this, after enabling the i 2 cn operation, immediately set the lreln bit to 1 with a bit manipulation instruction. remark the lreln and wreln bits are 0 when read after the data has been set.
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 691 of 1113 sep 22, 2011 (2/4) spien note enable/disable generation of interrupt request when stop condition is detected 0 disabled 1 enabled condition for clearing (spien bit = 0) condition for setting (spien bit = 1) ? cleared by instruction ? after reset ? set by instruction wtimn note control of wait state and interrupt request generation 0 interrupt request is generated at the eighth clock?s falling edge. master mode: after output of eight clocks, clock output is set to low level and the wait state is set. slave mode: after input of eight cl ocks, the clock is set to low level and the wait state is set for the master device. 1 interrupt request is generated at the ninth clock?s falling edge. master mode: after output of nine clocks, clock output is set to low level and the wait state is set. slave mode: after input of nine cl ocks, the clock is set to low level and the wait state is set for the master device. during address transfer, an interrupt occurs at the falling edge of the ninth clock regardless of this bit setting. this bit setting becomes valid when the address transfer is completed. in master mode, a wait state is inserted at the falling edge of the ninth clock during address transfer. for a slave device that has received a local address, a wait state is inserted at the falling edge of the ninth clock afte r ack is generated. when the slave device has received an extension code, however, a wait state is inserted at the falling edge of the eighth clock. condition for clearing (wtimn bit = 0) condition for setting (wtimn bit = 1) ? cleared by instruction ? after reset ? set by instruction acken note acknowledgment control 0 acknowledgment disabled. 1 acknowledgment enabled. during t he ninth clock period, the sda0n line is set to low level. the acken bit setting is invalid for address reception by the slave device. in this case, ack is generated when the addresses match. however, the acken bit setting is valid for reception of t he extension code. set the acken bit in the system that receives the extension code. condition for clearing (acken bit = 0) condition for setting (acken bit = 1) ? cleared by instruction ? after reset ? set by instruction note this flag?s signal is invalid when the iicen bit = 0. remark n = 0 to 2
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 692 of 1113 sep 22, 2011 (3/4) sttn start condition trigger 0 start condition is not generated. 1 when bus is released (in stop mode): a start condition is generated (for starting as mast er). the sda0n line is changed from high level to low level while the scln line is high level and then the start condition is generated. next, after the rated amount of time has elapsed, the scl0n line is changed to low level. during communication with a third party: if the communication reservation functi on is enabled (iicfn.iicrsvn bit = 0) ? this trigger functions as a start condition reserve flag. when set to 1, it releases the bus and then automatically generates a start condition. if the communication reservation function is disabled (iicrsvn = 1) ? the iicfn.stcfn bit is set to 1 and information se t (1) to the sttn bit is cleared. this trigger does not generate a start condition. in the wait state (when master device): a restart condition is generated after the wait state is released. cautions concerning set timing for master reception: cannot be set to 1 during tran sfer. can be set to 1 only when the acken bit has been set to 0 and the slave has been no tified of final reception. for master transmission: a start c ondition cannot be generated normally during the ack period. set to 1 during the wait period that follows output of the ninth clock. for slave: even when the communication reservati on function is disabled (iicrsvn bit = 1), the communication reservation status is entered. ? setting to 1 at the same time as the sptn bit is prohibited. ? when the sttn bit is set to 1, setting the sttn bit to 1 again is disabled until the setting is cleared to 0. condition for clearing (sttn bit = 0) condition for setting (sttn bit = 1) ? when the sttn bit is set to 1 in the communication reservation disabled status ? cleared by loss in arbitration ? cleared after start condition is generated by master device ? when the lreln bit = 1 (communication save) ? when the iicen bit = 0 (operation stop) ? after reset ? set by instruction remarks 1. the sttn bit is 0 if it is read immediately after data setting. 2. n = 0 to 2
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 693 of 1113 sep 22, 2011 (4/4) sptn stop condition trigger 0 stop condition is not generated. 1 stop condition is generated (terminati on of master device?s transfer). after the sda0n line goes to low level, either set the scl0n line to high level or wait until the scl0n pin goes to high level. next, after the rated am ount of time has elapsed, the sda0n line is changed from low level to high level and a stop condition is generated. cautions concerning set timing for master reception: cannot be set to 1 during transfer. can be set to 1 only when the acken bit has been set to 0 and during the wait period after the slave has been noti fied of final reception. for master transmission: a stop condition cannot be gener ated normally during the ack reception period. set to 1 during the wait period that follows output of the ninth clock. ? cannot be set to 1 at the same time as the sttn bit. ? the sptn bit can be set to 1 only when in master mode note . ? when the wtimn bit has been set to 0, if the sptn bit is se t to 1 during the wait period that follows output of eight clocks, note that a stop condition will be generated dur ing the high-level period of the ninth clock. the wtimn bit should be changed from 0 to 1 during t he wait period following output of eight clocks, and the sptn bit should be set to 1 during the wait period that follows output of the ninth clock. ? when the sptn bit is set to 1, setting the sptn bit to 1 again is disabled until the setting is cleared to 0. condition for clearing (sptn bit = 0) condition for setting (sptn bit = 1) ? cleared by loss in arbitration ? automatically cleared after stop condition is detected ? when the lreln bit = 1 (communication save) ? when the iicen bit = 0 (operation stop) ? after reset ? set by instruction note set the sptn bit to 1 only in master mode. however, when the iicrsvn bit is 0, the sptn bit must be set to 1 and a stop condition generated before the first stop condition is detected following the switch to the operation enabled status. for details, see 19.15 cautions . caution when the trcn bit = 1, the wreln bit is set to 1 during the ninth clock and the wait state is canceled, after which the trcn bit is cleared to 0 and the sda0n line is set to high impedance. remarks 1. the sptn bit is 0 if it is r ead immediately after data setting. 2. n = 0 to 2
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 694 of 1113 sep 22, 2011 (2) iic status registers 0 to 2 (iics0 to iics2) the iicsn register indi cates the status of i 2 c0n (n = 0 to 2). these registers are read-only, in 8-bit or 1-bit units. however, the iicsn register can only be read when the iiccn.sttn bit is 1 or during the wait period. reset sets these registers to 00h. caution accessing the iicsn register is prohibited in the following statuses. for details, see 3.4.9 (1) accessing specific on-chip peripheral i/o registers. ? when the cpu operates on the subclock and main clock oscillation is stopped ? when the cpu operates on the internal oscillator clock (1/3) after reset: 00h r address: iics0 fffffd86h, iics1 fffffd96h, iics2 fffffda6h <7> <6> <5> <4> <3> <2> <1> <0> iicsn mstsn aldn excn coin trcn ackdn stdn spdn (n = 0 to 2) mstsn master device status 0 slave device status or communication standby status 1 master device communication status condition for clearing (mstsn bit = 0) condition for setting (mstsn bit = 1) ? when a stop condition is detected ? when the aldn bit = 1 (arbitration loss) ? cleared by lreln bit = 1 (communication save) ? when the iicen bit changes from 1 to 0 (operation stop) ? after reset ? when a start condition is generated aldn arbitration loss detection 0 this status means either that there was no arbitr ation or that the arbitration result was a ?win?. 1 this status indicates the arbitration result was a ?loss?. the mstsn bit is cleared to 0. condition for clearing (aldn bit = 0) condition for setting (aldn bit = 1) ? automatically cleared after the iicsn register is read note ? when the iicen bit changes from 1 to 0 (operation stop) ? after reset ? when the arbitration result is a ?loss?. excn detection of extension code reception 0 extension code was not received. 1 extension code was received. condition for clearing (excn bit = 0) condition for setting (excn bit = 1) ? when a start condition is detected ? when a stop condition is detected ? cleared by lreln bit = 1 (communication save) ? when the iicen bit changes from 1 to 0 (operation stop) ? after reset ? when the higher four bits of the received address data are either ?0000? or ?1111? (set at the rising edge of the eighth clock). note this bit is also cleared when a bit manipulation instruction is executed for another bit in the iicsn register.
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 695 of 1113 sep 22, 2011 (2/3) coin matching address detection 0 addresses do not match. 1 addresses match. condition for clearing (coin bit = 0) condition for setting (coin bit = 1) ? when a start condition is detected ? when a stop condition is detected ? cleared by lreln bit = 1 (communication save) ? when the iicen bit changes from 1 to 0 (operation stop) ? after reset ? when the received address matches the local address (svan register) (set at the rising edge of the eighth clock). trcn transmit/receive status detection 0 receive status (other than transmit status). the sda0n line is set to high impedance. 1 transmit status. the value in the so latch is enab led for output to the sda0n line (valid starting at the falling edge of the first byte?s ninth clock). condition for clearing (trcn bit = 0) condition for setting (trcn bit = 1) ? when a stop condition is detected ? cleared by lreln bit = 1 (communication save) ? when the iicen bit changes from 1 to 0 (operation stop) ? cleared by iiccn.wreln bit = 1 note ? when the aldn bit changes from 0 to 1 (arbitration loss) ? after reset master ? when ?1? is output to the first byte?s lsb (transfer direction specification bit) slave ? when a start condition is detected when not used for communication master ? when a start condition is generated ? when ?0? is output to the first byte?s lsb (transfer direction specification bit) slave ? when ?1? is input by the first byte?s lsb (transfer direction specification bit) ackdn ack detection 0 ack was not detected. 1 ack was detected. condition for clearing (ackdn bit = 0) condition for setting (ackd bit = 1) ? when a stop condition is detected ? at the rising edge of the next byte?s first clock ? cleared by lreln bit = 1 (communication save) ? when the iicen bit changes from 1 to 0 (operation stop) ? after reset ? after the sda0n bit is set to low level at the rising edge of the scl0n pin?s ninth clock note the trcn bit is cleared to 0 and sda0n line becomes high impedance when the wreln bit is set to 1 and the wait state is canceled to 0 at the ninth clock by trcn bit = 1. remark n = 0 to 2
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 696 of 1113 sep 22, 2011 (3/3) stdn start condition detection 0 start condition was not detected. 1 start condition was detected. this indicates that the address transfer period is in effect condition for clearing (stdn bit = 0) condition for setting (stdn bit = 1) ? when a stop condition is detected ? at the rising edge of the next byte?s first clock following address transfer ? cleared by lreln bit = 1 (communication save) ? when the iicen bit changes from 1 to 0 (operation stop) ? after reset ? when a start condition is detected spdn stop condition detection 0 stop condition was not detected. 1 stop condition was detected. the master device ?s communication is terminated and the bus is released. condition for clearing (spdn bit = 0) condition for setting (spdn bit = 1) ? at the rising edge of the address transfer byte?s first clock following setting of th is bit and detection of a start condition ? when the iicen bit changes from 1 to 0 (operation stop) ? after reset ? when a stop condition is detected remark n = 0 to 2
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 697 of 1113 sep 22, 2011 (3) iic flag registers 0 to 2 (iicf0 to iicf2) the iicfn register sets the i 2 c0n operation mode and indicates the i 2 c bus status. these registers can be read or written in 8-bit or 1-bit units. however, the stcfn and iicbsyn bits are read-only. iicrsvn enables/disables the communication reservation function (see 19.14 communication reservation ). the initial value of the iicbsyn bit is set by using the stcenn bit (see 19.15 cautions ). the iicrsvn and stcenn bits can be written only when operation of i 2 c0n is disabled (iiccn.iicen bit = 0). after operation is enabled, iicfn can be read (n = 0 to 2). reset sets these registers to 00h.
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 698 of 1113 sep 22, 2011 after reset: 00h r/w note address: iicf0 fffffd8ah, iicf1 fffffd9ah, iicf2 fffffdaah <7> <6> 5 4 3 2 <1> <0> iicfn stcfn iicbsyn 0 0 0 0 stcenn iicrsvn (n = 0 to 2) stcfn sttn bit clear 0 start condition issued 1 start condition cannot be is sued, sttn bit cleared condition for clearing (stcfn bit = 0) condition for setting (stcfn bit = 1) ? cleared by iiccn.sttn bit = 1 ? when the iiccn.iicen bit = 0 ? after reset ? when start condition is not issued and sttn flag is cleared to 0 during communication reservation is disabled (iicrsvn bit = 1). iicbsyn i 2 c0n bus status 0 bus released status (default communication status when stcenn bit = 1) 1 bus communication status (default comm unication status when stcenn bit = 0) condition for clearing (iicbsyn bit = 0) condition for setting (iicbsyn bit = 1) ? when stop condition is detected ? when the iicen bit = 0 ? after reset ? when start condition is detected ? by setting the iicen bit when the stcenn bit = 0 stcenn initial start enable trigger 0 start conditions cannot be generated until a st op condition is detected following operation enable (iicen bit = 1). 1 start conditions can be generated even if a stop condition is not detected following operation enable (iicen bit = 1). condition for clearing (stcenn bit = 0) condition for setting (stcenn bit = 1) ? when start condition is detected ? after reset ? setting by instruction iicrsvn communication reservation function disable bit 0 communication reservation enabled 1 communication reservation disabled condition for clearing (iicrsvn bit = 0) condition for setting (iicrsvn bit = 1) ? clearing by instruction ? after reset ? setting by instruction note bits 6 and 7 are read-only bits. cautions 1. write the stcenn bit only when operation is stopped (iicen bit = 0). 2. when the stcenn bit = 1, the bus relea sed status (iicbsyn bit = 0) is recognized regardless of the actual bus status immediately after the i 2 cn bus operation is enabled. therefore, to issue the first start condition (sttn bit = 1), it is necessary to confirm that th e bus has been released, so as to not disturb other communications. 3. write the iicrsvn bit only when operation is stopped (iicen bit = 0).
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 699 of 1113 sep 22, 2011 (4) iic clock select registers 0 to 2 (iiccl0 to iiccl2) the iiccln register sets the transfer clock for i 2 c0n. these registers can be read or written in 8-bit or 1- bit units. however, the cldn and dadn bits are read-only. set the iiccln register when the iiccn.iicen bit = 0. the smcn, cln1, and cln0 bits are set by the comb ination of the iicxn.clxn bit and the ocksthm, ocksm1, and ocksm0 bits of the ocksm register (see 19.4 (6) i 2 c0n transfer clock setting method ) (n = 0 to 2, m = 0, 1). reset sets these registers to 00h. after reset: 00h r/w note address: iiccl0 fffffd84h, iiccl1 fffffd94h, iiccl2 fffffda4h 7 6 <5> <4> 3 2 1 0 iiccln 0 0 cldn dadn smcn dfcn cln1 cln0 (n = 0 to 2) cldn detection of scl0n pin level (valid only when iiccn.iicen bit = 1) 0 the scl0n pin was detected at low level. 1 the scl0n pin was detected at high level. condition for clearing (cldn bit = 0) condition for setting (cldn bit = 1) ? when the scl0n pin is at low level ? when the iicen bit = 0 (operation stop) ? after reset ? when the scl0n pin is at high level dadn detection of sda0n pin level (valid only when iicen bit = 1) 0 the sda0n pin was detected at low level. 1 the sda0n pin was detected at high level. condition for clearing (dadn bit = 0) condition for setting (dad0n bit = 1) ? when the sda0n pin is at low level ? when the iicen bit = 0 (operation stop) ? after reset ? when the sda0n pin is at high level smcn operation mode switching 0 operation in standard mode 1 operation in high-speed mode dfcn digital filter operation control 0 digital filter off 1 digital filter on the digital filter can be used only in high-speed mode. in high-speed mode, the transfer clock does not vary regardless of the dfcn bit setting (on/off). the digital filter is used to e liminate noise in high-speed mode. note bits 4 and 5 are read-only bits. caution be sure to clear bits 7 and 6 to ?0?. remark when the iiccn.iicen bit = 0, 0 is read when reading the cldn and dadn bits.
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 700 of 1113 sep 22, 2011 (5) iic function expansion regist ers 0 to 2 (iicx0 to iicx2) the iicxn register sets i 2 c0n function expansion (valid only in the high-speed mode). these registers can be read or wri tten in 8-bit or 1-bit units. setting of the clxn bit is performed in combination with the smcn, cln1, and cln0 bits of the iiccln register and the ocksthm, ocksm1, and ocksm 0 bits of the ocksm register (see 19.4 (6) i 2 c0n transfer clock setting method ) (m = 0, 1). set the iicxn register wh en the iiccn.iicen bit = 0. reset sets these registers to 00h. iicxn (n = 0 to 2) after reset: 00h r/w address: iicx0 fffffd85h, iicx1 fffffd95h, iicx2 fffffda5h 0 0 0 0 0 0 0 clxn < > (6) i 2 c0n transfer clock setting method the i 2 c0n transfer clock frequency (f scl ) is calculated using the following expression (n = 0 to 2). f scl = 1/(m t + t r + t f ) m = 12, 18, 24, 36, 44, 48, 54, 60, 66, 72, 86, 88, 96, 132, 172, 176, 198, 220, 258, 344 (see table 19-2 clock settings ). t: 1/f xx t r : scl0n pin rise time t f : scl0n pin fall time for example, the i 2 c0n transfer clock frequency (f scl ) when f xx = 19.2 mhz, m = 198, t r = 200 ns, and t f = 50 ns is calculated using following expression. f scl = 1/(198 52 ns + 200 ns + 50 ns) ? 94.7 khz m t + t r + t f m/2 t t f t r m/2 t scl0n scl0n inversion scl0n inversion scl0n inversion the clock to be selected can be set by the combinat ion of the smcn, cln1, and cln0 bits of the iiccln register, the clxn bit of the iic xn register, and the ocksthm, ocksm1, and ocksm0 bits of the ocksm register (n = 0 to 2, m = 0, 1).
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 701 of 1113 sep 22, 2011 table 19-2. clock settings (1/2) iicx0 iiccl0 bit 0 bit 3 bit 1 bit 0 clx0 smc0 cl01 cl00 selection clock transfer clock settable main clock frequency (f xx ) range operating mode f xx (when ocks0 = 18h set) f xx /44 2.50 mhz f xx 4.19 mhz f xx /2 (when ocks0 = 10h set) f xx /88 4.00 mhz f xx 8.38 mhz f xx /3 (when ocks0 = 11h set) f xx /132 6.00 mhz f xx 12.57 mhz f xx /4 (when ocks0 = 12h set) f xx /176 8.00 mhz f xx 16.76 mhz 0 0 0 0 f xx /5 (when ocks0 = 13h set) f xx /220 10.00 mhz f xx 20.00 mhz f xx (when ocks0 = 18h set) f xx /86 4.19 mhz f xx 8.38 mhz f xx /2 (when ocks0 = 10h set) f xx /172 8.38 mhz f xx 16.76 mhz f xx /3 (when ocks0 = 11h set) f xx /258 12.57 mhz f xx 20.00 mhz 0 0 0 1 f xx /4 (when ocks0 = 12h set) f xx /344 16.76 mhz f xx 20.00 mhz 0 0 1 0 f xx note f xx /86 4.19 mhz f xx 8.38 mhz f xx (when ocks0 = 18h set) f xx /66 f xx = 6.40 mhz f xx /2 (when ocks0 = 10h set) f xx /132 f xx = 12.80 mhz 0 0 1 1 f xx /3 (when ocks0 = 11h set) f xx /198 f xx = 19.20 mhz standard mode (smc0 bit = 0) f xx (when ocks0 = 18h set) f xx /24 4.19 mhz f xx 8.38 mhz f xx /2 (when ocks0 = 10h set) f xx /48 8.00 mhz f xx 16.76 mhz f xx /3 (when ocks0 = 11h set) f xx /72 12.00 mhz f xx 20.00 mhz 0 1 0 f xx /4 (when ocks0 = 12h set) f xx /96 16.00 mhz f xx 20.00 mhz 0 1 1 0 f xx note f xx /24 4.00 mhz f xx 8.38 mhz f xx (when ocks0 = 18h set) f xx /18 f xx = 6.40 mhz f xx /2 (when ocks0 = 10h set) f xx /36 f xx = 12.80 mhz 0 1 1 1 f xx /3 (when ocks0 = 11h set) f xx /54 f xx = 19.20 mhz f xx (when ocks0 = 18h set) f xx /12 4.00 mhz f xx 4.19 mhz f xx /2 (when ocks0 = 10h set) f xx /24 8.00 mhz f xx 8.38 mhz f xx /3 (when ocks0 = 11h set) f xx /36 12.00 mhz f xx 12.57 mhz f xx /4 (when ocks0 = 12h set) f xx /48 16.00 mhz f xx 16.67 mhz 1 1 0 f xx /5 (when ocks0 = 13h set) f xx /60 f xx = 20.00 mhz 1 1 1 0 f xx note f xx /12 4.00 mhz f xx 4.19 mhz high-speed mode (smc0 bit = 1) other than above setting prohibited ? ? ? note since the selection clock is f xx regardless of the value set to the ocks0 register, clear the ocks0 register to 00h (i 2 c division clock stopped status). remark : don?t care
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 702 of 1113 sep 22, 2011 table 19-2. clock settings (2/2) iicxm iicclm bit 0 bit 3 bit 1 bit 0 clxm smcm clm1 clm0 selection clock transfer clock settable main clock frequency (f xx ) range operating mode f xx (when ocks1 = 18h set) f xx /44 2.50 mhz f xx 4.19 mhz f xx /2 (when ocks1 = 10h set) f xx /88 4.00 mhz f xx 8.38 mhz f xx /3 (when ocks1 = 11h set) f xx /132 6.00 mhz f xx 12.57 mhz f xx /4 (when ocks1 = 12h set) f xx /176 8.00 mhz f xx 16.76 mhz 0 0 0 0 f xx /5 (when ocks1 = 13h set) f xx /220 10.00 mhz f xx 20.00 mhz f xx (when ocks1 = 18h set) f xx /86 4.19 mhz f xx 8.38 mhz f xx /2 (when ocks1 = 10h set) f xx /172 8.38 mhz f xx 16.76 mhz f xx /3 (when ocks1 = 11h set) f xx /258 12.57 mhz f xx 20.00 mhz 0 0 0 1 f xx /4 (when ocks1 = 12h set) f xx /344 16.76 mhz f xx 20.00 mhz 0 0 1 0 f xx note f xx /86 4.19 mhz f xx 8.38 mhz f xx (when ocks1 = 18h set) f xx /66 f xx = 6.40 mhz f xx /2 (when ocks1 = 10h set) f xx /132 f xx = 12.80 mhz 0 0 1 1 f xx /3 (when ocks1 = 11h set) f xx /198 f xx = 19.20 mhz standard mode (smcm bit = 0) f xx (when ocks1 = 18h set) f xx /24 4.19 mhz f xx 8.38 mhz f xx /2 (when ocks1 = 10h set) f xx /48 8.00 mhz f xx 16.76 mhz f xx /3 (when ocks1 = 11h set) f xx /72 12.00 mhz f xx 20.00 mhz 0 1 0 f xx /4 (when ocks1 = 12h set) f xx /96 16.00 mhz f xx 20.00 mhz 0 1 1 0 f xx note f xx /24 4.00 mhz f xx 8.38 mhz f xx (when ocks1 = 18h set) f xx /18 f xx = 6.40 mhz f xx /2 (when ocks1 = 10h set) f xx /36 f xx = 12.80 mhz 0 1 1 1 f xx /3 (when ocks1 = 11h set) f xx /54 f xx = 19.20 mhz f xx (when ocks1 = 18h set) f xx /12 4.00 mhz f xx 4.19 mhz f xx /2 (when ocks1 = 10h set) f xx /24 8.00 mhz f xx 8.38 mhz f xx /3 (when ocks1 = 11h set) f xx /36 12.00 mhz f xx 12.57 mhz f xx /4 (when ocks1 = 12h set) f xx /48 16.00 mhz f xx 16.67 mhz 1 1 0 f xx /5 (when ocks1 = 13h set) f xx /60 f xx = 20.00 mhz 1 1 1 0 f xx note f xx /12 4.00 mhz f xx 4.19 mhz high-speed mode (smcm bit = 1) other than above setting prohibited ? ? ? note since the selection clock is f xx regardless of the value set to the ocks1 register, clear the ocks1 register to 00h (i 2 c division clock stopped status). remarks 1. m = 1, 2 2. : don?t care
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 703 of 1113 sep 22, 2011 (7) iic division clock select re gisters 0, 1 (ocks0, ocks1) the ocksm register controls the i 2 c0n division clock (n = 0 to 2, m = 0, 1). these registers control the i 2 c00 division clock via the ocks0 register and the i 2 c01 and i 2 c02 division clocks via the ocks1 register. these registers can be read or written in 8-bit units. reset sets these registers to 00h. 0 ocksm (m = 0, 1) 00 ocksenm ocksthm 0 ocksm1 ocksm0 after reset: 00h r/w address: ocks0 fffff340h, ocks1 fffff344h disable i 2 c division clock operation enable i 2 c division clock operation ocksenm 0 1 operation setting of i 2 c division clock ocksm1 0 0 1 1 0 other than above ocksm0 0 1 0 1 0 selection of i 2 c division clock f xx /2 f xx /3 f xx /4 f xx /5 f xx setting prohibited ocksthm 0 0 0 0 1 (8) iic shift registers 0 to 2 (iic0 to iic2) the iicn register is used for serial transmission/re ception (shift operations) synchronized with the serial clock. these registers can be read or written in 8-bit units, but data should not be written to the iicn register during a data transfer. access (read/write) the iicn register only during the wait period. accessi ng this register in communication states other than the wait period is prohibited. however, for the master device, the iicn register can be written once only after the transmission trigge r bit (iiccn.sttn bit) has been set to 1. a wait state is released by writing the iicn register duri ng the wait period, and data tr ansfer is started (n = 0 to 2). reset sets these registers to 00h. after reset: 00h r/w address: iic0 fffffd80h, iic1 fffffd90h, iic2 fffffda0h 7 6 5 4 3 2 1 0 iicn (n = 0 to 2)
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 704 of 1113 sep 22, 2011 (9) slave address registers 0 to 2 (sva0 to sva2) the svan register holds the i 2 c bus?s slave address. these registers can be read or written in 8-bit units, but bit 0 should be fixed to 0. however, rewriting this register is prohibited when the iic sn.stdn bit = 1 (start condition detection). reset sets these registers to 00h. after reset: 00h r/w address: sva0 ffff fd83h, sva1 fffffd93h , sva2 fffffda3h 7 6 5 4 3 2 1 0 svan 0 (n = 0 to 2)
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 705 of 1113 sep 22, 2011 19.5 i 2 c bus mode functions 19.5.1 pin configuration the serial clock pin (scl0n) and serial data bus pin (sda0n) are configured as follows (n = 0 to 2). scl0n ............. this pi n is used for serial clock input and output. this pin is an n-ch open-drain output for both ma ster and slave devices. input is schmitt input. sda0n ............ this pin is used for serial data input and output. this pin is an n-ch open-drain output for both ma ster and slave devices. input is schmitt input. since outputs from the serial clock line and the serial data bus line are n-ch open-drain outputs, an external pull-up resistor is required. figure 19-6. pin configuration diagram v dd scl0n sda0n scl0n sda0n v dd clock output master device (clock input) data output data input (clock output) clock input data output data input slave device
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 706 of 1113 sep 22, 2011 19.6 i 2 c bus definitions and control methods the following section describes the i 2 c bus?s serial data communication format and the signals used by the i 2 c bus. the transfer timing for the ?start condition?, ?addr ess?, ?transfer direction specification?, ?data?, and ?stop condition? generated on the i 2 c bus?s serial data bus is shown below. figure 19-7. i 2 c bus serial data transfer timing 1 to 7 8 9 1 to 8 9 1 to 8 9 scl0n sda0n r/w start condition address ack data data stop condition ack ack the master device generates the start c ondition, slave address, and stop condition. ack can be generated by either the mast er or slave device (normally, it is generated by the device that receives 8-bit data). the serial clock (scl0n) is continuously output by the master dev ice. however, in the slave device, the scl0n pin?s low-level period can be extended and a wait state can be inserted (n = 0 to 2). 19.6.1 start condition a start condition is met when the scl0n pin is high level and the sda0n pin changes from high level to low level. the start condition for the scl0n and sda0n pins is a signal t hat the master device outputs to the slave device when starting a serial transfer. the slave device can defect the start condition (n = 0 to 2). figure 19-8. start condition h scl0n sda0n a start condition is output when the iiccn.sttn bit is set (1) after a stop condition has been detected (iicsn.spdn bit = 1). when a start condition is detec ted, the iicsn.stdn bit is set (1) (n = 0 to 2). caution when the iiccn.iicen bit of the v850es/jg3-l is set to 1 while communicat ions with other devices are in progress, the start condi tion may be detected dependi ng on the status of the communication line. be sure to set the iiccn.iic en bit to 1 when the scl0n and sda0n lines are high level.
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 707 of 1113 sep 22, 2011 19.6.2 addresses the 7 bits of data that follow the start condition are defined as an address. an address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the master device via the bus lines. therefore, each slav e device connected via the bus lines must have a unique address. the slave devices include hardware that detects the st art condition and checks whether or not the 7-bit address data matches the data values stored in the svan register . if the address data matches the values of the svan register, the slave device is selected and communicates with the master device until the master device generates a start condition or stop condition (n = 0 to 2). figure 19-9. address address scl0n 1 sda0n intiicn note 23456789 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w note the interrupt request signal (intiicn) is generat ed if a local address or extension code is received during slave device operation. remark n = 0 to 2 the slave address and the eighth bit, which specif ies the transfer direction as described in 19.6.3 transfer direction specification below, are written together to iic shift r egister n (iicn) and then output. received addresses are written to the iicn register (n = 0 to 2). the slave address is assigned to the higher 7 bits of the iicn register.
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 708 of 1113 sep 22, 2011 19.6.3 transfer direction specification in addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction. when this transfer direction specification bit has a va lue of 0, it indicates that the master device is transmitting data to a slave device. when the transfer direction specification bit has a valu e of 1, it indicates that th e master device is receiving data from a slave device. figure 19-10. transfer direction specification scl0n 1 sda0n intiicn 23456789 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w transfer direction specification note note the intiicn signal is generated if a local address or extension code is received during slave device operation. remark n = 0 to 2
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 709 of 1113 sep 22, 2011 19.6.4 ack ack is used to confirm the serial data stat us of the transmitting and receiving devices. the receiving device returns ack for every 8 bits of data it receives. the transmitting device normally receives ack after transmi tting 8 bits of data. when ack is returned from the receiving device, the reception is judged as normal and proc essing continues. the detection of ack is confirmed with the iicsn.ackdn bit. when the master device is the receiv ing device, after receiving the final data, it does not return ack and generates the stop condition. when the slave device is the receiving device and does not return ack, the master device generates either a stop condition or a restart condition, and then stops the current transmission. failure to return ack may be caused by the following factors. (a) reception was not performed normally. (b) the final data was received. (c) the receiving device (slave) does not exist for the specified address. when the receiving device sets the sda0n line to low level during the ninth clock, ack is generated (normal reception). when the iiccn.acken bit is set to 1, automatic ack ge neration is enabled. transmission of the eighth bit following the 7 address data bits causes the iicsn.trcn bi t to be set. normally, set the acken bit to 1 for reception (trcn bit = 0). when the slave device is receiving (when trcn bit = 0), if the slave device cannot rece ive data or does not need to receive any more data, clear the acken bit to 0 to i ndicate to the master that no more data can be received. similarly, when the master device is receiving (when trcn bit = 0) and the subsequent data is not needed, clear the acken bit to 0 to prevent ack from being generated. this notifies the slave device (transmitting device) of the end of the data transmission (transmission stopped). figure 19-11. ack scl0n 1 sda0n 23456789 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w ack remark n = 0 to 2 when the local address is received, ac k is automatically generated regardle ss of the value of the acken bit. no ack is generated if the received address is not a local address (nack). when receiving the extension code, set the ac ken bit to 1 in advance to generate ack. the ack generation method during data reception is based on the wait timing setting, as described by the following. ? when 8-clock wait is selected (iiccn.wtimn bit = 0): ack is generated at the falling edge of the scl0n pin?s ei ghth clock if the acken bit is set to 1 before the wait state cancellation. ? when 9-clock wait is selected (iiccn.wtimn bit = 1): ack is generated if the acken bit is set to 1 in advance. remark n = 0 to 2
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 710 of 1113 sep 22, 2011 19.6.5 stop condition when the scl0n pin is high level, changing the sda0n pin from low level to high level generates a stop condition (n = 0 to 2). a stop condition is generated when the master device outp uts to the slave device when serial transfer has been completed. when used as the slave device, the start condition can be detected. figure 19-12. stop condition h scl0n sda0n remark n = 0 to 2 a stop condition is generated when the iiccn.sptn bit is set to 1. when the stop condition is detected, the iicsn.spdn bit is set to 1 and the interrupt request signal (i ntiicn) is generated when the iiccn.spien bit is set to 1 (n = 0 to 2).
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 711 of 1113 sep 22, 2011 19.6.6 wait state a wait state is used to notify the comm unication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). setting the scl0n pin to low level notifies the communication partner of the wait state. when the wait state has been canceled for both the master and slave devices, the next data transfer can begin (n = 0 to 2). figure 19-13. wait state (1/2) (a) when master device has a nine-clock wait and slave device has an eight-clock wait (master: transmission, slave: r eception, and iiccn.acken bit = 1) scl0n 6 sda0n 78 9 123 scl0n iicn 6 h 78 123 d2 d1 d0 ack d7 d6 d5 9 iicn scl0n acken master master returns to high impedance but slave is in wait state (low level). wait after output of ninth clock. iicn data write (cancel wait state) slave wait after output of eighth clock. ffh is written to iicn register or iiccn.wreln bit is set to 1. transfer lines wait state from slave wait state from master remark n = 0 to 2
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 712 of 1113 sep 22, 2011 figure 19-13. wait state (2/2) (b) when master and slave devices both have a nine-clock wait (master: transmission, slave: reception, and acken bit = 1) scl0n 6 sda0n 789 123 scl0n iicn 6 h 78 1 23 d2 d1 d0 ack d7 d6 d5 9 iicn scl0n acken master master and slave both wait after output of ninth clock. iicn data write (cancel wait state) slave ffh is written to iicn register or wreln bit is set to 1. generate according to previously set acken bit value transfer lines wait state from master/ slave wait state from slave remark n = 0 to 2 a wait state may be automatically ge nerated depending on the setting of the iiccn.wtimn bit (n = 0 to 2). normally, when the iiccn.wreln bit is set to 1 or when ffh is written to the iicn register on the receiving side, the wait state is canceled and the trans mitting side writes data to the iicn r egister to cancel the wait state. the master device can also cancel the wait state via either of the following methods. ? by setting the iiccn.sttn bit to 1 ? by setting the iiccn.sptn bit to 1
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 713 of 1113 sep 22, 2011 19.6.7 wait state cancellation method in the case of i 2 c0n, a wait state can be canceled normally in the following ways (n = 0 to 2). ? by writing data to the iicn register ? by setting the iiccn.wreln bit to 1 (wait state cancellation) ? by setting the iiccn.sttn bit to 1 (start condition generation) ? by setting the iiccn.sptn bit to 1 (stop condition generation) if any of these wait state canc ellation actions is performed, i 2 c0n will cancel the wa it state and restart communication. when canceling the wait state and sending data (inc luding addresses), write data to the iicn register. to receive data after canceling the wait state, or to complete data transmission, set the wreln bit to 1. to generate a restart condition after cancelin g the wait state, set the sttn bit to 1. to generate a stop condition after canceling the wait state, set the sptn bit to 1. cancel each wait state only once. for example, if data is written to the iicn register followin g wait state cancellation by setting the wreln bit to 1, a conflict between the sda0n line change timing and the iicn regi ster write timing may result in the data output to the sda0n line being incorrect. even in other operations, if communication is stopped halfway, clearing the iiccn.iicen bit to 0 will stop communication, enabling the wait state to be cancelled. if the i 2 c bus deadlocks due to noise, etc., setting the iiccn.lre ln bit to 1 causes the communication to stop, enabling the wait state to be cancelled.
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 714 of 1113 sep 22, 2011 19.7 i 2 c interrupt request signals (intiicn) the following shows the value of the iicsn register at the intiicn interrupt r equest signal generation timing and at the intiicn signal timing (n = 0 to 2). 19.7.1 master device operation (1) start ~ address ~ data ~ data ~ stop (normal transmission/reception) <1> when iiccn.wtimn bit = 0 iiccn.sptn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iicsn register = 1000x110b s 2: iicsn register = 1000x000b s 3: iicsn register = 1000x000b (wtimn bit = 1) s 4: iicsn register = 1000xx00b 5: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2 <2> when wtimn bit = 1 sptn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iicsn register = 1000x110b s 2: iicsn register = 1000x100b s 3: iicsn register = 1000xx00b 4: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 715 of 1113 sep 22, 2011 (2) start ~ address ~ data ~ start ~ address ~ data ~ stop (restart) <1> when wtimn bit = 0 sttn bit = 1 sptn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 s 5 s 6 7 s 1: iicsn register = 1000x110b s 2: iicsn register = 1000x000b (wtimn bit = 1) s 3: iicsn register = 1000xx00b (wtimn bit = 0) s 4: iicsn register = 1000x110b (wtimn bit = 0) s 5: iicsn register = 1000x000b (wtimn bit = 1) s 6: iicsn register = 1000xx00b 7: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2 <2> when wtimn bit = 1 sttn bit = 1 sptn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iicsn register = 1000x110b s 2: iicsn register = 1000xx00b s 3: iicsn register = 1000x110b s 4: iicsn register = 1000xx00b 5: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 716 of 1113 sep 22, 2011 (3) start ~ code ~ data ~ data ~ stop (extension code transmission) <1> when wtimn bit = 0 sptn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iicsn register = 1010x110b s 2: iicsn register = 1010x000b s 3: iicsn register = 1010x000b (wtimn bit = 1) s 4: iicsn register = 1010xx00b 5: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2 <2> when wtimn bit = 1 sptn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iicsn register = 1010x110b s 2: iicsn register = 1010x100b s 3: iicsn register = 1010xx00b 4: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 717 of 1113 sep 22, 2011 19.7.2 slave device operation (when recei ving slave address data (address match)) (1) start ~ address ~ data ~ data ~ stop <1> when iiccn.wtimn bit = 0 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iicsn register = 0001x110b s 2: iicsn register = 0001x000b s 3: iicsn register = 0001x000b 4: iicsn register = 00000001b remarks 1. s : always generated : generated only when iiccn.spien bit = 1 x: don?t care 2. n = 0 to 2 <2> when wtimn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iicsn register = 0001x110b s 2: iicsn register = 0001x100b s 3: iicsn register = 0001xx00b 4: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 718 of 1113 sep 22, 2011 (2) start ~ address ~ data ~ start ~ address ~ data ~ stop <1> when wtimn bit = 0 (afte r restart, address match) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iicsn register = 0001x110b s 2: iicsn register = 0001x000b s 3: iicsn register = 0001x110b s 4: iicsn register = 0001x000b 5: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2 <2> when wtimn bit = 1 (afte r restart, address match) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iicsn register = 0001x110b s 2: iicsn register = 0001xx00b s 3: iicsn register = 0001x110b s 4: iicsn register = 0001xx00b 5: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 719 of 1113 sep 22, 2011 (3) start ~ address ~ data ~ start ~ code ~ data ~ stop <1> when wtimn bit = 0 (after rest art, extension code reception) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iicsn register = 0001x110b s 2: iicsn register = 0001x000b s 3: iicsn register = 0010x010b s 4: iicsn register = 0010x000b 5: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2 <2> when wtimn bit = 1 (after rest art, extension code reception) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 s 5 6 s 1: iicsn register = 0001x110b s 2: iicsn register = 0001xx00b s 3: iicsn register = 0010x010b s 4: iicsn register = 0010x110b s 5: iicsn register = 0010xx00b 6: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 720 of 1113 sep 22, 2011 (4) start ~ address ~ data ~ start ~ address ~ data ~ stop <1> when wtimn bit = 0 (after restart, a ddress mismatch (= not extension code)) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iicsn register = 0001x110b s 2: iicsn register = 0001x000b s 3: iicsn register = 00000x10b 4: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2 <2> when wtimn bit = 1 (after restart, a ddress mismatch (= not extension code)) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iicsn register = 0001x110b s 2: iicsn register = 0001xx00b s 3: iicsn register = 00000x10b 4: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 721 of 1113 sep 22, 2011 19.7.3 slave device operation (w hen receiving extension code) (1) start ~ code ~ data ~ data ~ stop <1> when iiccn.wtimn bit = 0 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iicsn register = 0010x010b s 2: iicsn register = 0010x000b s 3: iicsn register = 0010x000b 4: iicsn register = 00000001b remarks 1. s : always generated : generated only when iiccn.spien bit = 1 x: don?t care 2. n = 0 to 2 <2> when wtimn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iicsn register = 0010x010b s 2: iicsn register = 0010x110b s 3: iicsn register = 0010x100b s 4: iicsn register = 0010xx00b 5: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 722 of 1113 sep 22, 2011 (2) start ~ code ~ data ~ st art ~ address ~ data ~ stop <1> when wtimn bit = 0 (afte r restart, address match) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iicsn register = 0010x010b s 2: iicsn register = 0010x000b s 3: iicsn register = 0001x110b s 4: iicsn register = 0001x000b 5: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2 <2> when wtimn bit = 1 (afte r restart, address match) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 s 5 6 s 1: iicsn register = 0010x010b s 2: iicsn register = 0010x110b s 3: iicsn register = 0010xx00b s 4: iicsn register = 0001x110b s 5: iicsn register = 0001xx00b 6: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 723 of 1113 sep 22, 2011 (3) start ~ code ~ data ~ st art ~ code ~ data ~ stop <1> when wtimn bit = 0 (after rest art, extension code reception) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iicsn register = 0010x010b s 2: iicsn register = 0010x000b s 3: iicsn register = 0010x010b s 4: iicsn register = 0010x000b 5: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2 <2> when wtimn bit = 1 (after rest art, extension code reception) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 s 5 s 6 7 s 1: iicsn register = 0010x010b s 2: iicsn register = 0010x110b s 3: iicsn register = 0010xx00b s 4: iicsn register = 0010x010b s 5: iicsn register = 0010x110b s 6: iicsn register = 0010xx00b 7: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 724 of 1113 sep 22, 2011 (4) start ~ code ~ data ~ st art ~ address ~ data ~ stop <1> when wtimn bit = 0 (after restart, a ddress mismatch (= not extension code)) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iicsn register = 0010x010b s 2: iicsn register = 0010x000b s 3: iicsn register = 00000x10b 4: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2 <2> when wtimn bit = 1 (after restart, a ddress mismatch (= not extension code)) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iicsn register = 0010x010b s 2: iicsn register = 0010x110b s 3: iicsn register = 0010xx00b s 4: iicsn register = 00000x10b 5: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 725 of 1113 sep 22, 2011 19.7.4 operation without communication (1) start ~ code ~ data ~ data ~ stop st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp 1 1: iicsn register = 00000001b remarks 1. : generated only when spien bit = 1 2. n = 0 to 2 19.7.5 operation when arbitrat ion loss occurs (operation as slave after arbitration loss) (1) when arbitration loss occurs during transmission of slave address data <1> when iiccn.wtimn bit = 0 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iicsn register = 0101x110b (example: when iicsn .aldn bit is read during interrupt servicing) s 2: iicsn register = 0001x000b s 3: iicsn register = 0001x000b 4: iicsn register = 00000001b remarks 1. s : always generated : generated only when iiccn.spien bit = 1 x: don?t care 2. n = 0 to 2 <2> when wtimn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iicsn register = 0101x110b (example: when aldn bit is read during interrupt servicing) s 2: iicsn register = 0001x100b s 3: iicsn register = 0001xx00b 4: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 726 of 1113 sep 22, 2011 (2) when arbitration loss occurs dur ing transmission of extension code <1> when wtimn bit = 0 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iicsn register = 0110x010b (example: when aldn bit is read during interrupt servicing) s 2: iicsn register = 0010x000b s 3: iicsn register = 0010x000b 4: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2 <2> when wtimn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iicsn register = 0110x010b (example: when aldn bit is read during interrupt servicing) s 2: iicsn register = 0010x110b s 3: iicsn register = 0010x100b s 4: iicsn register = 0010xx00b 5: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 727 of 1113 sep 22, 2011 19.7.6 operation when arbitrat ion loss occurs (no communicat ion after arbitration loss) (1) when arbitration loss occurs durin g transmission of slave address data st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 2 s 1: iicsn register = 01000110b (example: when iicsn .aldn bit is read during interrupt servicing) 2: iicsn register = 00000001b remarks 1. s : always generated : generated only when iiccn.spien bit = 1 2. n = 0 to 2 (2) when arbitration loss occurs during transmission of extension code st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 2 s 1: iicsn register = 0110x010b (example: when aldn bit is read during interrupt servicing) iiccn.lreln bit is set to 1 by software 2: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 728 of 1113 sep 22, 2011 (3) when arbitration loss o ccurs during data transfer <1> when iiccn.wtimn bit = 0 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 3 s 1: iicsn register = 10001110b s 2: iicsn register = 01000000b (example: when aldn bit is read during interrupt servicing) 3: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 2. n = 0 to 2 <2> when wtimn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 3 s 1: iicsn register = 10001110b s 2: iicsn register = 01000100b (example: when aldn bit is read during interrupt servicing) 3: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 2. n = 0 to 2
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 729 of 1113 sep 22, 2011 (4) when arbitration loss occurs due to restart condition during data transfer <1> not extension code (example: address mismatch) st ad6 to ad0 r/w ack d7 to dn st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 3 s 1: iicsn register = 1000x110b s 2: iicsn register = 01000110b (example: when aldn bit is read during interrupt servicing) 3: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. dn = d6 to d0 n = 0 to 2 <2> extension code st ad6 to ad0 r/w ack d7 to dn st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 3 s 1: iicsn register = 1000x110b s 2: iicsn register = 0110x010b (example: when aldn bit is read during interrupt servicing) iiccn.lreln bit is set to 1 by software 3: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. dn = d6 to d0 n = 0 to 2
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 730 of 1113 sep 22, 2011 (5) when arbitration loss occurs due to stop condition during data transfer st ad6 to ad0 r/w ack d7 to dn sp s 1 2 s 1: iicsn register = 1000x110b 2: iicsn register = 01000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. dn = d6 to d0 n = 0 to 2
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 731 of 1113 sep 22, 2011 (6) when arbitration loss occurs due to low level of sda0n pin when attempting to generate a restart condition <1> when wtimn bit = 0 iiccn.sttn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iicsn register = 1000x110b s 2: iicsn register = 1000x000b (wtimn bit = 1) s 3: iicsn register = 1000xx00b (wtimn bit = 0) s 4: iicsn register = 01000000b (example: when aldn bit is read during interrupt servicing) 5: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2 <2> when wtimn bit = 1 iiccn.sttn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iicsn register = 1000x110b s 2: iicsn register = 1000xx00b s 3: iicsn register = 01000100b (example: when aldn bit is read during interrupt servicing) 4: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 732 of 1113 sep 22, 2011 (7) when arbitration loss occurs due to a stop conditio n when attempting to gene rate a restart condition <1> when wtimn bit = 0 sttn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iicsn register = 1000x110b s 2: iicsn register = 1000x000b (wtimn bit = 1) s 3: iicsn register = 1000xx00b 4: iicsn register = 01000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2 <2> when wtimn bit = 1 sttn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 3 s 1: iicsn register = 1000x110b s 2: iicsn register = 1000xx00b 3: iicsn register = 01000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 733 of 1113 sep 22, 2011 (8) when arbitration loss occurs due to low level of sda0n pin when attempting to generate a stop condition <1> when wtimn bit = 0 iiccn.sptn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iicsn register = 1000x110b s 2: iicsn register = 1000x000b (wtimn bit = 1) s 3: iicsn register = 1000xx00b (wtimn bit = 0) s 4: iicsn register = 01000000b (example: when aldn bit is read during interrupt servicing) 5: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2 <2> when wtimn bit = 1 iiccn.sptn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iicsn register = 1000x110b s 2: iicsn register = 1000xx00b s 3: iicsn register = 01000000b (example: when aldn bit is read during interrupt servicing) 4: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 734 of 1113 sep 22, 2011 19.8 interrupt request signal (intiicn) generation timing and wait control the setting of the iiccn.wtimn bit de termines the timing by which the intiicn register is generated and the corresponding wait control, as shown below (n = 0 to 2). table 19-3. intiicn generation timing and wait control during slave device operation du ring master device operation wtimn bit address data reception data transmission a ddress data reception data transmission 0 9 notes 1, 2 8 note 2 8 note 2 9 8 8 1 9 notes 1, 2 9 note 2 9 note 2 9 9 9 notes 1. the slave device?s intiicn signal and wait period oc cur at the falling edge of the ninth clock only when there is a match with the addr ess set to the svan register. at this point, ack is generated regardless of the value set to the iiccn.acken bit. for a slave device that has received an extensio n code, the intiicn signal occurs at the falling edge of the eighth clock. when the address does not match after restart, the intiicn signal is generated at the falling edge of the ninth clock, but no wait occurs. 2. if the received address does not match the contents of the svan register and an extension code is not received, neither the intiicn signal nor a wait occurs. remarks 1. the numbers in the table indicate the number of t he serial clock?s clock signals. interrupt requests and wait control are both synchronized with the falling edge of these clock signals. 2. n = 0 to 2 (1) during address transmission/reception ? slave device operation: interrupt and wait timing is determined in accordance with the conditions shown in notes 1 and 2 above regardless of the wtimn bit setting. ? master device operation: interrupt and wait timing occu rs at the falling edge of the ninth clock regardless of the wtimn bit setting. (2) during data reception ? master/slave device operation: interrupt and wait timing is determined according to the wtimn bit setting. (3) during data transmission ? master/slave device operation: interrupt and wait timing is determined according to the wtimn bit setting.
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 735 of 1113 sep 22, 2011 (4) wait cancellation method the following four wait cancellation methods are available. ? by setting the iiccn.wreln bit to 1 ? by writing to the iicn register ? by setting start condition (iiccn.sttn bit = 1) note ? by setting stop condition (iiccn.sptn bit = 1) note note master only when an 8-clock wait has been selected (wtimn bit = 0), whether or not ack has been generated must be determined prior to wait cancellation. remark n = 0 to 2 (5) stop condition detection the intiicn signal is generated when a stop condition is detected. remark n = 0 to 2
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 736 of 1113 sep 22, 2011 19.9 address match detection method in i 2 c bus mode, the master device can select a particula r slave device by transmitting the corresponding slave address. address match detection is performed automatically by hardware. the intiicn signal occurs when a local address has been set to the svan register and when the address set to the svan register matches the slave address sent by the master device, or when an ex tension code has been received (n = 0 to 2). 19.10 error detection in i 2 c bus mode, the status of the serial data bus pin (sda0n) during data transmission is captured by the iicn register of the transmitting device, so the data of the iicn register prior to transmission can be compared with the transmitted iicn data to enable detection of transmission er rors. a transmission error is judged as having occurred when the compared data values do not match (n = 0 to 2). 19.11 extension code (1) when the higher 4 bits of the receive address are ei ther 0000 or 1111, the extension code flag (iicsn.excn bit) is set for extension code reception and an interrupt request signal (intiicn) is issued at the falling edge of the eighth clock (n = 0 to 2). the local address stored in the svan register is not affected. (2) if 11110xx0 is set to the svan register by a 10-bit address transfer and 11110xx0 is transferred from the master device, the results are as follo ws. note that the intiicn signal oc curs at the falling edge of the eighth clock (n = 0 to 2) ? higher 4 bits of data match: excn bit = 1 ? 7 bits of data match: iicsn.coin bit = 1 (3) since the processing after the interrupt request signa l occurs differs according to the data that follows the extension code, such processing is performed by software. for example, when operation as a slave is not des ired after the extension c ode is received, set the iiccn.lreln bit to 1 and the cpu will ent er the next communi cation wait state. table 19-4. extension code bit definitions slave address r/w bit description 0000 000 0 general call address 0000 000 1 start byte 0000 001 x cbus address 0000 010 x address that is reserved for different bus format 1111 0xx x 10-bit slave address specification
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 737 of 1113 sep 22, 2011 19.12 arbitration when several master devices simultaneously generate a start condition (when the iiccn.sttn bit is set to 1 before the iicsn.stdn bit is set to 1), communication betw een the master devices is performed while the number of clocks is adjusted until the data differs. this kind of operation is called arbitration (n = 0 to 2). when one of the master devices loses in arbitration, an arbitration loss flag ( iicsn.aldn bit) is set to 1 at the timing at which the arbitration loss occurred, and the scl0 n and sda0n lines are both set to high impedance, which releases the bus (n = 0 to 2). arbitration loss is detected based on the timing of the next interrupt request signal (intiicn) (the eighth or ninth clock, when a stop condition is detected, etc.) and the setting of the aldn bit to 1, which is made by software (n = 0 to 2). for details of interrupt request timing, see 19.7 i 2 c interrupt request signals (intiicn) . figure 19-14. arbitration timing example master 1 master 2 transfer lines scl0n sda0n scl0n sda0n scl0n sda0n master 1 loses arbitration hi-z hi-z remark n = 0 to 2
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 738 of 1113 sep 22, 2011 table 19-5. status during arbitration an d interrupt request signal generation timing status during arbitration inte rrupt request generation timing transmitting address transmission read/write data after address transmission transmitting extension code read/write data after extension code transmission transmitting data ack transfer period after data reception when restart condition is detected during data transfer at falling edge of eighth or ninth clock following byte transfer note 1 when stop condition is detected during data transfer w hen stop condition is generated (when iiccn.spien bit = 1) note 2 when sda0n pin is low level while attempting to generate restart condition at falling edge of eighth or ninth clock following byte transfer note 1 when stop condition is detected while attempting to generate restart condition when stop condition is generated (when iiccn.spien bit = 1) note 2 when dsa0n pin is low level while attempting to generate stop condition when scl0n pin is low level while attempting to generate restart condition at falling edge of eighth or ninth clock following byte transfer note 1 notes 1. when the iiccn.wtimn bit = 1, an intiicn signal occu rs at the falling edge of the ninth clock. when the wtimn bit = 0 and the extension code?s slave addre ss is received, an intiicn signal occurs at the falling edge of the eighth clock (n = 0 to 2). 2. when there is a possibility that ar bitration will occur, set the spien bit to 1 for master device operation (n = 0 to 2). 19.13 wakeup function the i 2 c bus slave function is a function that generates an interrupt request signal (intiicn) when a local address and extension code have been received. this function makes processing more efficient by prev enting unnecessary intiicn signals from occurring when addresses do not match. when a start condition is detected, wake up standby mode is set. this wakeup standby mode is in effect while addresses are transmitted due to the pos sibility that an arbitration loss may change the master device (which has generated a start condition) to a slave device. however, when a stop condition is detect ed, the iiccn.spien bit is set regard less of the wakeup function, and this determines whether intiicn signal is enabled or disabled (n = 0 to 2).
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 739 of 1113 sep 22, 2011 19.14 communication reservation 19.14.1 when communication reservation functi on is enabled (iicfn.iicrsvn bit = 0) to start master device communications when the v850 es/jg3-l is not currently using the bus, a communication reservation can be made to enable transmission of a start co ndition when the bus is released. there are two modes in which the bus is not used by the v850es/jg3-l. ? when arbitration results in the v850es/jg3-l being neither the master nor a slave ? when an extension code is received and slave operation is disabled (ack is not returned and the bus was released when the iiccn.lreln bit was set to 1) (n = 0 to 2). if the iiccn.sttn bit is set to 1 while the bus is not us ed by the v850es/jg3-l, a star t condition is automatically generated and a wait status is set after the bus is released (after a stop condition is detected). when the bus release is detected (when a stop condition is detected), writing to the iicn register causes master address transfer to start. at this point, the ii ccn.spien bit should be set to 1 (n = 0 to 2). when sttn has been set to 1, the operation mode (as start condition or as communication reservation) is determined according to the bus status (n = 0 to 2). if the bus has been re leased .............................................a start condition is generated if the bus has not been released (stand by mode).............. communication reservation to detect which operation mode has been determined for the s ttn bit, set the sttn bit to 1, wait for the wait period, then check the iicsn.mstsn bit (n = 0 to 2). the wait periods, which should be set via software, are lis ted in table 19-6. these wait periods can be set by using the smcn, cln1, and cln0 bits of the iicc ln register and the iicxn.clxn bit (n = 0 to 2).
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 740 of 1113 sep 22, 2011 table 19-6. wait periods clock selection clxn smcn cln1 cln0 wait period f xx (when ocksm = 18h set) 0 0 0 0 26 clocks f xx /2 (when ocksm = 10h set) 0 0 0 0 52 clocks f xx /3 (when ocksm = 11h set) 0 0 0 0 78 clocks f xx /4 (when ocksm = 12h set) 0 0 0 0 104 clocks f xx /5 (when ocksm = 13h set) 0 0 0 0 130 clocks f xx (when ocksm = 18h set) 0 0 0 1 47 clocks f xx /2 (when ocksm = 10h set) 0 0 0 1 94 clocks f xx /3 (when ocksm = 11h set) 0 0 0 1 141 clocks f xx /4 (when ocksm = 12h set) 0 0 0 1 188 clocks f xx 0 0 1 0 47 clocks f xx (when ocksm = 18h set) 0 0 1 1 37 clocks f xx /2 (when ocksm = 10h set) 0 0 1 1 74 clocks f xx /3 (when ocksm = 11h set) 0 0 1 1 111 clocks f xx (when ocksm = 18h set) 0 1 0 16 clocks f xx /2 (when ocksm = 10h set) 0 1 0 32 clocks f xx /3 (when ocksm = 11h set) 0 1 0 48 clocks f xx /4 (when ocksm = 12h set) 0 1 0 64 clocks f xx 0 1 1 0 16 clocks f xx (when ocksm = 18h set) 0 1 1 1 13 clocks f xx /2 (when ocksm = 10h set) 0 1 1 1 26 clocks f xx /3 (when ocksm = 11h set) 0 1 1 1 39 clocks f xx (when ocksm = 18h set) 1 1 0 10 clocks f xx /2 (when ocksm = 10h set) 1 1 0 20 clocks f xx /3 (when ocksm = 11h set) 1 1 0 30 clocks f xx /4 (when ocksm = 12h set) 1 1 0 40 clocks f xx /5 (when ocksm = 13h set) 1 1 0 50 clocks f xx 1 1 1 0 10 clocks remarks 1. n = 0 to 2 m = 0, 1 2. = don?t care the communication reservation timing is shown below.
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 741 of 1113 sep 22, 2011 figure 19-15. communication reservation timing 2 1 3456 2 13456 789 scl0n sda0n program processing hardware processing write to iicn set spdn and intiicn sttn =1 communication reservation set stdn generated by master with bus access remark n = 0 to 2 sttn: bit of iiccn register stdn: bit of iicsn register spdn: bit of iicsn register communication reservations are accept ed at the following timing. after the iicsn.stdn bit is set to 1, a communication reservation can be made by setting the iiccn.s ttn bit to 1 before a stop condition is detected (n = 0 to 2). figure 19-16. timing for accep ting communication reservations scl0n sda0n stdn spdn standby mode remark n = 0 to 2
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 742 of 1113 sep 22, 2011 the communication reservation flowchart is illustrated below. figure 19-17. communication reservation flowchart di set1 sttn define communication reservation wait cancel communication reservation no yes iicn register xxh ei mstsn bit = 0? (communication reservation) note (generate start condition) sets sttn bit (communication reservation). secures wait period set by software (see table 17-6 ). confirmation of communication reservation clears user flag. iicn register write operation defines that communication reservation is in effect (defines and sets user flag to any part of ram). note when communication is reserved, the iicn register is written when a stop condition interrupt request occurs. remark n = 0 to 2
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 743 of 1113 sep 22, 2011 19.14.2 when communication reservation functi on is disabled (iic fn.iicrsvn bit = 1) if the iiccn.sttn bit is set when the bus is not being used by the v850es/jg3-l in a bus communication, this request is rejected and a start condition is not generated. t here are two modes in which the bus is not used by the v850es/jg3-l. ? when arbitration results in the v850es/jg 3-l being neither the master nor a slave ? when an extension code is received and slave operation is disabled (ack is not returned and the bus was released when the iiccn.lreln bit was set to 1) (n = 0 to 2). to confirm whether the start condition was generated or request was rejected, check the iicfn.stcfn flag. the time shown in table 19-7 is required until the stcfn flag is se t after setting the sttn bit to 1. therefore, secure the time by software. table 19-7. wait periods ocksenm ocksm1 ocksm0 cln1 cln0 wait period 1 0 0 0 10 clocks 1 0 1 0 15 clocks 1 1 0 0 20 clocks 1 1 1 0 25 clocks 0 0 0 1 0 5 clocks remarks 1. : don?t care 2. n = 0 to 2 m = 0, 1
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 744 of 1113 sep 22, 2011 19.15 cautions (1) when iicfn.stcenn bit = 0 immediately after the i 2 c0n operation is enab led, the bus communi cation status (iicfn.iicbsyn bit = 1) is recognized regardless of the actual bus status. to execute master communicati on in the status where a stop condition has not been detected, generate a stop condition and then re lease the bus before starting the master communication. use the following sequence for generating a stop condition. <1> set the iiccln register. <2> set the iiccn.iicen bit. <3> set the iiccn.sptn bit. (2) when iicfn.stcenn bit = 1 immediately after i 2 c0n operation is enabled, the bus released status (iicbsyn bit = 0) is recognized regardless of the actual bus status. to generate t he first start condition (iiccn.sttn bit = 1), it is necessary to confirm that the bus has been rele ased, so as to not disturb other communications. (3) when the iiccn.iicen bit of the v8 50es/jg3-l is set to 1 while communi cations with other devices are in progress, the start condition may be detected depending on t he status of the communication line. be sure to set the iiccn.iicen bit to 1 when the scl0n and sda0n lines are high level. (4) determine the operation clock frequency by the ii ccln, iicxn, and ocksm registers before enabling the operation (iiccn.iicen bit = 1). to change the operati on clock frequency, clear the iiccn.iicen bit to 0 once. (5) after the iiccn.sttn and iiccn.sptn bits have been set to 1, they must not be re -set without being cleared to 0 first. (6) if transmission has been reserved, set the iiccn.spien bit to 1 so that an interrupt request is generated by the detection of a stop condit ion. after an interrupt request has been generated, the wait status will be released by writing communication data to i 2 cn, then transferring will begin. if an interrupt is not generated by the detection of a stop condition, transmission will halt in the wait st atus because an interrupt request was not generated. however, it is not necessary to set the spien bit to 1 for the software to detect the iicsn.mstsn bit. remark n = 0 to 2 m = 0, 1
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 745 of 1113 sep 22, 2011 19.16 communication operations next the following three operations are shown using flowcharts. (1) master operation in single master system the flowchart when using the v850es/jg3-l as the ma ster in a single master system is shown below. this flowchart is broadly divided into the initia l settings and communication processing. execute the initial settings at startup. if communication with t he slave is required, prepare the communication and then execute communication processing. (2) master operation in multimaster system in the i 2 c0n bus multimaster system, whether the bus is released or used cannot be judged by the i 2 c bus specifications when the bus takes part in a co mmunication. here, when data and clock are at a high level for a certain period (1 frame), the v850es/jg 3-l takes part in a communication with bus released state. this flowchart is broadly divided into the initial settings, communication waiting, and communication processing. the processing when the v850es/jg3-l loses in arbitrati on and is specified as the slave is omitted here, and only the processing as the master is shown. execute the initial settings at startup to take part in a communication. then, wait for the communi cation request as the master or wait for the specification as the slave. the actual communicati on is performed in the communication processing, and it supports the transmission/reception with the sl ave and the arbitration with other masters. (3) slave operation an example of when the v850es/jg3- l is used as the slave of the i 2 c0n bus is shown below. when used as the slave, operation is started by an interrupt. execute t he initial settings at startup, then wait for the intiicn interrupt occurrence (communicati on waiting). when the intiicn interrupt occurs, the communication status is judged and its result is passed as a flag over to the main processing. by checking the flags, necessary communication processing is performed. remark n = 0 to 2
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 746 of 1113 sep 22, 2011 19.16.1 master operation in single master system figure 19-18. master operation in single master system iicxn 0xh iiccln xxh ocksm xxh iicfn 0xh set stcenn, iicrsvn = 0 iiccn xxh acken = wtimn = spien = 1 iicen = 1 set ports initialize i 2 c bus note sptn = 1 svan xxh write iicn write iicn sptn = 1 wreln = 1 start end read iicn acken = 0 wtimn = wreln = 1 no no yes no no no yes yes yes yes stcenn = 1? acken = 1 wtimn = 0 intiicn interrupt occurred? transfer completed? transfer completed? restarted? trcn = 1? ackdn = 1? ackdn = 1? refer to table 4-15 settings when pins are used for alternate functions to set the i 2 c mode before this function is used. transfer clock selection local address setting start condition setting communication start preparation (start condition generation) communication start (address, transfer direction specification) waiting for ack detection waiting for data transmission transmission start communication processing initial settings reception start waiting for data reception no yes intiicn interrupt occurred? waiting for ack detection communication start preparation (stop condition generation) waiting for stop condition detection no yes yes no intiicn interrupt occurred? yes no intiicn interrupt occurred? yes no yes no yes no intiicn interrupt occurred? sttn = 1 note release the i 2 c0n bus (scl0n, sda0n pins = high level) in compliance with the s pecifications of the product involved in the communication. for example, when the eeprom tm outputs a low level to the sda0n pin, set the scl0n pin as an output pin and output clock pulses fr om that output pin until the sda 0n pin is constantly high level. remarks 1. for the transmission and reception formats, confo rm to the specifications of the product involved in the communication. 2. n = 0 to 2, m = 0, 1
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 747 of 1113 sep 22, 2011 19.16.2 master operation in multimaster system figure 19-19. master operation in multimaster system (1/3) iicxn 0xh iiccln xxh ocksm xxh iicfn 0xh set stcenn, iicrsvn iiccn xxh acken = wtimn = spien = 1 iicen = 1 set ports sptn = 1 svan xxh spien = 1 start slave operation slave operation bus release status for a certain period confirmation of bus status is in progress yes confirm bus status note master operation started? communication reservation enable communication reservation disable spdn = 1? stcenn = 1? iicrsvn = 0? a refer to table 4-15 settings when pins are used for alternate functions to set the i 2 c mode before this function is used. transfer clock selection local address setting start condition setting (communication start request issued) (no communication start request) ? waiting for slave specification from another master ? waiting for communication start request (depending on user program) communication start preparation (stop condition generation) waiting for stop condition detection no yes yes no intiicn interrupt occurred? intiicn interrupt occurred? yes no yes no spdn = 1? yes no slave operation no intiicn interrupt occurred? yes no 1 b spien = 0 yes no waiting for communication request communication waiting initial settings note confirm that the bus release st atus (iiccln.cldn bit = 1, iiccln.dadn bit = 1) has been maintained for a certain period (1 frame, for example). when the sda0n pin is constantly low level, determine whether to release the i 2 c0n bus (scl0n, sda0n pins = high level) by referring to the specifications of the product involved in the communication. remark n = 0 to 2, m = 0, 1
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 748 of 1113 sep 22, 2011 figure 19-19. master operation in multimaster system (2/3) sttn = 1 wait slave operation yes mstsn = 1? excn = 1 or coin =1? communication start preparation (start condition generation) securing wait time by software (refer to table 19-6 ) waiting for bus release (communication reserved) wait status after stop condition detection and start condition generation by communication reservation function no intiicn interrupt occurred? yes yes no no a c sttn = 1 wait slave operation yes iicbsyn = 0? excn = 1 or coin =1? communication start preparation (start condition generation) communication reservation disabled communication reservation enabled securing wait time by software (refer to table 19-7 ) waiting for bus release stop condition detection no no intiicn interrupt occurred? yes yes no yes stcfn = 0? no b d c d communication processing communication processing remark n = 0 to 2
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 749 of 1113 sep 22, 2011 figure 19-19. master operation in multimaster system (3/3) write iicn wtimn = 1 wreln = 1 read iicn acken = 1 wtimn = 0 wtimn = wreln = 1 acken = 0 write iicn yes trcn = 1? restarted? mstsn = 1? communication start (address, transfer direction specification) transmission start no yes waiting for data transmission reception start yes no intiicn interrupt occurred? yes no transfer completed? waiting for ack detection yes no intiicn interrupt occurred? waiting for data transmission not in communication yes no intiicn interrupt occurred? no yes ackdn = 1? no yes no c 2 yes mstsn = 1? no yes transfer completed? no yes ackdn = 1? no 2 yes mstsn = 1? no 2 waiting for ack detection yes no intiicn interrupt occurred? yes mstsn = 1? no c 2 yes excn = 1 or coin = 1? no 1 2 sptn = 1 sttn = 1 slave operation end communication processing communication processing remarks 1. conform the transmission and reception formats to the specifications of the product involved in the communication. 2. when using the v850es/jg3-l as the master in a multimaster system, read the iicsn.mstsn bit for each intiicn interrupt occurrenc e to confirm the arbitration result. 3. when using the v850es/jg3-l as the slave in a multimaster system, conf irm the status using the iicsn and iicfn registers for each intiic n interrupt occurrence to determine the next processing. 4. n = 0 to 2
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 750 of 1113 sep 22, 2011 19.16.3 slave operation the following shows the processing pr ocedure of the slave operation. basically, the operation of the slave device is event-d riven. therefore, processing by an intiicn interrupt (processing requiring a significant change of the opera tion status, such as stop condition detection during communication) is necessary. the following description assumes that data communic ation does not support extension codes. also, it is assumed that the intiicn interrupt servicing performs only status change processing and that the actual data communication is passing during the main processing. figure 19-20. outline of so ftware during slave operation i 2 c intiicn signal setting, etc. setting, etc. flag data main processing interrupt servicing therefore, the following three flags ar e prepared so that the data transfer processing can be performed by passing these flags to the main processing instead of intiicn signal. (1) communication mode flag this flag indicates the following communication statuses. clear mode: data communication not in progress communication mode: data communication in progress (valid address detection stop condition detection, ack from master not detected, address mismatch) (2) ready flag this flag indicates that data communication is enabled. th is is the same status as an intiicn interrupt during normal data transfer. this flag is set in the interrupt pr ocessing block and cleared in the main processing block. the ready flag for the first data for transmission is not se t in the interrupt processing block, so the first data is transmitted without clear processing (the address ma tch is regarded as a request for the next data). (3) communication direction flag this flag indicates the direction of communication and is the same as the value of iicsn.trcn bit. the following shows the operation of the ma in processing block during slave operation. i 2 c0n is started and waits for the comm unication enabled status. when communication is enabled, transfer is executed using the communication mode flag and ready flag (the processing of the stop condition and start condition is performed by interrupts, conditions are confirmed by flags). for transmission, transmission is repeated until the master de vice stops returning ack. when the master device stops returning ack, transfer is complete.
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 751 of 1113 sep 22, 2011 for reception, the required number of data items are received and ack is not returned for the next data immediately after transfer is complete. after that, the master device generates the stop condition or restart condition. this causes exit from communications. figure 19-21. slave operation flowchart (1) yes yes yes yes yes yes yes no no no no no no communication mode flag = 1? communication mode flag = 1? communication direction flag = 1? ready flag = 1? communication direction flag = 0? read iicn clear ready flag clear ready flag communication direction flag = 1? wreln = 1 ackdn = 1? clear communication mode flag wreln = 1 write iicn iiccn xxh acken = wtimn = 1 spien = 0, iicen = 1 svan xxh local address setting iicxn 0xh iiccln xxh ocksm xxh set ports transfer clock selection iicfn 0xh set iicrsvn start condition setting transmission start reception start no yes no communication mode flag = 1? yes no ready flag = 1? refer to table 4-15 settings when pins are used for alternate functions to set the i 2 c mode before this function is used. start initial settings communication processing remark n = 0 to 2, m = 0, 1
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 752 of 1113 sep 22, 2011 the following shows an example of the pr ocessing of the slave device by an intiicn interrupt (it is assumed that no extension codes are used here). during an intiicn inte rrupt, the status is confirm ed and the following steps are executed. <1> when a stop condition is detected, communication is terminated. <2> when a start condition is det ected, the address is confirmed. if the address does not match, communication is terminated. if the address matches, t he communication mode is set and wait is released, and operation returns from the interrupt (the ready flag is cleared). <3> for data transmission/reception, when the ready flag is set, operation returns from the interrupt while the i 2 c0n bus remains in the wait status. remark <1> to <3> above correspond to <1> to <3> in figure 19-22 slave operation flowchart (2) . figure 19-22. slave operation flowchart (2) yes yes yes no no no intiicn occurred set ready flag interrupt servicing completed spdn = 1? stdn = 1? coin = 1? clear communication direction flag, ready flag, and communication mode flag <1> <2> <3> communication direction flag trcn set communication mode flag clear ready flag remark n = 0 to 2
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 753 of 1113 sep 22, 2011 19.17 timing of data communication when using i 2 c bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. after outputting the slave address, the master device transm its the iicsn.trcn bit value, which specifies the data transfer direction, and then starts serial communication with the slave device. the shift operation of the iicn register is synchronized with the falling edge of the serial clock pin (scl0n). the transmit data is transferred to the so latch an d is output (msb first) via the sda0n pin. data that is input via the sda0n pin is captured by t he iicn register at the risi ng edge of the scl0n pin. the data communication timing is shown below. remark n = 0 to 2
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 754 of 1113 sep 22, 2011 figure 19-23. example of mast er to slave communication (when 9-clock wait is selected fo r both master and slave) (1/3) (a) start condition ~ address iicn ackdn stdn spdn wtimn h h l l l l h h h l l acken mstsn sttn sptn wreln intiicn trcn iicn ackdn stdn spdn wtimn acken mstsn sttn sptn wreln intiicn trcn scl0n sda0n processing by master device transfer lines processing by slave device 123456789 4 3 2 1 ad6 ad5 ad4 ad3 ad2 ad1 ad0 w ack d4 d5 d6 d7 iicn address iicn data iicn ffh transmit start condition receive (when excn = 1) note note note to cancel slave wait, write ffh to iicn or set wreln. remark n = 0 to 2
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 755 of 1113 sep 22, 2011 figure 19-23. example of mast er to slave communication (when 9-clock wait is selected fo r both master and slave) (2/3) (b) data iicn ackdn stdn spdn wtimn h h l l l l l l h h h h l l l l l acken mstsn sttn sptn wreln intiicn trcn iicn ackdn stdn spdn wtimn acken mstsn sttn sptn wreln intiicn trcn scl0n sda0n processing by master device transfer lines processing by slave device 1 9 8 23456789 3 2 1 d7 d0 d6 d5 d4 d3 d2 d1 d0 d5 d6 d7 iicn data iicn ffh note iicn ffh note iicn data transmit receive note note ack ack note to cancel slave wait, write ffh to iicn or set wreln. remark n = 0 to 2
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 756 of 1113 sep 22, 2011 figure 19-23. example of mast er to slave communication (when 9-clock wait is selected fo r both master and slave) (3/3) (c) stop condition iicn ackdn stdn spdn wtimn h h l l l l h h h l acken mstsn sttn sptn wreln intiicn trcn iicn ackdn stdn spdn wtimn acken mstsn sttn sptn wreln intiicn trcn scl0n sda0n processing by master device transfer lines processing by slave device 123456789 2 1 d7 d6 d5 d4 d3 d2 d1 d0 ad5 ad6 iicn data iicn address iicn ffh note iicn ffh note stop condition start condition transmit note note (when spien = 1) receive (when spien = 1) ack note to cancel slave wait, write ffh to iicn or set wreln. remark n = 0 to 2
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 757 of 1113 sep 22, 2011 figure 19-24. example of sla ve to master communication (when 8-clock wait is selected for master a nd 9-clock wait is selected for slave) (1/3) (a) start condition ~ address iicn ackdn stdn spdn wtimn h h l l l h l acken mstsn sttn l l sptn wreln intiicn trcn iicn ackdn stdn spdn wtimn acken mstsn sttn sptn wreln intiicn trcn scl0n sda0n processing by master device transfer lines processing by slave device 123456789 4 56 3 2 1 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r d4 d3 d2 d5 d6 d7 iicn address iicn ffh note note iicn data start condition ack note to cancel master wait, write ffh to iicn or set wreln. remark n = 0 to 2
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 758 of 1113 sep 22, 2011 figure 19-24. example of sla ve to master communication (when 8-clock wait is selected for master and 9-clock wait is selected for slave (2/3) (b) data iicn ackdn stdn spdn wtimn h h h l l l l l l l h h l l l l l acken mstsn sttn sptn wreln intiicn trcn iicn ackdn stdn spdn wtimn acken mstsn sttn sptn wreln intiicn trcn scl0n sda0n processing by master device transfer lines processing by slave device 1 89 23456789 3 2 1 d7 d0 ack d6 d5 d4 d3 d2 d1 d0 ack d5 d6 d7 note note receive transmit iicn data iicn data iicn ffh note iicn ffh note note to cancel master wait, write ffh to iicn or set wreln. remark n = 0 to 2
v850es/jg3-l chapter 19 i 2 c bus r01uh0165ej0700 rev.7.00 page 759 of 1113 sep 22, 2011 figure 19-24. example of sla ve to master communication (when wait is changed from 8 clocks to 9 clocks for m aster and 9-clock wait is selected for slave) (3/3) (c) stop condition iicn ackdn stdn spdn wtimn h h l l l acken mstsn sttn sptn wreln intiicn trcn iicn ackdn stdn spdn wtimn acken mstsn sttn sptn wreln intiicn trcn scl0n sda0n processing by master device transfer lines processing by slave device 12345678 9 1 d7 d6 d5 d4 d3 d2 d1 d0 ad6 iicn address iicn ffh note note iicn data stop condition start condition (when spien = 1) nack (when spien = 1) note to cancel master wait, write ffh to iicn or set wreln. remark n = 0 to 2
v850es/jg3-l chapter 20 dma function (dma controller) r01uh0165ej0700 rev.7.00 page 760 of 1113 sep 22, 2011 chapter 20 dma function (dma controller) the v850es/jg3-l includes a direct memory access (dma) controller (dmac) that executes and controls dma transfer. the dmac controls data transfer between memory and i/os, between memories, or between i/os based on dma requests issued by on-chip peripheral i/o (serial interf aces, timer/counters, and a/d converter), interrupts from external input pins, or software triggers (memory refers to internal ram or external memory). 20.1 features ? 4 independent dma channels ? transfer unit: 8/16 bits ? maximum transfer count: 65,536 (2 16 ) ? program execution using internal rom during dma transfer ? transfer type: two-cycle transfer ? data transfer between buses that have different bus widths ? transfer mode: single transfer mode ? transfer requests ? request by interrupts from on-chip peripheral i/os (serial interfaces, timer/counters, a/d converter) or interrupts from external input pin ? requests triggered by software ? transfer sources and destinations ? internal ram ? on-chip peripheral i/o ? on-chip peripheral i/o ? on-chip peripheral i/o ? internal ram ? external memory ? external memory ? on-chip peripheral i/o ? external memory ? external memory ? expanded internal ram ? on-chip peripheral i/o ( pd70f3841, 70f3842) ? expanded internal ram ? external memory ( pd70f3841, 70f3842)
v850es/jg3-l chapter 20 dma function (dma controller) r01uh0165ej0700 rev.7.00 page 761 of 1113 sep 22, 2011 20.2 configuration the block diagram of the dmac is shown below. figure 20-1. block diagram of dmac cpu internal ram on-chip peripheral i/o on-chip peripheral i/o bus internal bus data control address control count control channel control dmac v850es/jg3-l bus interface dma source address register n (dsanh/dsanl) dma transfer count register n (dbcn) dma channel control register n (dchcn) dma destination address register n (ddanh/ddanl) dma addressing control register n (dadcn) dma trigger factor register n (dtfrn) external bus external memory expanded internal ram remark n = 0 to 3
v850es/jg3-l chapter 20 dma function (dma controller) r01uh0165ej0700 rev.7.00 page 762 of 1113 sep 22, 2011 the dmac includes the following hardware. table 20-1. configuration of dmac item configuration registers dma source address re gisters 0 to 3 (dsa0 to dsa3) dma destination address registers 0 to 3 (dda0 to dda3) dma transfer count register 0 to 3 (dbc0 to dbc3) dma addressing control registers 0 to 3 (dadc0 to dadc3) dma channel control registers 0 to 3 (dchc0 to dchc3) dma trigger factor registers 0 to 3 (dtfr0 to dtfr3)
v850es/jg3-l chapter 20 dma function (dma controller) r01uh0165ej0700 rev.7.00 page 763 of 1113 sep 22, 2011 20.3 registers (1) dma source address registers 0 to 3 (dsa0 to dsa3) the dsa0 to dsa3 registers set the dma source addresse s (26 bits each) for dma channel n (n = 0 to 3). these registers are divided into two 16-bit registers, dsanh and dsanl. these registers can be read or written in 16-bit units. external memory, on-chip peripheral i/o, or expanded internal ram internal ram ir 0 1 specification of dma transfer source set the address (a25 to a16) of the dma transfer source (the default value is undefined). during dma transfer, the next dma transfer source address is held. when dma transfer is completed, the dma address set first is held. sa25 to sa16 set the address (a15 to a0) of the dma transfer source (the default value is undefined). during dma transfer, the next dma transfer source address is held. when dma transfer is completed, the dma address set first is held. sa15 to sa0 after reset: undefined r/w address: dsa0h fffff082h, dsa1h fffff08ah, dsa2h fffff092h, dsa3h fffff09ah, dsa0l fffff080h, dsa1l fffff088h, dsa2l fffff090h, dsa3l fffff098h dsanl (n = 0 to 3) sa15 sa14 sa13 sa12 sa6 sa5 sa4 sa3 sa2 sa1 sa0 sa7 sa8 sa9 sa10 sa11 dsanh (n = 0 to 3) ir 000 sa22 sa21 sa20 sa19 sa18 sa17 sa16 sa23 sa24 sa25 0 0 cautions 1. be sure to clear bits 14 to 10 of the dsanh register to 0. 2. set the dsanh and dsanl registers duri ng one of the following periods in which dma transfer is disabled (dchcn.enn bit = 0). ? period from after reset to start of first dma transfer ? period from after channel in itialization by dchcn.initn bit to start of dma transfer ? period from after completion of dma transfer (dchcn.tcn bit = 1) to start of the next dma transfer 3. when the value of the dsan register is read, two 16-bit registers, dsanh and dsanl, are read. if reading and updating conflic t, the value being updated may be read (see 20.13 cautions). 4. dma transfer of misaligned 16-bit data with is not supported. if an odd address is specified as the transfer source, the least signifi cant bit of the address is forcibly handled as being 0. 5. following a reset, set the dsanh, dsa nl, ddanh, ddanl, and dbcn registers before starting dma transfer. if these registers ar e not set, dma transfers are not guaranteed.
v850es/jg3-l chapter 20 dma function (dma controller) r01uh0165ej0700 rev.7.00 page 764 of 1113 sep 22, 2011 (2) dma destination address regi sters 0 to 3 (dda0 to dda3) the dda0 to dda3 registers set the dm a destination address (26 bits each) for dma channel n (n = 0 to 3). these registers are divided into two 16-bit registers, ddanh and ddanl. these registers can be read or written in 16-bit units. external memory, on-chip peripheral i/o, or expanded internal ram internal ram ir 0 1 specification of dma transfer destination set the address (a25 to a16) of the dma transfer destination (the default value is undefined). during dma transfer, the next dma transfer destination address is held. when dma transfer is completed, the dma transfer source address set first is held. da25 to da16 set the address (a15 to a0) of the dma transfer destination (the default value is undefined). during dma transfer, the next dma transfer destination address is held. when dma transfer is completed, the dma transfer source address set first is held. da15 to da0 after reset: undefined r/w address: dda0h fffff086h, dda1h fffff08eh, da2h fffff096h, dda3h fffff09eh, dda0l fffff084h, dda1l fffff08ch, dda2l fffff094h, dda3l fffff09ch ddanl (n = 0 to 3) da15 da14 da13 da12 da6 da5 da4 da3 da2 da1 da0 da7 da8 da9 da10 da11 ddanh (n = 0 to 3) ir 000 da22 da21 da20 da19 da18 da17 da16 da23 da24 da25 0 0 cautions 1. be sure to clear bits 14 to 10 of the ddanh register to 0. 2. set the ddanh and ddanl registers during one of the following periods in which dma transfer is disabled (dchcn.enn bit = 0). ? period from after reset to start of first dma transfer ? period from after channel in itialization by dchcn.initn bit to start of dma transfer ? period from after completion of dma transfer (dchcn.tcn bit = 1) to start of the next dma transfer 3. when the value of the ddan register is read, two 16-bit registers, ddanh and ddanl, are read. if reading and updating conflict, a val ue being updated may be read (see 20.13 cautions). 4. dma transfer of misaligned 16-bit data is not supported. if an odd address is specifi ed as the transfer destination, the least signifi cant bit of the address is forcibly handled as being 0. 5. following a reset, set the dsanh, dsa nl, ddanh, ddanl, and dbcn registers before starting dma transfer. if these registers ar e not set, dma transfers are not guaranteed.
v850es/jg3-l chapter 20 dma function (dma controller) r01uh0165ej0700 rev.7.00 page 765 of 1113 sep 22, 2011 (3) dma transfer count registers 0 to 3 (dbc0 to dbc3) the dbc0 to dbc3 registers are 16-bi t registers that set the byte transfe r count for dma channel n (n = 0 to 3). these registers hold the remaini ng transfer count during dma transfer. these registers are decremented by 1 per transfer regard less of the transfer data un it (8/16 bits), and the transfer is terminated if a borrow occurs. the number of transfers specified first is held when dma transfer is complete. these registers can be read or written in 16-bit units. 1st byte transfer or remaining byte transfer count 2nd byte transfer or remaining byte transfer count : 65,536 (2 16 )th byte transfer or remaining byte transfer count bc15 to bc0 0000h 0001h : ffffh byte transfer count setting or remaining byte transfer count during dma transfer after reset: undefined r/w address: dbc0 fffff0c0h, dbc1 fffff0c2h, dbc2 fffff0c4h, dbc3 fffff0c6h dbcn (n = 0 to 3) 15 bc15 14 bc14 13 bc13 12 bc12 11 bc11 10 bc10 9 bc9 8 bc8 7 bc7 6 bc6 5 bc5 4 bc4 3 bc3 2 bc2 1 bc1 0 bc0 cautions 1. set the dbcn register during one of the following peri ods in which dma transfer is disabled (dchcn.enn bit = 0). ? period from after reset to start of first dma transfer ? period from after channel in itialization by dchcn.initn bit to start of dma transfer ? period from after completion of dma transfer (dchcn.tcn bit = 1) to start of the next dma transfer 2. following a reset, set the dsanh, dsa nl, ddanh, ddanl, and dbcn registers before starting dma transfer. if these registers ar e not set, dma transfers are not guaranteed.
v850es/jg3-l chapter 20 dma function (dma controller) r01uh0165ej0700 rev.7.00 page 766 of 1113 sep 22, 2011 (4) dma addressing control registers 0 to 3 (dadc0 to dadc3) the dadc0 to dadc3 registers are 16-bit registers that control the dma transfer mode for dma channel n (n = 0 to 3). these registers can be read or written in 16-bit units. reset sets these registers to 0000h. dadcn (n = 0 to 3) 8 bits 16 bits ds0 0 1 setting of transfer data size increment decrement fixed setting prohibited sad1 0 0 1 1 sad0 0 1 0 1 setting of count direction of the transfer source address increment decrement fixed setting prohibited dad1 0 0 1 1 dad0 0 1 0 1 setting of count direction of the destination address after reset: 0000h r/w address: dadc0 fffff0d0h, dadc1 fffff0d2h, dadc2 fffff0d4h, dadc3 fffff0d6h sad1 sad0 dad1 dad0 0 0 0 0 0ds000 00 0 0 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 cautions 1. be sure to clear bits 15, 13 to 8, and 3 to 0 of the dadcn register to 0. 2. set the dadcn register during one of the following periods in which dma transfer is disabled (dchcn.enn bit = 0). ? period from after reset to start of first dma transfer ? period from after channel in itialization by dchcn.initn bit to start of dma transfer ? period from after completion of dma transfer (dchcn.tcn bit = 1) to start of the next dma transfer 3. the dsn0 bit specifies the si ze of the transfer data, and do es not control bus sizing. for details about external bus sizing, see 5.5.2 (1 ) bus size configuration register (bsc). 4. if the transfer data size is set to 16 bits (ds0 bit = 1), tran sfer cannot be started from an odd address. transfer is always started from an address with the first bi t of the lower address aligned to 0. 5. if dma transfer is executed on an on-chip pe ripheral i/o register (as the transfer source or destination), be sure to specify the same transfer size as th e register size. for example, to execute dma transfer on an 8-bit register , be sure to specify 8-bit transfer.
v850es/jg3-l chapter 20 dma function (dma controller) r01uh0165ej0700 rev.7.00 page 767 of 1113 sep 22, 2011 (5) dma channel control regist ers 0 to 3 (dchc0 to dchc3) the dchc0 to dchc3 registers are 8-bit registers that control dma transfer for dma channel n. these registers can be read or written in 8-bit or 1-bit units. (however, bit 7 is read-only and bits 1 and 2 are write-only. if bit 1 or 2 is read, the value read is always 0.) reset sets these registers to 00h. dchcn (n = 0 to 3) dma transfer is not complete. dma transfer is complete. this bit is set to 1 at the last dma transfer and cleared to 0 when it is read. tcn note 1 0 1 status flag indicating whether dma transfer via dma channel n is complete dma transfer disabled dma transfer enabled dma transfer is enabled when the enn bit is set to 1. when dma transfer is completed (when a terminal count is generated), this bit is automatically cleared to 0. to abort dma transfer, clear the enn bit to 0 by software. to resume dma transfer, set the enn bit to 1 again. when aborting or resuming dma transfer, be sure to follow the procedure described in 18.13 (5) procedure for temporarily stopping dma transfer . enn 0 1 setting of whether dma transfer via dma channel n is to be enabled or disabled this is a software startup trigger for dma transfer. if this bit is set to 1 in the dma transfer enabled state (tcn bit = 0, enn bit = 1), dma transfer is started. stgn note 2 after reset: 00h r/w address: dchc0 fffff0e0h, dchc1 fffff0e2h, dchc2 fffff0e4h, dchc3 fffff0e6h tcn note 1 0 0 0 0 initn note 2 stgn note 2 enn <0> <1> <2> 3 4 5 6 <7> initn note 2 if the initn bit is set to 1 with dma transfer disabled (enn bit = 0), the dma transfer status can be initialized. notes 1. the tcn bit is read-only. 2. the initn and stgn bits are write-only. cautions 1. be sure to clear bits 6 to 3 of the dchcn register to 0. 2. when dma transfer is completed (when a terminal count is genera ted), the enn bit is cleared to 0 and then the tcn bit is set to 1. if the dchcn regi ster is read while its bits are being updated, a value indicati ng ?transfer not completed and tr ansfer is disab led? (tcn bit = 0 and enn bit = 0) may be read.
v850es/jg3-l chapter 20 dma function (dma controller) r01uh0165ej0700 rev.7.00 page 768 of 1113 sep 22, 2011 (6) dma trigger factor registers 0 to 3 (dtfr0 to dtfr3) the dtfr0 to dtfr3 registers are 8-bit registers that control the dma transfer start trigger via interrupt request signals from on-chip peripheral i/o. the interrupt request signals set by these re gisters serve as dma transfer start factors. these registers can be read or written in 8-bit units. however, dfn bit can be read or written in 1-bit units. reset sets these registers to 00h. dtfrn (n = 0 to 3) no dma transfer request dma transfer request dfn note 0 1 dma transfer request status flag after reset: 00h r/w address: dtfr0 fffff810h, dtfr1 fffff812h, dtfr2 fffff814h, dtfr3 fffff816h dfn 0 ifcn5 ifcn4 ifcn3 ifcn2 ifcn1 ifcn0 0 1 2 3 4 5 6 <7> note do not write 1 to the dfn bit by us ing software. write 0 to this bit to clear a dma transfer request if an interrupt specified as the dma transfer start fa ctor occurs while dma transfer is disabled. cautions 1. set the ifcn5 to ifcn0 bits during one of the following periods in which dma transfer is disabled (dchcn.enn bit = 0). ? period from after reset to start of first dma transfer ? period from after channel in itialization by dchcn.initn bit to start of dma transfer ? period from after completion of dma transfer (dchcn.tcn bit = 1) to start of the next dma transfer 2. be sure to follow the steps below when changing the dtfrn re gister settings. (n = 0 to 3, m = 0 to 3, n m) <1> stop the dman operation of the ch annel to be rewritten (dchcn.enn bit = 0). <2> change the dtfrn regi ster settings. (be sure to set dfn bit = 0 and change the settings in the 8-bit manipulation.) <3> confirm that dfn bit = 0. (st op the interrupt genera tion source operation beforehand.) <4> enable the dman operation (enn bit = 1). 3. an interrupt request that is generated in the standby mode (idle1, idle2, stop, or sub-idle mode) does not start the dma transf er cycle (nor is the dfn bit set to 1). 4. if a dma start factor is selected by the ifcn 5 to ifcn0 bits, the dfn bi t is set to 1 when an interrupt from the selected on-chip peripher al i/o occurs, regardless of whether the dma transfer is enabled. if dma is enabled in this status, dma transfer immediately starts. remark for the ifcn5 to ifcn0 bits, see table 20-2 dma start factors .
v850es/jg3-l chapter 20 dma function (dma controller) r01uh0165ej0700 rev.7.00 page 769 of 1113 sep 22, 2011 table 20-2. dma start factors(1/2) ifcn5 ifcn4 ifcn3 ifcn2 ifcn1 ifcn0 interrupt source 0 0 0 0 0 0 dma request by interrupt disabled 0 0 0 0 0 1 intp0 0 0 0 0 1 0 intp1 0 0 0 0 1 1 intp2 0 0 0 1 0 0 intp3 0 0 0 1 0 1 intp4 0 0 0 1 1 0 intp5 0 0 0 1 1 1 intp6 0 0 1 0 0 0 intp7 0 0 1 0 0 1 inttq0ov 0 0 1 0 1 0 inttq0cc0 0 0 1 0 1 1 inttq0cc1 0 0 1 1 0 0 inttq0cc2 0 0 1 1 0 1 inttq0cc3 0 0 1 1 1 0 inttp0ov 0 0 1 1 1 1 inttp0cc0 0 1 0 0 0 0 inttp0cc1 0 1 0 0 0 1 inttp1ov 0 1 0 0 1 0 inttp1cc0 0 1 0 0 1 1 inttp1cc1 0 1 0 1 0 0 inttp2ov 0 1 0 1 0 1 inttp2cc0 0 1 0 1 1 0 inttp2cc1 0 1 0 1 1 1 inttp3cc0 0 1 1 0 0 0 inttp3cc1/intua5t note 0 1 1 0 0 1 inttp4cc0 0 1 1 0 1 0 inttp4cc1 0 1 1 0 1 1 inttp5cc0 0 1 1 1 0 0 inttp5cc1 0 1 1 1 0 1 inttm0eq0 0 1 1 1 1 0 intcb0r/intiic1 0 1 1 1 1 1 intcb0t 1 0 0 0 0 0 intcb1r 1 0 0 0 0 1 intcb1t 1 0 0 0 1 0 intcb2r 1 0 0 0 1 1 intcb2t 1 0 0 1 0 0 intcb3r 1 0 0 1 0 1 intcb3t 1 0 0 1 1 0 intua0r/intcb4r 1 0 0 1 1 1 intua0t/intcb4t 1 0 1 0 0 0 intua1r/intiic2 1 0 1 0 0 1 intua1t 1 0 1 0 1 0 intua2r/intiic0 1 0 1 0 1 1 intua2t 1 0 1 1 0 0 intad note pd70f3792, 70f3793, 70f 3841, 70f3842 only remark n = 0 to 3
v850es/jg3-l chapter 20 dma function (dma controller) r01uh0165ej0700 rev.7.00 page 770 of 1113 sep 22, 2011 table 20-2. dma start factors(2/2) ifcn5 ifcn4 ifcn3 ifcn2 ifcn1 ifcn0 interrupt source 1 0 1 1 0 1 intkr 1 0 1 1 1 0 intrtc1 note 1 0 1 1 1 1 intua3r note 1 1 0 0 0 0 intua3t note 1 1 0 0 0 1 intua4r note 1 1 0 0 1 0 intua4t note 1 1 0 0 1 1 intua5r note 1 1 0 1 0 0 intuc0r note 1 1 0 1 0 1 intuc0t note other than above setting prohibited note pd70f3792, 70f3793, 70f 3841, 70f3842 only remark n = 0 to 3
v850es/jg3-l chapter 20 dma function (dma controller) r01uh0165ej0700 rev.7.00 page 771 of 1113 sep 22, 2011 20.4 transfer sources and destinations table 20-3 shows the relationship betw een the transfer sources and destinations ( : transfer enabled, : transfer disabled). table 20-3. relationship between transfer sources and destinations transfer destination internal rom on-chip peripheral i/o internal ram expanded internal ram external memory on-chip peripheral i/o internal ram expanded internal ram external memory source internal rom caution the operation is not guaranteed for combinations of transfer destination and source marked with ? ? in table 20-3. 20.5 transfer modes single transfer is supported as the transfer mode. in single transfer mode, the bus is released at each byte/h alfword transfer. if there is a subsequent dma transfer request, transfer is performed again once. this operation continues until a terminal count occurs. figure 20-2. single transfer (using only one channel) dma0 transfer request bus mastership dma0 dma0 note note dma0 note note note note dma0 note dma0 note note when a dma0 transfer request is acknowledged, a dma transfer is performed and bus mastership is released to the cpu. this operation is repeated as long as dma0 transfer is requested, until the tc0 bit is set to 1 (completion of dma transfer). note the cpu is using the bus, or the bus is unused.
v850es/jg3-l chapter 20 dma function (dma controller) r01uh0165ej0700 rev.7.00 page 772 of 1113 sep 22, 2011 20.6 transfer types two-cycle transfer is supported as the transfer type. in two-cycle transfer, data is transferred in two cycles, a read cycle and a write cycle. in the read cycle, the transfer source address is output a nd data is read from the source to the dmac. in the write cycle, the transfer destination a ddress is output and data is written from the dmac to the destination. an idle cycle of one clock is always inserted between a re ad cycle and a write cycle. if the data bus width differs between the transfer source and destination in two-cycle dma transfer, the operation is performed as follows. <16-bit data transfer (dadcn.dsn0 bit = 1)> <1> transfer from 32-bit bus to 16-bit bus a read cycle (the higher or lower 16-bit data) is generated, followed by a write cycle (16 bits). <2> transfer from 16-/32-bit bus to 8-bit bus a 16-bit read cycle is generated once, and t hen an 8-bit write cycle is generated twice. <3> transfer from 8-bit bus to 16-/32-bit bus an 8-bit read cycle is generated twice, and then a 16-bit write cycle is generated once. <4> transfer from 16-bit bus to 32-bit bus a 16-bit read cycle is generated once, and t hen a 16-bit write cycle is generated once. for dma transfer executed on an on-chip pe ripheral i/o register (transfer sour ce/destination), be sure to specify the same transfer size as the register size. for example, to execute dma transfer on an 8-bit register, be sure to specify byte (8-bit) transfer. remark the bus width of each transfer source and destination is as follows. ? on-chip peripheral i/o: 16 bits ? internal ram: 32 bits ? external memory: 8 bits or 16 bits ? expanded internal ram: 16 bits
v850es/jg3-l chapter 20 dma function (dma controller) r01uh0165ej0700 rev.7.00 page 773 of 1113 sep 22, 2011 20.7 dma channel priorities the dma channel priorities are fixed as follows. dma channel 0 > dma channel 1 > dma channel 2 > dma channel 3 when the dmac has released the bus, if another dma transfe r request that has a higher priority is issued, the one that has the higher priority always takes precedence. if a new transfer request for the same channel and a transfer request for another channel with a lower priority are generated in a transfer cycle, dma transfer on the channel with the lower priority is executed after the bus is released to the cpu (the new transfer request for the same channel is ignored in the transfer cycle). the priorities are checked for every transfer cycle. figure 20-3. single transfer (using multiple channels) dma3 dma0 transfer request dma1 transfer request dma2 transfer request dma3 transfer request bus mastership dma0 note note dma1 dma2 note dma3 note note note note note note note if multiple dma transfer requests are acknowledged at t he same time, transfer is executed from the one with the higher priority. note the cpu is using the bus, or the bus is unused.
v850es/jg3-l chapter 20 dma function (dma controller) r01uh0165ej0700 rev.7.00 page 774 of 1113 sep 22, 2011 20.8 time related to dma transfer the time required to respond to a dma request, and the minimum number of clocks required for dma transfer are shown below. single transfer: dma response time (<1>) + transfer source memory access (<2>) + 1 note 1 + transfer destination memory access (<2>) table 20-4. number of execution clocks during dma cycle dma cycle number of execution clocks <1> dma request response time 4 clocks (min.) + noise elimination time note 2 external memory access depends on connected memory note 3 . internal ram access 2 clocks peripheral i/o register access 3 clocks + number of wait cycles specified by vswc register note 4 <2> memory access expanded internal ram note 5 4 clocks notes 1. one clock is always inserted between a read cycle and a write cycle in dma transfer. 2. if an external interrupt (intpn) is specified as the tr igger to start dma transfer, noise elimination time is added (n = 0 to 7). 3. transfer must be executed twice when transferring 16-bit data using the 8-bit bus. 4. more wait cycles may be necessary for accessing a special register described in 3.4.9 (1) . 5. before using the expanded internal ram, be sure to execute the initial setting of the expanded internal ram. for details of the expanded internal ram, see 3.4.3 (3) initial settings for expanded internal ram .
v850es/jg3-l chapter 20 dma function (dma controller) r01uh0165ej0700 rev.7.00 page 775 of 1113 sep 22, 2011 20.9 dma transfer start factors there are two types of dma transfe r start factors, as shown below. (1) request by software if the dchcn.stgn bit is set to 1 while the dchcn.tcn bit is 0 and dchcn.enn bit is 1 (dma transfer enabled), dma transfer starts. to request the next dma transfer cycle immediately after that, confirm, by using the dbcn register, that the preceding dma transfer cycle has been completed, and set the stgn bit to 1 again (n = 0 to 3). tcn bit = 0, enn bit = 1 stgn bit = 1 ? starts the first dma transfer. confirm that the contents of the dbcn register have been updated. stgn bit = 1 ? starts the second dma transfer. : generation of terminal count ? enn bit = 0, tc n bit = 1, and intdman signal is generated. (2) request by on-chip peripheral i/o if an interrupt request is g enerated from the on-chip peripheral i/o se t by the dtfrn register when the tcn bit is 0 and enn bit is 1 (dma transfer enabled), dma transfer starts (n = 0 to 3). cautions 1. two start factors (software trigger a nd hardware trigger) cannot be used for one dma channel. if two start factors are simultan eously generated for one dma channel, only one of them is valid. however, the va lid start factor cannot be identified. 2. a new transfer request generated for a dma channel after the preceding dma transfer request was generated and befo re the transfer is comple te is ignored (cleared). 3. the transfer request interval for the sam e dma channel varies depending on the setting of bus waits in the dma transfer cycle, the start status of the other channels, or an external bus hold request. in particul ar, as described in caution 2, a new transfer request generated for the same channel before a dm a transfer cycle starts or during a dma transfer cycle is ignored. therefore, the transfer request inte rval for the same dma channel must be sufficiently secured by the system. when a software trigger is used, whether the preceding dma tr ansfer cycle has completed can be checked by reading the dbcn register.
v850es/jg3-l chapter 20 dma function (dma controller) r01uh0165ej0700 rev.7.00 page 776 of 1113 sep 22, 2011 20.10 dma abort factors dma transfer is aborted if a bus hold occurs. the same applies if transfer is executed between t he internal memory/on-chip peripheral i/o and internal memory/on-chip peripheral i/o. when the bus hold is cleared, dma transfer is resumed. 20.11 end of dma transfer when dma transfer has been completed the number of time s set to the dbcn register and when the dchcn.enn bit is cleared to 0 and tcn bit is set to 1, a dma trans fer end interrupt request signal (intdman) is generated for the interrupt controller (intc) (n = 0 to 3). the v850es/jg3-l does not output a terminal count signal to an external device. therefore, confirm completion of dma transfer by using the dma transfer end interrupt or polling the tcn bit. 20.12 operation timing the operation timing of dma is as follows. four examples are shown: ? multiple channels request dma transfer simultaneously (see figure 20-4 ). ? a new dma transfer with a higher priority is requested during a dma transfer (see figure 20-5 ). ? a new dma transfer request for the same channel is ignored (one channel) (see figure 20-6 ). ? a new dma transfer request for the same channel is ignored (multiple channels) (see figure 20-7 ).
v850es/jg3-l chapter 20 dma function (dma controller) r01uh0165ej0700 rev.7.00 page 777 of 1113 sep 22, 2011 figure 20-4. priority of dma (1) read write idle write read dma0 transfer request system clock dma1 transfer request dma2 transfer request dma transfer mode of processing df0 bit df1 bit df2 bit idle dma2 processing cpu processing dma1 processing cpu processing cpu processing dma0 processing read preparation for transfer end processing preparation for transfer preparation for transfer end processing <1> <2> <4> <3> <1> when a dma transfer request is generated, the corresponding df bit is set (1). <2> starting dma0 transfer clears the df0 bit (0). <3> starting dma1 transfer clears the df1 bit (0). <4> starting dma2 transfer clears the df2 bit (0). remarks 1. transfer in the order of dma0 dma1 dma2 2. in the case of transfer between external memory spaces (multiplexed bus, no wait)
v850es/jg3-l chapter 20 dma function (dma controller) r01uh0165ej0700 rev.7.00 page 778 of 1113 sep 22, 2011 figure 20-5. priority of dma (2) preparation for transfer read write idle dma0 transfer request system clock dma1 transfer request dma2 transfer request dma transfer mode of processing df0 bit df1 bit df2 bit cpu processing dma0 processing cpu processing dma1 processing cpu processing dma0 processing read write idle end processing read preparation for transfer preparation for transfer end processing <1> <2> <5> <3> <4> <1> when a dma transfer request is generated, the corresponding df bit is set (1). <2> starting dma0 transfer clears the df0 bit (0). <3> starting dma1 transfer clears the df1 bit (0). <4> after the dma transfer on channel 0 is complete, a new dma transfer is requested for channel 0. <5> starting dma0 transfer clears the df0 bit (0). transfer on channel 2 is held pending. remarks 1. transfer in the order of dma0 dma1 dma0 (dma2 is held pending.) 2. in the case of transfer between external memory spaces (multiplexed bus, no wait)
v850es/jg3-l chapter 20 dma function (dma controller) r01uh0165ej0700 rev.7.00 page 779 of 1113 sep 22, 2011 figure 20-6. period in which dma transfer request is ignored (1) <1> <2> <2> <2> preparation for transfer read cycle write cycle idle end processing dma transfer mode of processing dfn bit system clock transfer request generated after this can be acknowledged dma0 processing cpu processing cpu processing note 2 note 2 dman transfer request note 1 note 2 a new dma transfer request is not acknowledged <1> when a dma transfer request is generated, the corresponding df bit is set (1). <2> a new dma transfer request is ignored because the preceding transfer is not complete. notes 1. interrupt from on-chip peripheral i/o, or software trigger (dchcn.stgn bit) 2. a new dma request for the same channel is ignored between when the transfer request is generated and the end processing. remark in the case of transfer between external memory spaces (multiplexed bus, no wait)
v850es/jg3-l chapter 20 dma function (dma controller) r01uh0165ej0700 rev.7.00 page 780 of 1113 sep 22, 2011 figure 20-7. period in which dma transfer request is ignored (2) read write idle write read dma0 transfer request system clock dma1 transfer request dma2 transfer request dma transfer mode of processing df0 bit df1 bit df2 bit idle <1> <2> <3> <4> cpu processing dma0 processing cpu processing dma1 processing cpu processing read preparation for transfer dma0 processing end processing preparation for transfer preparation for transfer end processing <1> dma0 transfer request <2> a new dma0 transfer request is generated during dma0 transfer. a dma transfer request for the same channel is ignored during dma transfer. <3> requests for dma0 and dma1 are generated at the same time. the dma0 request is ignored (a dma transfer request for the same channel during transfer is ignored). the dma1 request is acknowledged. <4>requests for dma0, dma1, and dma2 are generated at the same time. the dma1 request is ignored (a dma transfer request for the same channel during transfer is ignored). the dma0 request is acknowledged according to priority. the dma2 request is held pending. (the next transfer will occur for dma2).
v850es/jg3-l chapter 20 dma function (dma controller) r01uh0165ej0700 rev.7.00 page 781 of 1113 sep 22, 2011 20.13 cautions (1) vswc register when using the dmac, be sure to specify an appropriate va lue for the vswc register, in accordance with the operating frequency. if an inappropriate value is specified for the vswc regist er, the dmac does not operat e correctly (for details about the vswc register, refer to 3.4.8 (1) (a) system wait control register (vswc) ). (2) dma transfer execu ted for internal ram when a data access instruction located in the intern al ram is executed for a misaligned address, do not execute the instruction via dma to transfer data to/from the internal ram, because the cpu may not operate correctly afterward. similarly, when executing a dma transfer to transfer data to/from the internal ram, do not execute a data access instruction located in the internal ram for a misaligned address. (3) reading dchcn.tcn bit (n = 0 to 3) the tcn bit is cleared to 0 when it is read, but not if read at a specific time. to definitely clear the tcn bit, add the following processing. (a) when waiting for completion of dma transfer by polling tcn bit confirm that the tcn bit has been set to 1 (after tcn bit = 1 is read), and then read the tcn bit three more times. (b) when reading tcn bit in interrupt service routine read the tcn bit three times.
v850es/jg3-l chapter 20 dma function (dma controller) r01uh0165ej0700 rev.7.00 page 782 of 1113 sep 22, 2011 (4) dma transfer initialization pr ocedure (setting dchcn.initn bit to 1) even if the initn bit is set to 1 when the channel exec uting dma transfer is to be initialized, the channel may not be initialized. to definitely initialize the channel, execute eit her of the following two procedures. (a) temporarily stop transf er on all dma channels initialize the channel executing dma transfer using the procedure in <1> to <7> below. note, however, that tcn bit is cleared to 0 when step <5> is executed. make sure that the other processing programs do not expect that the tcn bit is 1. <1> disable interrupts (di). <2> read the dchcn.enn bit for dma channels other than the one to be forcibly terminated, and transfer the value to a general-purpose register. <3> clear the enn bit for the dma channels used (incl uding the channel to be forcibly terminated) to 0. to clear the enn bit for the last dma channel, ex ecute the clear instruction twice. if the dma transfer source or destination is the internal ram, execute the instruction three times. example: execute instructions in the following order if channels 0, 1, and 2 are used (if the internal ram is not the transfer source or destination). ? write 00h to dchc0 (clear the e00 bit to 0). ? write 00h to dchc1 (clear the e11 bit to 0). ? write 00h to dchc2 (clear the e22 bit to 0). ? write 00h to dchc2 again (clear the e22 bit to 0). <4> write 04h to dchcn corresponding to the channel to be forcibly terminated (set the initn bit to 1). <5> read the tcn bit of each channel not to be forcib ly terminated. if both the tcn bit and the enn bit read in <2> are 1 (logical product (and) is 1), clear the saved enn bit to 0. <6> after the operation in <5>, write the enn bit value to the dchcn register. <7> enable interrupts (ei). cautions 1. be sure to execute step <5> abo ve to prevent illegal setting of the enn bit of the channels on which dma transfer has be en normally completed between <2> and <3>. 2. clearing the enn bit to 0 (<3>) and se tting the initn bit to 1 (<4>) by using a bit manipulation instruction clear s the tcn bit, so a bit manipulation instruction must not be used.
v850es/jg3-l chapter 20 dma function (dma controller) r01uh0165ej0700 rev.7.00 page 783 of 1113 sep 22, 2011 (b) repeatedly setting the initn bit until tr ansfer is forcibly terminated correctly <1> before starting dma, copy the initial number of tr ansfers of the channel to be forcibly terminated to a general-purpose register. <2> suppress a request from the dma request source for the channel to be forcibly terminated (stop operation of the on-ch ip peripheral i/o). <3> check that the dma transfer request for the channel to be forcibly terminated is not held pending, by using the dtfrn.dfn bit. if a dma transfer reques t is held pending, wait until execution of the pending dma transfer request is completed. <4> when it has been confirmed that the dma request for the channel to be forcibly terminated is not held pending, clear the enn bit to 0. <5> again, clear the enn bit for the channel to be forcibly terminated to 0. if the internal ram is the transfer source or des tination of the channel to be forcibly terminated, execute this operation again. <6> set the initn bit of the channel to be forcibly terminated to 1. <7> read the value of the dbcn register corresponding to the channel to be forcibly terminated, and compare it with the value copied in <1>. if the tw o values do not match, repeat operations <6> and <7>. remarks 1. when the value of the dbcn regist er is read in <7>, the initial number of transfers is read if forced termination has been correctly completed. if not, the remaining number of transfers is read. 2. note that method (b) may take a long time if the application frequently uses dma transfer for a channel other than the dma channel to be forcibly terminated. (5) procedure for tempor arily stopping dma transfer (clearing enn bit) stop and resume the dma transfer under ex ecution using the following procedure. <1> suppress a transfer request from the dma request s ource (stop operation of t he on-chip peripheral i/o). <2> check the dma transfer request is not held pending , by using the dfn bit (check if the dfn bit = 0). if a request is held pending, wait until execution of the pending dma transfer request is completed. <3> check the tcn bit to confirm that dma transfer is not complete (confirm that the tcn bit is 0). if the tcn bit is 1, execute the dma transfer completion processing. <4> if it has been confirmed that no dma transfer reques t is held pending, clear the enn bit to 0 (this operation suspends dma transfer). <5> set the enn bit to 1 to resume dma transfer. <6> resume the operation of the dm a request source that has been stoppe d (start operation of the on-chip peripheral i/o). (6) memory boundary the operation is not guaranteed if the address of the transfer source or destination exceeds the area of the dma source or destination (external memory, internal ram, on-chip peripheral i/o, or expanded internal ram) during dma transfer. (for details about the addresses of each area, see figure 3-2 .) (7) transferring misaligned data dma transfer of misaligned 16-bit data is not supported. if an odd address is specified as the transfer source or destination, the least significant bit of the address is forcibly handled as 0.
v850es/jg3-l chapter 20 dma function (dma controller) r01uh0165ej0700 rev.7.00 page 784 of 1113 sep 22, 2011 (8) bus arbitration for cpu because the dma controller is a higher priority bus master than the cpu, a cpu access that takes place during dma transfer is held pending until the dma trans fer cycle is completed and the bus is released to the cpu. however, the cpu can access the internal rom and the internal ram for which dma transfer is not being executed. ? the cpu can access the internal rom and internal ram when dma transfer is being executed between the external memory and on-chip peripheral i/o, or the expanded internal ram and on-chip peripheral i/o. ? the cpu can access the internal rom when dma transfer is being executed between the on-chip peripheral i/o and the internal ram. (9) registers/bits that must not be rewritten during dma transfer set up the following registers during one of the period s below when a dma transfer is not under execution (n = 0 to 3). [registers] ? dsanh, dsanl, ddanh, ddanl, dbcn, and dadcn registers ? dtfrn.ifcn5 to dtfrn.ifcn0 bits [timing of setting] ? period from after reset to start of the first dma transfer ? period from after channel initiali zation to start of dma transfer ? period from after completion of dma transfer (tcn bit = 1) to start of the next dma transfer (10) be sure to set the following register bits to 0 (n = 0 to 3). ? bits 14 to 10 of dsanh register ? bits 14 to 10 of ddanh register ? bits 15, 13 to 8, and 3 to 0 of dadcn register ? bits 6 to 3 of dchcn register (11) dma start factor do not start multiple dma channels with the same star t factor. if multiple channels are started with the same factor, dma for which a channel has already been set may starts or a dma channel with a lower priority may be acknowledged before a dma channel with a higher priority. the operation cannot be guaranteed in this case.
v850es/jg3-l chapter 20 dma function (dma controller) r01uh0165ej0700 rev.7.00 page 785 of 1113 sep 22, 2011 (12) read values of dsan and ddan registers if the dsan and ddan registers are read during a dma transfer, the values before and after the registers were updated might be read. for example, if the dsanh regist er and then the dsanl register are read when the dma transfer source address (dsan register) is 0000ffffh and the coun t direction is incremental (dadcn.sad1 and dadcn.sad0 bits = 00), the value of the dsanl regist er differs as follows, depending on whether dma transfer is executed immediately after the dsanh register is read. (a) if dma transfer does not occur wh ile dsan register is being read <1> reading dsanh register value: dsanh register = 0000h <2> reading dsanl register value: dsanl register = ffffh (b) if dma transfer occurs while dsan register is being read <1> reading dsanh register value: dsanh register = 0000h <2> occurrence of dma transfer <3> incrementing dsan register: dsan register = 00010000h <4> reading dsanl register value: dsanl register = 0000h (13) setting up dma transfer again when re-specifying dma settings by using t he ddanh, ddanl, dsanh, dsanl, dbcn, and dadcn registers during the current dma (the tcn bit is set to 1), be sure to initialize the dma channels first. the dma transfer must be initialized using the procedure described in 20.13 (4) dma transfer initialization procedure .
v850es/jg3-l chapter 21 interrupt ser vicing/exception proc essing function r01uh0165ej0700 rev.7.00 page 786 of 1113 sep 22, 2011 chapter 21 interrup t servicing/exception processing function the v850es/jg3-l is provided with an interrupt controller dedicated to in terrupt servicing (intc) and can handle a total of 57 interrupt requests. an interrupt is an event that occurs independently of program execution, and an ex ception is an event whose occurrence is dependent on program execution. the v850es/jg3-l can handle interrupt request signals from the on-chip peripheral hardware and external sources. moreover, exception proc essing can be started by a trap instru ction (software exception) or by generation of an exception event (illegal ex ecution of instructions) (exception trap). 21.1 features interrupts ? non-maskable interrupts: external: 1, internal: 1 source ? maskable interrupts: external: 8, internal: 47 sources ( pd70f3737, 70f3738) external: 8, internal: 54 sources ( pd70f3792, 70f3793, 70f3841, 70f3842) ? 8 levels of programmable priorities (maskable interrupts) ? multiple interrupt control according to priority ? masks can be specified for eac h maskable interrupt request. ? noise elimination, edge detection, and valid edge s pecification for external interrupt request signals exceptions ? software exceptions: 32 sources ? exception trap: 2 sources (illegal opcode exception, debug trap) the interrupt/exception sources are listed in table 21-1.
v850es/jg3-l chapter 21 interrupt ser vicing/exception proc essing function r01uh0165ej0700 rev.7.00 page 787 of 1113 sep 22, 2011 table 21-1. interrupt source list (1/3) type default priority name trigger generating unit exception code handler address interrupt control register reset ? reset reset pin input reset input by internal source reset 0000h 00000000h ? ? nmi nmi pin valid edge input pin 0010h 00000010h ? non-mask able ? intwdt2 wdt2 overflow wdt2 0020h 00000020h ? ? trap0n note 2 trap instruction ? 004nh note 2 00000040h ? software exception ? trap1n note 2 trap instruction ? 005nh note 2 00000050h ? exception trap ? ilgop/ dbg0 illegal opcode/ dbtrap instruction ? 0060h 00000060h ? 0 intlvi low voltage detection poclvi 0080h 00000080h lviic 1 intp0 external interrupt pin input edge detection (intp0) pin 0090h 00000090h pic0 2 intp1 external interrupt pin input edge detection (intp1) pin 00a0h 000000a0h pic1 3 intp2 external interrupt pin input edge detection (intp2) pin 00b0h 000000b0h pic2 4 intp3 external interrupt pin input edge detection (intp3) pin 00c0h 000000c0h pic3 5 intp4 external interrupt pin input edge detection (intp4) pin 00d0h 000000d0h pic4 6 intp5 external interrupt pin input edge detection (intp5) pin 00e0h 000000e0h pic5 7 intp6 external interrupt pin input edge detection (intp6) pin 00f0h 000000f0h pic6 8 intp7 external interrupt pin input edge detection (intp7) pin 0100h 00000100h pic7 9 inttq0ov tmq0 overflow tmq0 0110h 00000110h tq0ovic 10 inttq0cc0 tmq0 capture 0/compare 0 match tmq0 0120h 00000120h tq0ccic0 11 inttq0cc1 tmq0 capture 1/compare 1 match tmq0 0130h 00000130h tq0ccic1 12 inttq0cc2 tmq0 capture 2/compare 2 match tmq0 0140h 00000140h tq0ccic2 13 inttq0cc3 tmq0 capture 3/compare 3 match tmq0 0150h 00000150h tq0ccic3 14 inttp0ov tmp0 overflow tmp0 0160h 00000160h tp0ovic 15 inttp0cc0 tmp0 capture 0/compare 0 match tmp0 0170h 00000170h tp0ccic0 16 inttp0cc1 tmp0 capture 1/compare 1 match tmp0 0180h 00000180h tp0ccic1 17 inttp1ov tmp1 overflow tmp1 0190h 00000190h tp1ovic 18 inttp1cc0 tmp1 capture 0/compare 0 match tmp1 01a0h 000001a0h tp1ccic0 19 inttp1cc1 tmp1 capture 1/compare 1 match tmp1 01b0h 000001b0h tp1ccic1 20 inttp2ov tmp2 overflow tmp2 01c0h 000001c0h tp2ovic 21 inttp2cc0 tmp2 capture 0/compare 0 match tmp2 01d0h 000001d0h tp2ccic0 maskable 22 inttp2cc1 tmp2 capture 1/compare 1 match tmp2 01e0h 000001e0h tp2ccic1 notes 1. the software that generated the ex ception event can be checked using the exception code set to the eicc bit of the ecr register. 2. n = 0 to fh
v850es/jg3-l chapter 21 interrupt ser vicing/exception proc essing function r01uh0165ej0700 rev.7.00 page 788 of 1113 sep 22, 2011 table 21-1. interrupt source list (2/3) type default priority name trigger generating unit exception code handler address interrupt control register 23 inttp3ov (/intua5r) note tmp3 overflow/ intua5 reception completion/ uarta5 reception error tmp3/ uarta5 01f0h 000001f0h tp3ovic/ ua5ric 24 inttp3cc0 tmp3 capture 0/compare 0 match tmp3 0200h 00000200h tp3/ccic0 25 inttp3cc1 (/intua5t) note tmp3 capture 1/compare 1 match/ intua5 successive transmission enable tmp3/ uarta5 0210h 00000210h tp3ccic1/ ua5tic 26 inttp4ov tmp4 overflow tmp4 0220h 00000220h tp4ovic 27 inttp4cc0 tmp4 capture 0/compare 0 match tmp4 0230h 00000230h tp4ccic0 28 inttp4cc1 tmp4 capture 1/compare 1 match tmp4 0240h 00000240h tp4ccic1 29 inttp5ov tmp5 overflow tmp5 0250h 00000250h tp5ovic 30 inttp5cc0 tmp5 capture 0/compare 0 match tmp5 0260h 00000260h tp5ccic0 31 inttp5cc1 tmp5 capture 1/compare 1 match tmp5 0270h 00000270h tp5ccic1 32 inttm0eq0 tmm0 compare match tmm0 0280h 00000280h tm0eqic0 33 intcb0r/ intiic1 csib0 reception completion/ csib0 reception error/ iic1 transfer completion csib0/ iic1 0290h 00000290h cb0ric/ iicic1 34 intcb0t csib0 successive transmission write enable csib0 02a0h 000002a0h cb0tic 35 intcb1r csib1 reception completion/ csib1 reception error csib1 02b0h 000002b0h cb1ric 36 intcb1t csib1 successive transmission write enable csib1 02c0h 000002c0h cb1tic 37 intcb2r csib2 reception completion/ csib2 reception error csib2 02d0h 000002d0h cb2ric 38 intcb2t csib2 successive transmission write enable csib2 02e0h 000002e0h cb2tic 39 intcb3r csib3 reception completion/ csib3 reception error csib3 02f0h 000002f0h cb3ric 40 intcb3t csib3 successive transmission write enable csib3 0300h 00000300h cb3tic 41 intua0r/ intcb4r uarta0 reception completion/ uarta0 reception error/ csib4 reception completion/ csib4 reception error uarta0/ csib4 0310h 00000310h ua0ric/ cb4ric 42 intua0t/ intcb4t uarta0 successive transmission enable/csib4 successive transmission write enable uarta0/ csib4 0320h 00000320h ua0tic/ cb4tic 43 intua1r/ intiic2 uarta1 reception completion/ uarta1 reception error/ iic2 transfer completion uarta1/ iic2 0330h 00000330h ua1ric/ iicic2 44 intua1t uarta1 successive transmission enable uarta1 0340h 00000340h ua1tic maskable 45 intua2r/ intiic0 uarta2 reception completion/ uarta2 reception error/ iic0 transfer completion uarta2/ iic0 0350h 00000350h ua2ric/ iicic0 note pd70f3792, 70f3793, 70f3841, 70f3842 only
v850es/jg3-l chapter 21 interrupt ser vicing/exception proc essing function r01uh0165ej0700 rev.7.00 page 789 of 1113 sep 22, 2011 table 21-1. interrupt source list (3/3) type default priority name trigger generating unit exception code handler address interrupt control register 46 intua2t uarta2 successive transmission enable uarta2 0360h 00000360h ua2tic 47 intad a/d conversion completion a/d 0370h 00000370h adic 48 intdma0 dma0 transfer completion dma 0380h 00000380h dmaic0 49 intdma1 dma1 transfer completion dma 0390h 00000390h dmaic1 50 intdma2 dma2 transfer completion dma 03a0h 000003a0h dmaic2 51 intdma3 dma3 transfer completion dma 03b0h 000003b0h dmaic3 52 intkr key return interrupt kr 03c0h 000003c0h kric 53 intwti (/intrtc2) note watch timer interval/ rtc interval signal wt/ rtc 03d0h 000003d0h wtiic/ rtc2ic 54 intwt (/intrtc0) note watch timer reference time/ rtc constant cycle signal wt/ rtc 03e0h 000003e0h wtic/ rtc0ic 55 intrtc1 note rtc alarm match rtc 03f0h 000003f0h rtc1ic 56 intua3r note uarta3 reception completion/ uarta3 reception error uarta3 0400h 00000400h ua3ric 57 intua3t note uarta3 successive transmission enable uarta3 0410h 00000410h ua3tic 58 intua4r note uarta4 reception completion/ uarta4 reception error uarta4 0420h 00000420h ua4ric 59 intua4t note uarta4 successive transmission enable uarta4 0430h 00000430h ua4tic 60 intuc0r note uartc0 reception completion/ uartc0 reception error uartc0 0440h 00000440h uc0ric maskable 61 intuc0t note uartc0 successive transmission enable uartc0 0450h 00000450h uc0tic note pd70f3792, 70f3793, 70f3841, 70f3842 only remarks 1. default priority: the priority order that is appli ed when multiple maskable interrupt requests having the same priority level occur simultaneously. smaller numbers have a higher priority, with 0 given the highest priority . the priority order of non-maskable interrupts is intwdt2 > nmi. 2. the execution address of the illegal instruction when an illegal opcode exception occurs is calculated by (restored pc ? 4).
v850es/jg3-l chapter 21 interrupt ser vicing/exception proc essing function r01uh0165ej0700 rev.7.00 page 790 of 1113 sep 22, 2011 21.2 non-maskable interrupts a non-maskable interrupt request signal is acknowledged ev en when interrupts are disabled (di) by the cpu. a non-maskable interrupt is not subject to priority control and takes precedence over all the other interrupt request signals. this product has the following two non-maskable interrupt request signals. ? nmi pin input (nmi) ? non-maskable interrupt request signal generated by overflow of watchdog timer (intwdt2) the valid edge of the nmi pin can be se lected from four types: ?rising edge?, ?falling edge?, ?both edges?, and ?no edge detection?. "no edge detection" is selected by default. be sure to specify the valid edge. the non-maskable interrupt request sign al generated by overflow of watch dog timer 2 (intwdt2) functions when the wdtm2.wdm21 and wdtm2.wdm20 bits are set to ?01?. if two or more non-maskable interrupt request signals occur at the same time, the interrupt with the higher priority is serviced, as follows (the interrupt reques t signal with the lower priority is ignored). intwdt2 > nmi if a new nmi or intwdt2 request signal is issued while a n on-maskable interrupt is being serviced, it is serviced as follows. (1) if new nmi request signal is issued wh ile non-maskable interrupt is being serviced the new nmi request signal is held pending, regardless of the value of the psw.np bit. the pending nmi request signal is acknowledged after the non-maskable interrupt currently under execution has been serviced (after the reti instruction has been executed). (2) if new intwdt2 request signal is issued while non-maskable interrupt is being serviced if the np bit is set (1) while a non-maskable interrupt is being serviced, the new intwdt2 request signal is held pending. the pending intwdt2 request signal is acknowledged after the non-maskable interrupt currently under execution has been serviced (a fter the reti instruction has been executed). if the np bit is cleared (0) while a non-maskable interrupt is being serviced, the newly generated intwdt2 request signal is acknowledged (the current non-maskable interrupt servicing is stopped). caution for details about the non-maskable interrupt servicing requested by the intwdt2 signal, see 21.2.2 (2) from intwdt2 signal. figure 21-1. non-maskable interrupt requ est signal acknowledgment operation (1/2) (a) nmi and intwdt2 request signa ls generated at the same time main routine system reset note nmi and intwd t2 requests (generated simultaneously) intwd t2 servicing note execute the initialization rout ine to restart the processing.
v850es/jg3-l chapter 21 interrupt ser vicing/exception proc essing function r01uh0165ej0700 rev.7.00 page 791 of 1113 sep 22, 2011 figure 21-1. non-maskable interrupt requ est signal acknowledgment operation (2/2) (b) non-maskable interrupt request signal generated during non-maskable interrupt servicing non-maskable interrupt being serviced non-maskable interrupt request signal generated during non-maskable interrupt servicing nmi intwdt2 nmi ? nmi request generated during nmi servicing ? intwdt2 request generated during nmi servicing (np bit = 1 retained before intwdt2 request) main routine nmi request nmi servicing (held pending) servicing of pending nmi nmi request main routine system reset note nmi request nmi servicing (held pending) intwdt2 servicing intwdt2 request ? intwdt2 request generated during nmi servicing (np bit = 0 set before intwdt2 request) main routine system reset note nmi request nmi servicing intwdt2 servicing intwdt2 request np = 0 ? intwdt2 request generated during nmi servicing (np = 0 set after intwdt2 request) main routine system reset note nmi request nmi servicing intwdt2 servicing np = 0 ? intwdt2 request generated during intwdt2 servicing main routine system reset note intwdt2 request intwdt2 servicing (invalid) ? nmi request generated during intwdt2 servicing intwdt2 main routine system reset note intwdt2 request intwdt2 servicing (invalid) nmi request (held pending) intwdt2 request intwdt2 request note execute the initialization rout ine to restart the processing.
v850es/jg3-l chapter 21 interrupt ser vicing/exception proc essing function r01uh0165ej0700 rev.7.00 page 792 of 1113 sep 22, 2011 21.2.1 operation if a non-maskable interrupt request signal is generated, t he cpu performs the following processing and transfers control to the handler routine. <1> saves the current pc to fepc. <2> saves the current psw to fepsw. <3> writes exception code (0010h, 0020h) to the higher halfword (fecc) of ecr. <4> sets the psw.np and psw.id bits to 1 and clears the psw.ep bit to 0. <5> sets the handler address (00000010h, 00000020h) corresponding to the non-maskable interrupt to the pc, and transfers control. the servicing of a non-maskable interrupt is shown below. figure 21-2. non-maskable interrupt servicing psw.np fepc fepsw ecr.fecc psw.np psw.ep psw.id pc pc psw 0010h, 0020h 1 0 1 00000010h, 00000020h 1 0 nmi input non-maskable interrupt request interrupt servicing interrupt request held pending intc acknowledged cpu processing
v850es/jg3-l chapter 21 interrupt ser vicing/exception proc essing function r01uh0165ej0700 rev.7.00 page 793 of 1113 sep 22, 2011 21.2.2 restoration (1) from nmi pin input execution is returned from nmi servic ing by using the reti instruction. when the reti instruction is execut ed, the cpu performs the following processing and transfers control to the address of the restored pc. <1> loads the saved pc and psw from fepc and fepsw , respectively, because the psw.ep bit is 0 and the psw.np bit is 1. <2> transfers control back to the address of the restored pc and psw. the processing of the reti in struction is shown below. figure 21-3. reti instruction processing reti instruction return to original processing pc psw corresponding bit of ispr note eipc eipsw 0 psw.ep 1 0 1 0 pc psw fepc fepsw psw.np pc psw fepc fepsw note for details about the ispr register, see 21.3.6 in-service priority register (ispr) . caution when the ep and np bits are changed by the ldsr instruction during non-maskable interrupt servicing, to restore the pc and psw correctly wh en returning by using the reti instruction, the ep bit must be cleared to 0 and the np bit must be set to 1 using the ldsr instruction immediately before the reti instruction. remark the solid line shows the cpu processing flow.
v850es/jg3-l chapter 21 interrupt ser vicing/exception proc essing function r01uh0165ej0700 rev.7.00 page 794 of 1113 sep 22, 2011 (2) from intwdt2 signal non-maskable interrupt servicing executed by intwdt2 cannot be returned from by using the reti instruction. to return from such servicing, execute the following software reset processing to initialize any interrupt servicing and branch to reset handler. in the software reset processing, however, the registers that can be set up only once immediately after a reset ends (such as the wdtm2 register) cannot be set up again. to reset these registers to their initial statuses, a hardware reset such as reset pin input is required. figure 21-4. software reset processing intwdt2 occurs. set to inhibit edge detection for nmi (intf0.intf02 = 0, intr0.intr02 = 0) reti reti execute loop processing 9 times other initialization processing branch to reset handler intwdt2 service routine software reset processing routine fepc, eipc the loop start address in software reset processing fepsw, eipsw value that sets np bit = 0, ep bit = 0 and id bit to 1 fepc software reset processing address fepsw value that sets np bit = 1, ep bit = 0 and id bit = 1 remark reti need to execute 10 times for clear two level non-maskable interrupts and 8 level maskable interrupts. 21.2.3 np flag the np flag is a status flag that indicates that a non-maskable interrupt is being serviced. this flag is set when a non-maskable interrupt request signal has been acknowledged, and masks non-maskable interrupt requests to prohibit multiple interrupts from being acknowledged. 0 np ep id sat cy ov s z psw no non-maskable interrupt servicing (initial value) non-maskable interrupt currently being serviced np 0 1 non-maskable interrupt servicing status
v850es/jg3-l chapter 21 interrupt ser vicing/exception proc essing function r01uh0165ej0700 rev.7.00 page 795 of 1113 sep 22, 2011 21.3 maskable interrupts maskable interrupt request signals can be masked by inte rrupt control registers. the v850es/jg3-l has 55 maskable interrupt sources. when an interrupt request signal has been acknowledged, interrupts are disabled (di) and subsequent maskable interrupt request signals are not acknowledged. when the ei instruction is executed in an interrupt service routine, in terrupts are enabled (ei), which enables acknowledgment of interrupt request signals having a priority higher than that of the interrupt request signal currently being serviced. interrupt request signals with the same priority level cannot be nested. for details about multiple interrupts, see 21.6 multiple interrupt servicing control . 21.3.1 operation if a maskable interrupt request signal is generated, the cpu performs the following processing and transfers control to the handler routine. <1> saves the current pc to eipc. <2> saves the current psw to eipsw. <3> writes an exception code to the lower halfword of ecr (eicc). <4> sets the psw.id bit to 1 and clears the psw.ep bit to 0. <5> loads the corresponding handler addr ess to the pc and transfers control. a maskable interrupt request signal masked by the interr upt controller (intc)(xxm k bit = 1) and a maskable interrupt request signal generated while another interrupt is being serviced (while the psw.np bit is 1 or the psw.id bit is 1) are held pending in the intc. the cause of being held pending and the workaround are described below. table 21-2. maskable interrupts held pending cause workaround xxmk bit = 1 unmask the signal (clear xxmk bit to 0). another interrupt havi ng higher priority is being held pending wait for the servicing of the interrupt to end. psw.np bit = 1 and psw.id bit = 1 set the np bit to 0 and the id bit to 1 by using the reti and ldsr instructions. remark for details about the xxmk bit, see 21.3.4 interrupt control register (xxicn) . figure 21-5 shows the servicing of maskable interrupts.
v850es/jg3-l chapter 21 interrupt ser vicing/exception proc essing function r01uh0165ej0700 rev.7.00 page 796 of 1113 sep 22, 2011 figure 21-5. maskable interrupt servicing int input xxif = 1 no xxmk = 0 no is the interrupt unmasked? yes yes no no no maskable interrupt request interrupt request held pending psw.np psw.id 1 1 interrupt request held pending 0 0 interrupt servicing cpu processing intc processing yes yes yes priority higher than that of interrupt currently being serviced? priority higher than that of other interrupt request? highest default priority among interrupt requests with the same priority? eipc eipsw ecr.eicc psw.ep psw.id corresponding bit of ispr note pc pc psw exception code 0 1 1 handler address interrupt requested? note for the ispr register, see 21.3.6 in-service priority register (ispr) .
v850es/jg3-l chapter 21 interrupt ser vicing/exception proc essing function r01uh0165ej0700 rev.7.00 page 797 of 1113 sep 22, 2011 21.3.2 restoration execution is returned from maskable interrupt servicing by using the reti instruction. when the reti instruction is executed , the cpu performs the following processing and transfers control to the address of the restored pc. <1> loads the saved pc and psw from eipc and eipsw , respectively, because the psw.ep bit is 0 and the psw.np bit is 0. <2> transfers control back to the address of the restored pc and psw. the processing of the reti instruction is shown below. figure 21-6. reti instruction processing reti instruction return to original processing pc psw corresponding bit of ispr note eipc eipsw 0 psw.ep 1 0 1 0 pc psw fepc fepsw psw.np pc psw fepc fepsw note for details about the ispr register, see 21.3.6 in-service priority register (ispr) . caution when the ep and np bits are changed by the ldsr instruction during maskable interrupt servicing, to restore the pc and psw correctly wh en returning by using the reti instruction, the ep bit and the np bit must be cleared to 0 using the ldsr instruction immediately before the reti instruction. remark the solid line shows the cpu processing flow.
v850es/jg3-l chapter 21 interrupt ser vicing/exception proc essing function r01uh0165ej0700 rev.7.00 page 798 of 1113 sep 22, 2011 21.3.3 priorities of maskable interrupts the intc can acknowledge an interrupt while servicing anot her. interrupts that occur at the same time are serviced according to their priority order. there are two types of priority level control: control based on the programmabl e priority levels that are specified by the interrupt priority level specification bit (xxprn) of the interrupt control register (xxicn), and control based on the default priority levels. programmable priority contro l classifies interrupt request signals into eight levels according to the setting of the xxprn flag. when multiple interrupts having the same priority level specified by the xxprn bit occur at the same time, the interrupts are serv iced according to the priority levels assigned to the corresponding interrupt requests (default prio rity level) beforehand. for details, see table 21-1 interrupt source list . for details about multiple interrupts, see 21.6 multiple interrupt servicing control . remark xx: identification name of each peripheral unit (see table 21-3 interrupt control registers (xxicn) ) n: peripheral unit number (see table 21-3 interrupt c ontrol registers (xxicn) ).
v850es/jg3-l chapter 21 interrupt ser vicing/exception proc essing function r01uh0165ej0700 rev.7.00 page 799 of 1113 sep 22, 2011 figure 21-7. example of processing in which a nother interrupt request signal is issued while an interrupt is being serviced (1/2) main routine ei ei interrupt request a (level 3) servicing of a servicing of b servicing of c interrupt request c (level 3) servicing of d servicing of e ei interrupt request e (level 2) servicing of f ei servicing of g interrupt request g (level 1) interrupt request h (level 1) servicing of h interrupt request b is acknowledged because the priority of b is higher than that of a and interrupts are enabled. although the priority of interrupt request d is higher than that of c, d is held pending because interrupts are disabled. interrupt request f is held pending even if interrupts are enabled because its priority is lower than that of e. interrupt request h is held pending even if interrupts are enabled because its priority is the same as that of g. interrupt request b (level 2) interrupt request d (level 2) interrupt request f (level 3) caution to service multiple interrupts, the values of the eipc and eipsw registers must be saved before executing the ei instruction. when returning from multiple interrupt servicing, restore the values of eipc and eipsw after executing the di instruction. remarks 1. a to u in the figure are the temporary names of interrupt request signals shown for the sake of explanation. 2. the default priority in the figure indicates the re lative priority between two interrupt request signals.
v850es/jg3-l chapter 21 interrupt ser vicing/exception proc essing function r01uh0165ej0700 rev.7.00 page 800 of 1113 sep 22, 2011 figure 21-7. example of processing in which a nother interrupt request signal is issued while an interrupt is being serviced (2/2) main routine ei interrupt request i (level 2) servicing of i servicing of k interrupt request j (level 3) servicing of j interrupt request l (level 2) ei ei ei interrupt request o (level 3) interrupt request s (level 1) interrupt request k (level 1) servicing of l servicing of n servicing of m servicing of s servicing of u servicing of t interrupt request m (level 3) interrupt request n (level 1) servicing of o interrupt request p (level 2) interrupt request q (level 1) interrupt request r (level 0) interrupt request u (level 2) note 2 interrupt request t (level 2) note 1 servicing of p servicing of q servicing of r ei if levels 3 to 0 are acknowledged interrupt request j is held pending because its priority is lower than that of i. k that occurs after j is acknowledged because it has the higher priority. interrupt requests m and n are held pending because servicing of l is performed in the interrupt disabled status. pending interrupt requests are acknowledged after servicing of interrupt request l. at this time, interrupt request n is acknowledged first even though m has occurred first because the priority of n is higher than that of m. pending interrupt requests t and u are acknowledged after servicing of s. because the priorities of t and u are the same, u is acknowledged first because it has the higher default priority, regardless of the order in which the interrupt requests have been generated. notes 1. lower default priority 2. higher default priority caution to service multiple interrupts, the values of the eipc and eipsw registers must be saved before executing the ei instruction. when returning from multiple interrupt servicing, restore the values of eipc and eipsw after executing the di instruction.
v850es/jg3-l chapter 21 interrupt ser vicing/exception proc essing function r01uh0165ej0700 rev.7.00 page 801 of 1113 sep 22, 2011 figure 21-8. example of servicing inte rrupt requests generated simultaneously default priority a > b > c main routine ei interrupt request a (level 2) interrupt request b (level 1) note 1 interrupt request c (level 1) note 2 servicing of interrupt request b . . servicing of interrupt request c servicing of interrupt request a interrupt request b and c are acknowledged first according to their priorities. because the priorities of b and c are the same, b is acknowledged first according to the default priority. nmi request notes 1. higher default priority 2. lower default priority caution to service multiple interrupts, the values of the eipc and eipsw registers must be saved before executing the ei instruction. when returning from multiple interrupt servicing, restore the values of eipc and eipsw after executing the di instruction. remarks 1. a to c in the figure are the temporary names of interrupt request signals shown for the sake of explanation. 2. the default priority in the figure indicates the re lative priority between two interrupt request signals.
v850es/jg3-l chapter 21 interrupt ser vicing/exception proc essing function r01uh0165ej0700 rev.7.00 page 802 of 1113 sep 22, 2011 21.3.4 interrupt control register (xxicn) an xxicn register is assigned to each interrupt request si gnal (maskable interrupt) and sets the control conditions for each maskable interrupt request. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 47h. cautions 1. to mask interrupts, set up the imr regist er or use a bit manipula tion instruction. the priority levels must be sp ecified at a time when no interrupt will occur. 2. disable interrupts (di) before reading the xxicn.xxifn bit. if the xxifn bit is read while interrupts are enabled (ei), the correct value m ay not be read if acknowledging an interrupt and reading the bit conflict. xxifn interrupt request not issued interrupt request issued xxifn 0 1 interrupt request flag note xxicn xxmkn 0 0 0 xxprn2 xxprn1 xxprn0 interrupt servicing enabled interrupt servicing disabled (pending) xxmkn 0 1 interrupt mask flag specifies level 0 (highest). specifies level 1. specifies level 2. specifies level 3. specifies level 4. specifies level 5. specifies level 6. specifies level 7 (lowest). xxprn2 0 0 0 0 1 1 1 1 interrupt priority specification bit xxprn1 0 0 1 1 0 0 1 1 xxprn0 0 1 0 1 0 1 0 1 after reset: 47h r/w address: fffff110h to fffff17ch <6> <7> note the flag xxlfn is reset automatically by the hardwa re if an interrupt request signal is acknowledged. remark xx: identification name of each peripheral unit (see table 21-3 interrupt control registers (xxicn) ) n: peripheral unit number (see table 21-3 interrupt c ontrol registers (xxicn) ). the addresses and bits of the interrupt control registers are as follows.
v850es/jg3-l chapter 21 interrupt ser vicing/exception proc essing function r01uh0165ej0700 rev.7.00 page 803 of 1113 sep 22, 2011 table 21-3. interrupt control registers (xxicn) (1/2) bit address register <7> <6> 5 4 3 2 1 0 fffff110h lviic lviif lvimk 0 0 0 lvipr2 lvipr1 lvipr0 fffff112h pic0 pif0 pmk0 0 0 0 ppr02 ppr01 ppr00 fffff114h pic1 pif1 pmk1 0 0 0 ppr12 ppr11 ppr10 fffff116h pic2 pif2 pmk2 0 0 0 ppr22 ppr21 ppr20 fffff118h pic3 pif3 pmk3 0 0 0 ppr32 ppr31 ppr30 fffff11ah pic4 pif4 pmk4 0 0 0 ppr42 ppr41 ppr40 fffff11ch pic5 pif5 pmk5 0 0 0 ppr52 ppr51 ppr50 fffff11eh pic6 pif6 pmk6 0 0 0 ppr62 ppr61 ppr60 fffff120h pic7 pif7 pmk7 0 0 0 ppr72 ppr71 ppr70 fffff122h tq0ovic tq0ovif tq0ovmk 0 0 0 tq0ovpr2 tq0ovpr1 tq0ovpr0 fffff124h tq0ccic0 tq0ccif0 tq0ccmk0 0 0 0 tq0ccpr02 tq0ccpr01 tq0ccpr00 fffff126h tq0ccic1 tq0ccif1 tq0ccmk1 0 0 0 tq0ccpr12 tq0ccpr11 tq0ccpr10 fffff128h tq0ccic2 tq0ccif2 tq0ccmk2 0 0 0 tq0ccpr22 tq0ccpr21 tq0ccpr20 fffff12ah tq0ccic3 tq0ccif3 tq0ccmk3 0 0 0 tq0ccpr32 tq0ccpr31 tq0ccpr30 fffff12ch tp0ovic tp0ovif tp0ovmk 0 0 0 tp0ovpr2 tp0ovpr1 tp0ovpr0 fffff12eh tp0ccic0 tp0ccif0 tp0ccmk0 0 0 0 tp0ccpr02 tp0ccpr01 tp0ccpr00 fffff130h tp0ccic1 tp0ccif1 tp0ccmk1 0 0 0 tp0ccpr12 tp0ccpr11 tp0ccpr10 fffff132h tp1ovic tp1ovif tp1ovmk 0 0 0 tp1ovpr2 tp1ovpr1 tp1ovpr0 fffff134h tp1ccic0 tp1ccif0 tp1ccmk0 0 0 0 tp1ccpr02 tp1ccpr01 tp1ccpr00 fffff136h tp1ccic1 tp1ccif1 tp1ccmk1 0 0 0 tp1ccpr12 tp1ccpr11 tp1ccpr10 fffff138h tp2ovic tp2ovif tp2ovmk 0 0 0 tp2ovpr2 tp2ovpr1 tp2ovpr0 fffff13ah tp2ccic0 tp2ccif0 tp2ccmk0 0 0 0 tp2ccpr02 tp2ccpr01 tp2ccpr00 fffff13ch tp2ccic1 tp2ccif1 tp2ccmk1 0 0 0 tp2ccpr12 tp2ccpr11 tp2ccpr10 fffff13eh tp3ovic /ua5ric note tp3ovif /ua5rif note tp3ovmk /ua5rmk note 0 0 0 tp3ovpr2 /ua5rpr2 note tp3ovpr1 /ua5rpr1 note tp3ovpr0 /ua5rpr0 note fffff140h tp3ccic0 tp3ccif0 tp3ccmk0 0 0 0 tp3ccpr02 tp3ccpr01 tp3ccpr00 fffff142h tp3ccic1 /ua5tic note tp3ccif1 /ua5tif note tp3ccmk1 /ua5tmk note 0 0 0 tp3ccpr12 /ua5tpr2 note tp3ccpr11 /ua5tpr1 note tp3ccpr10 /ua5tpr0 note fffff144h tp4ovic tp4ovif tp4ovmk 0 0 0 tp4ovpr2 tp4ovpr1 tp4ovpr0 fffff146h tp4ccic0 tp4ccif0 tp4ccmk0 0 0 0 tp4ccpr02 tp4ccpr01 tp4ccpr00 fffff148h tp4ccic1 tp4ccif1 tp4ccmk1 0 0 0 tp4ccpr12 tp4ccpr11 tp4ccpr10 fffff14ah tp5ovic tp5ovif tp5ovmk 0 0 0 tp5ovpr2 tp5ovpr1 tp5ovpr0 fffff14ch tp5ccic0 tp5ccif0 tp5ccmk0 0 0 0 tp5ccpr02 tp5ccpr01 tp5ccpr00 fffff14eh tp5ccic1 tp5ccif1 tp5ccmk1 0 0 0 tp5ccpr12 tp5ccpr11 tp5ccpr10 fffff150h tm0eqic0 tm0eqif0 tm0eqmk0 0 0 0 tm0eqpr02 tm0eqpr01 tm0eqpr00 fffff152h cb0ric/ iicic1 cb0rif/ iicif1 cb0rmk/ iicmk1 0 0 0 cb0rpr2/ iicpr12 cb0rpr1/ iicpr11 cb0rpr0/ iicpr10 fffff154h cb0tic cb0tif cb0tmk 0 0 0 cb0tpr2 cb0tpr1 cb0tpr0 fffff156h cb1ric cb1rif cb1rmk 0 0 0 cb1rpr2 cb1rpr1 cb1rpr0 fffff158h cb1tic cb1tif cb1tmk 0 0 0 cb1tpr2 cb1tpr1 cb1tpr0 fffff15ah cb2ric cb2rif cb2rmk 0 0 0 cb2rpr2 cb2rpr1 cb2rpr0 fffff15ch cb2tic cb2tif cb2tmk 0 0 0 cb2tpr2 cb2tpr1 cb2tpr0 fffff15eh cb3ric cb3rif cb3rmk 0 0 0 cb3rpr2 cb3rpr1 cb3rpr0 note pd70f3792, 70f3793, 70f3841, 70f3842 only
v850es/jg3-l chapter 21 interrupt ser vicing/exception proc essing function r01uh0165ej0700 rev.7.00 page 804 of 1113 sep 22, 2011 table 21-3. interrupt control registers (xxicn) (2/2) bit address register <7> <6> 5 4 3 2 1 0 fffff160h cb3tic cb3tif cb3tmk 0 0 0 cb3tpr2 cb3tpr1 cb3tpr0 fffff162h ua0ric/ cb4ric ua0rif/ cb4rif ua0rmk/ cb4rmk 0 0 0 ua0rpr2/ cb4rpr2 ua0rpr1/ cb4rpr1 ua0rpr0/ cb4rpr0 fffff164h ua0tic/ cb4tic ua0tif/ cb4tif ua0tmk/ cb4tmk 0 0 0 ua0tpr2/ cb4tpr2 ua0tpr1/ cb4tpr1 ua0tpr0/ cb4tpr0 fffff166h ua1ric/ iicic2 ua1rif/ iicif2 ua1rmk/ iicmk2 0 0 0 ua1rpr2/ iicpr22 ua1rpr1/ iicpr21 ua1rpr0/ iicpr20 fffff168h ua1tic ua1tif ua1tmk 0 0 0 ua1tpr2 ua1tpr1 ua1tpr0 fffff16ah ua2ric/ iicic0 ua2rif/ iicif0 ua2rmk/ iicmk0 0 0 0 ua2rpr2/ iicpr02 ua2rpr1/ iicpr01 ua2rpr0/ iicpr00 fffff16ch ua2tic ua2tif ua2tmk 0 0 0 ua2tpr2 ua2tpr1 ua2tpr0 fffff16eh adic adif admk 0 0 0 adpr2 adpr1 adpr0 fffff170h dmaic0 dmaif0 dmamk0 0 0 0 dmapr02 dmapr01 dmapr00 fffff172h dmaic1 dmaif1 dmamk1 0 0 0 dmapr12 dmapr11 dmapr10 fffff174h dmaic2 dmaif2 dmamk2 0 0 0 dmapr22 dmapr21 dmapr20 fffff176h dmaic3 dmaif3 dmamk3 0 0 0 dmapr32 dmapr31 dmapr30 fffff178h kric krif krmk 0 0 0 krpr2 krpr1 krpr0 fffff17ah wtiic /rtc2ic note wtiif /rtc2if note wtimk /rtc2mk note 0 0 0 wtipr2 /rtc2ppr2 note wtipr1 /rtc2ppr1 note wtipr0 /rtc2ppr0 note fffff17ch wtic /rtc0ic note wtif /rtc0if note wtmk /rtc0mk note 0 0 0 wtpr2 /rtc0ppr2 note wtpr1 /rtc0ppr1 note wtpr0 /rtc0ppr0 note fffff17eh rtc1ic note rtc1if note rtc1mk note 0 0 0 rtc1ppr2 note rtc1ppr1 note rtc1ppr0 note fffff180h ua3ric note ua3rif note ua3rmk note 0 0 0 ua3rpr2 note ua3rpr1 note ua3rpro note fffff182h ua3tic note ua3tif note ua3tmk note 0 0 0 ua3tpr2 note ua3tpr1 note ua3tpr0 note fffff184h ua4ric note ua4rif note ua4rmk note 0 0 0 ua4rpr2 note ua4rpr1 note ua4rpr0 note fffff186h ua4tic note ua4tif note ua4tmk note 0 0 0 ua4tpr2 note ua4tpr1 note ua4tpr0 note fffff188h uc0ric note uc0rif note uc0rmk note 0 0 0 uc0rppr2 note uc0rppr1 note uc0rppr0 note fffff18ah uc0tic note uc0tif note uc0tmk note 0 0 0 uc0tppr2 note uc0tppr1 note uc0tppr20 note note pd70f3792, 70f3793, 70f3841, 70f3842 only 21.3.5 interrupt mask register s 0 to 3 (imr0 to imr3) the imr0 to imr3 registers specify masking of the maskable interrupts. the xxmkn bit of the imr0 to imr3 registers is equivalent to the xxicn.xxmkn bit. each imrm register can be read or written in 16-bit units (m = 0 to 3). if the higher 8 bits of each imrm r egister are used as an imrmh regist er and the lower 8 bits as an imrml register, these registers can be read or written in 8-bit or 1-bit units (m = 0 to 3). reset sets these registers to ffffh. caution the device file defines the xxicn.xxmkn bit as a reserved word. if a bit is manipulated using the name of xxmkn, the values of the xxicn register, instead of the imrm register, are rewritten (as a result, the values of the imrm register are also rewritten).
v850es/jg3-l chapter 21 interrupt ser vicing/exception proc essing function r01uh0165ej0700 rev.7.00 page 805 of 1113 sep 22, 2011 (1/2) (a) pd70f3737, 70f3738 tp0ccmk0 pmk6 imr0 (imr0h note ) imr0l tp0ovmk pmk5 tq0ccmk3 pmk4 tq0ccmk2 pmk3 tq0ccmk1 pmk2 tq0ccmk0 pmk1 tq0ovmk pmk0 pmk7 lvimk after reset: ffffh r/w address: imr0 fffff100h, imr0l fffff100h, imr0h fffff101h after reset: ffffh r/w address: imr1 fffff102h, imr1l fffff102h, imr1h fffff103h after reset: ffffh r/w address: imr2 fffff104h, imr2l fffff104h, imr2h fffff105h tp5ccmk1 tp3ovmk imr1 (imr1h note ) imr1l tp5ccmk0 tp2ccmk1 tp5ovmk tp2ccmk0 tp4ccmk1 tp2ovmk tp4ccmk0 tp1ccmk1 tp4ovmk tp1ccmk0 tp3ccmk1 tp1ovmk tp3ccmk0 tp0ccmk1 admk cb3rmk cb3tmk tm0eqmk0 xxmkn 0 1 interrupt servicing enabled interrupt servicing disabled imr2 (imr2h note ) imr2l ua2tmk cb2tmk cb2rmk ua1tmk cb1tmk cb1rmk cb0tmk ua0tmk/ cb4tmk ua2rmk/ iicmk0 ua0rmk/ cb4rmk cb0rmk/ iicmk1 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 1 imr3 imr3l 1 wtmk 1 wtimk 1 krmk 1 dmamk3 dmamk2 dmamk1 dmamk0 after reset: ffffh r/w address: imr3 fffff106h, imr3l fffff106h 8 1 9 1 10 1 11 12 13 14 15 1 2 3 4 5 6 7 1 0 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 8 9 10 11 12 13 setting of interrupt mask flag 14 15 1 2 3 4 5 6 7 0 ua1rmk/ iic2mk note to read or write bits 8 to 15 of the imr0 to imr2 r egisters in 8-bit or 1-bit units, specify them as bits 0 to 7 of imr0h to imr2h registers. caution set bits 7 to 15 of the imr3 register to 1. if the setting of these bits is changed, the operation is not guaranteed. remark xx: identification name of each peripheral unit (see table 21-3 interrupt control registers (xxicn) ). n: peripheral unit number (see table 21-3 interrupt c ontrol registers (xxicn) )
v850es/jg3-l chapter 21 interrupt ser vicing/exception proc essing function r01uh0165ej0700 rev.7.00 page 806 of 1113 sep 22, 2011 (2/2) (b) pd70f3792, 70f3793, 70f3841, 70f3842 tp0ccmk0 pmk6 imr0 (imr0h note ) imr0l tp0ovmk pmk5 tq0ccmk3 pmk4 tq0ccmk2 pmk3 tq0ccmk1 pmk2 tq0ccmk0 pmk1 tq0ovmk pmk0 pmk7 lvimk after reset: ffffh r/w address: imr0 fffff100h, imr0l fffff100h, imr0h fffff101h after reset: ffffh r/w address: imr1 fffff102h, imr1l fffff102h, imr1h fffff103h after reset: ffffh r/w address: imr2 fffff104h, imr2l fffff104h, imr2h fffff105h tp5ccmk1 imr1 (imr1h note ) imr1l tp5ccmk0 tp2ccmk1 tp5ovmk tp2ccmk0 tp4ccmk1 tp2ovmk tp4ccmk0 tp4ovmk tp1ccmk0 tp3ccmk0 tp0ccmk1 admk cb3rmk cb3tmk tm0eqmk0 xxmkn 0 1 interrupt servicing enabled interrupt servicing disabled imr2 (imr2h note ) imr2l ua2tmk cb2tmk cb2rmk ua1tmk cb1tmk cb1rmk cb0tmk ua0tmk/ cb4tmk ua2rmk/ iicmk0 tp3ovmk/ ua5rmk tp1ccmk1 tp1ovmk tp3ccmk1/ ua5tmk wtmk/ rtc0mk wtmk/ rtc2mk ua0rmk/ cb4rmk cb0rmk/ iicmk1 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 1 imr3 (imr3h note ) imr3l 1 uc0tmk uc0rmk krmk ua4tmk dmamk3 dmamk2 dmamk1 dmamk0 after reset: ffffh r/w address: imr3 fffff106h, imr3l fffff106h, imr3h fffff107h 8 ua3rmk 9 ua3tmk 10 ua4rmk 11 12 13 14 15 1 2 3 4 5 6 7 rtc1mk 0 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 8 9 10 11 12 13 setting of interrupt mask flag 14 15 1 2 3 4 5 6 7 0 ua1rmk/ iic2mk note to read or write bits 8 to 15 of the imr0 to imr3 r egisters in 8-bit or 1-bit units, specify them as bits 0 to 7 of imr0h to imr3h registers. caution set bits 14 and 15 of the imr3 register to 1. if the setting of these bits is changed, the operation is not guaranteed. remark xx: identification name of each peripheral unit (see table 21-3 interrupt control registers (xxicn) ). n: peripheral unit number (see table 21-3 interrupt c ontrol registers (xxicn) )
v850es/jg3-l chapter 21 interrupt ser vicing/exception proc essing function r01uh0165ej0700 rev.7.00 page 807 of 1113 sep 22, 2011 21.3.6 in-service priority register (ispr) the ispr register holds the priority level of the maskable interrupt currently acknowledged. when an interrupt request signal is acknowledged, the bit of this register corresponding to the pr iority level of that interrupt request signal is set to 1 and remains set while the interrupt is serviced. when the reti instruction is executed , the bit corresponding to the interrupt request signal having the highest priority is automatically reset to 0 by hardware. however, it is not reset to 0 when execution is returned from non-maskable interrupt servicing or exception processing. this register is read-only, in 8-bit or 1-bit units. reset sets this register to 00h. caution if an interrupt is acknowledged while the ispr register is being read in the interrupt enabled (ei) status, the value of the ispr register after the bits of the register have been set by acknowledging the interrupt may be read. to accurately read the value of the ispr register before an interrupt is acknowledged, read the register while interrupts are disabled (di). ispr7 interrupt request signal with priority n not acknowledged interrupt request signal with priority n acknowledged isprn 0 1 priority of interrupt currently acknowledged ispr ispr6 ispr5 ispr4 ispr3 ispr2 ispr1 ispr0 after reset: 00h r address: fffff1fah <7> <6> <5> <4> <3> <2> <1> <0> remark n = 0 to 7 (priority level)
v850es/jg3-l chapter 21 interrupt ser vicing/exception proc essing function r01uh0165ej0700 rev.7.00 page 808 of 1113 sep 22, 2011 21.3.7 id flag this flag stores information regarding enabling or disa bling maskable interrupt request signals. the interrupt disable flag (id) is assigned to the psw. reset sets this flag to 1 and the psw register to 00000020h. 0 np ep id sat cy ov s z psw maskable interrupt request signal acknowledgment enabled maskable interrupt request signal acknowledgment disabled id 0 1 specification of maskable interrupt servicing note after reset: 00000020h note interrupt disable flag (id) function this bit is set to 1 by the di instruction and cleared to 0 by the ei instruction. its value is also rewritten by the reti instruction, or by an ldsr inst ruction that writes data to the psw. non-maskable interrupt request signals and exceptions are acknowledged regardless of this flag. when a maskable interrupt request signal is acknowledged, t he id flag is automatically set to 1 by hardware. an interrupt request signal generated during the a cknowledgment disabled period (id flag = 1) is acknowledged when the xxicn.xxifn bit is se t to 1, and the id flag is cleared to 0. 21.3.8 watchdog timer mode register 2 (wdtm2) this register can be read or writt en in 8-bit units (for details, see chapter 12 watchdog timer 2 ). reset sets this register to 67h. 0 wdtm2 wdm21 wdm20 0 0 0 0 0 after reset: 67h r/w address: fffff6d0h stops operating non-maskable interrupt request mode reset mode (initial-value wdm21 0 0 1 wdm20 0 1 selection of watchdog timer operation mode
v850es/jg3-l chapter 21 interrupt ser vicing/exception proc essing function r01uh0165ej0700 rev.7.00 page 809 of 1113 sep 22, 2011 21.4 software exception a software exception occurs when the cpu executes the trap instruction, and can always be acknowledged. 21.4.1 operation if a software exception occurs, the cpu performs the follo wing processing and transfers control to the handler routine. <1> saves the current pc to eipc. <2> saves the current psw to eipsw. <3> writes an exception code to the lower 16 bits (eicc) of ecr (interrupt source). <4> sets the psw.ep and psw.id bits to 1. <5> sets the handler address (00000040h or 00000050h) for the software exception to the pc and transfers control. the processing of a software exception is shown below. figure 21-9. software exception processing trap instruction eipc eipsw ecr.eicc psw.ep psw.id pc pc psw exception code 1 1 handler address cpu processing exception processing note note trap instruction format: trap vector (t he vector is a value from 00h to 1fh.) the handler address is determined by t he trap instruction?s operand (vector). if the vector is 00h to 0fh, the handler address is 00000040h, and if the vector is 10h to 1fh, the handler address is 00000050h.
v850es/jg3-l chapter 21 interrupt ser vicing/exception proc essing function r01uh0165ej0700 rev.7.00 page 810 of 1113 sep 22, 2011 21.4.2 restoration execution is returned from software exception processing by the using reti instruction. when the reti instruction is executed , the cpu performs the following processing and transfers control to the address of the restored pc. <1> loads the saved pc and psw from eipc and eipsw, respectively, because the psw.ep bit is 1. <2> transfers control back to the address of the restored pc and psw. the processing of the reti instruction is shown below. figure 21-10. reti instruction processing reti instruction return to original processing pc psw corresponding bit of ispr note eipc eipsw 0 psw.ep 1 0 1 0 pc psw fepc fepsw psw.np pc psw eipc eipsw note for details about the ispr register, see 21.3.6 in-service priority register (ispr) . caution when the ep and np bits are changed by the ldsr instruction during the software exception processing, in order to restore the pc and psw correctly when returning by using the reti instruction, the ep bit must be set to 1 and the np bit must be cleared to 0 using the ldsr instruction immediately before the reti instruction. remark the solid line shows the cpu processing flow.
v850es/jg3-l chapter 21 interrupt ser vicing/exception proc essing function r01uh0165ej0700 rev.7.00 page 811 of 1113 sep 22, 2011 21.4.3 ep flag the ep flag is a status flag that indica tes that exception processing is in progress. this flag is set when an exception occurs. 0 np ep id sat cy ov s z psw exception processing not in progress (initial value). exception processing in progress. ep 0 1 exception processing status
v850es/jg3-l chapter 21 interrupt ser vicing/exception proc essing function r01uh0165ej0700 rev.7.00 page 812 of 1113 sep 22, 2011 21.5 exception trap an exception trap is an interrupt that is requested when t he illegal execution of an instruction takes place. in the v850es/jg3-l, an illegal opcode exception (ilgop: ill egal opcode trap) is used as an exception trap. 21.5.1 illegal opcode an illegal opcode is defined as an instruction with instru ction opcode (bits 10 to 5) = 111111b, sub-opcode (bits 26 to 23) = 0111b to 1111b, and sub-opcode (bit 16) = 0b. when such an instruction is executed, an exception trap occurs. 15 16 23 22 0 1 1 1 1 1 1 27 26 31 0 4 5 10 11 1 1 1 1 1 1 0 1 to : arbitrary caution illegal opcodes must not be used because instructions may be newly assigned to these opcodes in the future. (1) operation if an exception trap occurs, the cpu performs the followi ng processing and transfers control to the handler routine. <1> saves the current pc to dbpc. <2> saves the current psw to dbpsw. <3> sets the psw.np, psw.ep, and psw.id bits to 1. <4> sets the handler address (00000060h) for the exception trap to the pc and transfers control. the processing of an exception trap is shown below.
v850es/jg3-l chapter 21 interrupt ser vicing/exception proc essing function r01uh0165ej0700 rev.7.00 page 813 of 1113 sep 22, 2011 figure 21-11. exception trap processing exception trap (ilgop) occurs dbpc dbpsw psw.np psw.ep psw.id pc pc psw 1 1 1 00000060h exception processing cpu processing (2) restoration execution is returned from an exception trap by usi ng the dbret instruction. when the dbret instruction is executed, the cpu performs the following processing and transfers control to the address of the restored pc. <1> loads the saved pc and psw from dbpc and dbpsw. <2> transfers control back to the address of the restored pc and psw. cautions 1. dbpc and dbpsw can be accessed only during the interval be tween the execution of an illegal opcode and the dbret instruction. 2. if an illegal opcode is executed, specify the default settings or stop the subsequent processing. the processing for returning from an exception trap is shown below. figure 21-12. returning from exception trap dbret instruction pc psw dbpc dbpsw jump to address of restored pc
v850es/jg3-l chapter 21 interrupt ser vicing/exception proc essing function r01uh0165ej0700 rev.7.00 page 814 of 1113 sep 22, 2011 21.5.2 debug trap a debug trap is an exception that occurs when t he dbtrap instruction is executed and can always be acknowledged. (1) operation if a debug trap occurs, the cpu performs the following processing. <1> saves the current pc to dbpc. <2> saves the current psw to dbpsw. <3> sets the psw.np, psw.ep, and psw.id bits to 1. <4> sets the handler address (00000060h) for the debug trap to the pc and transfers control. caution the dbtrap instruction is intended for debugging and is basically used by the debug tool. if the application uses this instruction while it is being executed by the debug tool, a malfunction might occur. the processing of a debug trap is shown below. figure 21-13. debug trap processing dbtrap instruction dbpc dbpsw psw.np psw.ep psw.id pc pc psw 1 1 1 00000060h exception processing cpu processing
v850es/jg3-l chapter 21 interrupt ser vicing/exception proc essing function r01uh0165ej0700 rev.7.00 page 815 of 1113 sep 22, 2011 (2) restoration execution is returned from a debug trap by using the dbret instruction. when the dbret instruction is execut ed, the cpu performs the following processing and transfers control to the address of the restored pc. <1> loads the saved pc and psw from dbpc and dbpsw. <2> transfers control back to address of the restored pc and psw. caution dbpc and dbpsw can be accessed only during the interval between the execution of the dbtrap instruction and the dbret instruction. the processing for returning from a debug trap is shown below. figure 21-14. returning from debug trap dbret instruction pc psw dbpc dbpsw jump to address of restored pc
v850es/jg3-l chapter 21 interrupt ser vicing/exception proc essing function r01uh0165ej0700 rev.7.00 page 816 of 1113 sep 22, 2011 21.6 multiple interrupt servicing control in multiple interrupt servicing control, the servicing of an interrupt is stopped if an interrupt request signal that has a higher priority level is generated. the higher prio rity interrupt request signal is then acknowledged and the interrupt is serviced. if an interrupt request signal with a lower or equal priority level is generated while an interrupt is being serviced, the newly generated interrupt request signal will be held pending. multiple interrupt servicing control is performed when interrupts are enabled (psw.id bit = 0). even in an interrupt service routine, multiple inte rrupt control must be performed while inte rrupts are enabled (id bit = 0). if a maskable interrupt or software exception occurs in a maskabl e interrupt or software exception service program, eipc and eipsw must be saved. the following example shows the procedure for servicing multiple interrupts. (1) to acknowledge maskable interrupt re quest signals in a service program service program for maskable interrupt or exception ? ? ? eipc saved to memory or register ? eipsw saved to memory or register ? ei instruction (enables interrupt acknowledgment) ? ? acknowledges maskable interrupt ? ? ? di instruction (disables interrupt acknowledgment) ? saved value restored to eipsw ? saved value restored to eipc ? reti instruction
v850es/jg3-l chapter 21 interrupt ser vicing/exception proc essing function r01uh0165ej0700 rev.7.00 page 817 of 1113 sep 22, 2011 21.7 external interrupt request i nput pins (nmi, intp0 to intp7) 21.7.1 noise elimination (1) noise elimination for nmi pin the nmi pin has an internal noise eliminator that us es analog delay (several 10 ns ). therefore, a signal input to the nmi pin is not detected as an edge unless it maintains its input level for a certain period. the edge is detected only after a certain period has elapsed. the nmi pin is used for releasing the stop mode. in the stop mode, noise e limination using the system clock is not performed because the internal system clock is stopped. (2) noise elimination for intp0 to intp7 pins the intp0 to intp7 pins have an internal noise elimi nator that uses analog delay (several 10 ns). therefore, a signal input to each pin is not detected as an edge unless it ma intains its input level for a certain period. the edge is detected only after a certain period has elapsed. (3) noise elimination for intp3 pin the intp3 pin has an internal digital/analog noise elim inator, and digital or analog noise elimination can be selected by using the nfc.nfen bit (analog delay: several 10 ns). the sampling clock can be selected from f xx /64, f xx /128, f xx /256, f xx /512, f xx /1,024, or f xt by using the nfc.nfc2 to nfc.nfc0 bits. if the sampling clock is set to f xx /64, f xx /128, f xx /256, f xx /512, or f xx /1,024, the sampling clock stops in the idle or stop mode. it cannot therefore be used to release a standby mode. to release a standby mode, select f xt as the sampling clock or select the analog noise eliminator. 21.7.2 edge detection the valid edge of each of the nmi and intp0 to in tp7 pins can be selected from the following four. ? rising edge ? falling edge ? both rising and falling edges ? no edge detected caution the nmi pin alternately functions as the p02 pin, and functions as a normal port pin after being reset. to enable the nmi pin function, use the pmc0 register. the initial setting of the nmi pin is ?no edge detected?. select the nmi pin valid edge by using the intf0 and intr0 registers.
v850es/jg3-l chapter 21 interrupt ser vicing/exception proc essing function r01uh0165ej0700 rev.7.00 page 818 of 1113 sep 22, 2011 (1) external interrupt fallin g, rising edge specification register 0 (intf0, intr0) the intf0 and intr0 registers are 8-bit registers that specify det ection of the falling and rising edges of the nmi pin via bit 2 and the external interrupt pins (intp0 to intp3) via bits 3 to 6. these registers can be read or written in 8-bit or 1-bit units. reset sets these registers to 00h. caution when switching from the port function to the external interrupt function (alternate function), an edge might be detected. therefore, set the intf0n and intr0n bits to 00, and then specify the external interrupt function (pmc0.pmc0n bit = 1). when switching from the external interrupt function to the port function, an edge might be detected as well. therefore, set the intf0n and intr0n bits to 00, and then specify the port function (pmc0.pmc0n bit = 0). 0 intf0 intf06 intp3 intf05 intf04 intf03 intf02 0 0 after reset: 00h r/w address: intf0 fffffc00h, intr0 fffffc20h 0 intr0 intr06 intr05 intr04 intr03 intr02 0 0 intp2 intp1 intp0 nmi intp3 intp2 intp1 intp0 nmi remark for how to specify a valid edge, see table 21-4 . table 21-4. valid edge specification intf0n intr0n valid edge specification (n = 2 to 6) 0 0 no edge detected 0 1 rising edge 1 0 falling edge 1 1 both rising and falling edges caution be sure to clear the intf0n and intr0n bits to 00 when these registers are not used for the nmi or intp0 to intp3 pins. remark n = 2: control of nmi pin n = 3 to 6: control of intp0 to intp3 pins
v850es/jg3-l chapter 21 interrupt ser vicing/exception proc essing function r01uh0165ej0700 rev.7.00 page 819 of 1113 sep 22, 2011 (2) external interrupt fallin g, rising edge specification register 3 (intf3, intr3) the intf3 and intr3 registers are 8-bit registers that specify det ection of the falling and rising edges of the external interrupt pin (intp7). these registers can be read or written in 8-bit or 1-bit units. reset sets these registers to 00h. cautions 1. when switching from the port function to the external interrupt function (alternate function), an edge might be detected. the refore, set the intf31 and intr31 bits to 00, and then specify the external interr upt function (pmc3.pmc31 bit = 1). when switching from the external interrupt function to the port function, an edge might be detected as well. therefore, set the intf 31 and intr31 bits to 00, and then specify the port function (pmc3.pmc31 bit = 0). 2. the intp7 pin and rxda0 pin are alternat e-function pins. when using the pin as the rxda0 pin, disable edge detection for th e intp7 alternate-function pin (clear the intf3.intf31 bit and the inrt3.intr31 bit to 0) . when using the pin as the intp7 pin, stop uarta0 reception (clear the ua0ctl0.ua0rxe bit to 0). intf3 after reset: 00h r/w address: intf3 fffffc06h, intr3 fffffc26h 0 0 0 0 0 0 intf31 0 intr3 0 0 0 0 0 0 intr31 0 intp7 intp7 remark for how to specify a valid edge, see table 21-5 . table 21-5. valid edge specification intf31 intr31 valid edge specification 0 0 no edge detected 0 1 rising edge 1 0 falling edge 1 1 both rising and falling edges caution be sure to clear the intf31 and intr31 bits to 00 when these registers are not used for the intp7 pin.
v850es/jg3-l chapter 21 interrupt ser vicing/exception proc essing function r01uh0165ej0700 rev.7.00 page 820 of 1113 sep 22, 2011 (3) external interrupt fallin g, rising edge specification re gister 9h (intf9h, intr9h) the intf9h and intr9h registers are 8-bit registers that specify detection of the falling and rising edges of the external interrupt pins (intp4 to intp6). these registers can be read or written in 8-bit or 1-bit units. reset sets these registers to 00h. caution when switching from the port function to th e external interrupt function (alternate function), an edge might be detected. therefore, set the intf9n and intr9n bits to 00, and then specify the external interrupt function (pmc9.pmc9n bit = 1). when switching from the external interrupt function to the port function, an edge might be detected as well. therefore, set the intf9n and intr9n bits to 00, and then specify the port function (pmc9.pmc9n bit = 0). intf9h after reset: 00h r/w address: intf9h fffffc13h, intr9h fffffc33h intf915 intf914 intf913 0 0 0 0 0 8 9 10 11 12 13 14 15 intr9h intr915 intr914 intr913 0 0 0 0 0 8 9 10 11 12 13 14 15 intp6 intp5 intp4 intp6 intp5 intp4 remark for how to specify a valid edge, see table 21-6 . table 21-6. valid edge specification intf9n intr9n valid edge specification (n = 13 to 15) 0 0 no edge detected 0 1 rising edge 1 0 falling edge 1 1 both rising and falling edges caution be sure to clear the intf9n and intr9n bits to 00 when these registers are not used for the intp4 to intp6 pins. remark n = 13 to 15: control of intp4 to intp6 pins
v850es/jg3-l chapter 21 interrupt ser vicing/exception proc essing function r01uh0165ej0700 rev.7.00 page 821 of 1113 sep 22, 2011 (4) noise elimination control register (nfc) digital noise elimination can be selected for the intp3 pi n. the noise elimination settings are specified by using the nfc register. when digital noise elimination is selected, the samp ling clock for digital sampling can be selected from f xx /64, f xx /128, f xx /256, f xx /512, f xx /1,024, or f xt . sampling is performed three times. even when digital noise elimination is selected, using f xt as the sampling clock makes it possible to use the intp3 interrupt request signal to release the idle1, idle2, and stop modes. this register can be read or written in 8-bit units. reset sets this register to 00h. caution after the sampling clock has been changed, it takes 3 sampling clock cycles to initialize the digital noise eliminator. therefore, if an intp3 valid edge is input within these 3 sampling clock cycles after the sampling clock has been changed, an interrupt request signal may be generated. therefore, be careful about the following points when using the interrupt and dma functions. ? when using the interrupt function, after the 3 sampling clock cycles have elapsed, enable interrupts after the interrupt request flag (pic3.pif3 bit) has been cleared. ? when using the dma function (started by intp3), enable dma after 3 sampling clock cycles have elapsed. nfen nfc 0 0 0 0 nfc2 nfc1 nfc0 f xx /64 f xx /128 f xx /256 f xx /512 f xx /1,024 f xt (subclock) nfc2 0 0 0 0 1 1 digital sampling clock setting prohibited nfc1 0 0 1 1 0 0 nfc0 0 1 0 1 0 1 after reset: 00h r/w address: fffff318h analog noise elimination (60 ns (typ.)) digital noise elimination nfen 0 1 settings of intp3 pin noise elimination other than above remarks 1. since sampling is performed three times, the reli ably eliminated noise width is 2 sampling clock cycles. 2. in the case of noise with a wi dth smaller than 2 sampling clock cycles, an interrupt request signal is generated if noise synchronized with the sampling clock is input.
v850es/jg3-l chapter 21 interrupt ser vicing/exception proc essing function r01uh0165ej0700 rev.7.00 page 822 of 1113 sep 22, 2011 an example of the timing of noise elimi nation performed by the timer t input pi n digital filter is shown figure 21-15. figure 21-15. example of digi tal noise elimination timing noise elimination clock input signal internal signal 3 clocks sampling 3 times 3 clocks 1 clock 1 clock 2 clocks 2 clocks sampling 3 times remark if the noise elimination clock cycle is sampled twic e or less while the intp3 input signal is high level (or low level), the input signal is judged as noise and eliminated. if the noise elimination clock cycle is sampled three times or more, the edge of the signal is det ected as a valid input.
v850es/jg3-l chapter 21 interrupt ser vicing/exception proc essing function r01uh0165ej0700 rev.7.00 page 823 of 1113 sep 22, 2011 21.8 interrupt response time of cpu except for the following cases, the in terrupt response time of the cpu is at least 4 clock cycles. to input interrupt request signals successively, input the next inte rrupt request signal at least 5 clock cycles after the preceding interrupt. ? in idle1/idle2/stop mode ? when the external bus is accessed ? when interrupt request non-sample instructions are successively executed (see 21.9 periods in which interrupts are not acknowledged by cpu .) ? when an interrupt control register is accessed figure 21-16. pipeline operation when interr upt request signal is acknowledged (outline) (1) minimum interrupt response time if id ex internal clock instruction 1 instruction 2 interrupt acknowledgment operation instruction (first instruction of interrupt service routine) interrupt request if id ex mem wb ifx idx int1 int2 int3 int4 4 system clock cycles (2) maximum interrupt response time if id ex internal clock instruction 1 instruction 2 interrupt acknowledgment operation instruction (first instruction of interrupt service routine) interrupt request if id ex mem mem mem wb ifx idx int1 int2 int3 int3 int3 int4 6 system clock cycles remark int1 to int4: interrupt acknowledgment processing ifx: invalid instruction fetch idx: invalid instruction decode interrupt response time (i nternal system clock cycles) internal interrupt external interrupt conditions minimum 4 4 + analog delay time maximum 6 6 + analog delay time the following cases are exceptions. ? in idle1/idle2/stop mode ? external bus access ? two or more interrupt request non-sample instructions are executed in succession ? access to peripheral i/o register
v850es/jg3-l chapter 21 interrupt ser vicing/exception proc essing function r01uh0165ej0700 rev.7.00 page 824 of 1113 sep 22, 2011 21.9 periods in which interrupts are not acknowledged by cpu an interrupt is acknowledged by the cpu while an inst ruction is being executed. however, no interrupt will be acknowledged between an interrupt request non-sample inst ruction and the next instruct ion (the interrupt is held pending). the interrupt request non-sample instructions are as follows. ? ei instruction ? di instruction ? ldsr reg2, 0x5 instruction (for psw) ? the store instruction for the prcmd register ? the store, set1, not1, or clr1 inst ructions for the following registers. ? interrupt-related registers: interrupt control register (xxicn), interr upt mask registers 0 to 3 (imr0 to imr3) ? power save control register (psc) ? on-chip debug mode register (ocdm) remarks 1. xx: identification name of each peripheral unit (see table 21-3 interrupt control registers (xxicn) ) n: peripheral unit number (see table 21-3 interrupt c ontrol registers (xxicn) ). 2. for details about the operati on of the pipeline, see the v850es architecture user's manual (u15943e) . 21.10 cautions 21.10.1 restored pc restored pc is the value of the pr ogram counter (pc) saved to eipc, fepc, or dbpc when interrupt servicing starts. if a non-maskable or maskable interrupt is ackn owledged during the execution of any of the following instructions, the execution of that instruction stops and resumes follo wing completion of interrupt servicing. ? load instructions (sld.b, sld.bu, sld.h, sld.hu, sld.w) ? divide instructions (div, divh, divu, divhu) ? prepare, dispose instructions (only when an inte rrupt occurs before the stack pointer is updated)
v850es/jg3-l chapter 22 key interrupt function r01uh0165ej0700 rev.7.00 page 825 of 1113 sep 22, 2011 chapter 22 key interrupt function 22.1 function a key interrupt request signal (intkr) can be generated by inputting a falling edge to the eight key input pins (kr0 to kr7) by setting the krm register. caution if any of the kr0 to kr7 pins is at low level, the intkr signal is not generated even if a falling edge is input to another pin. table 22-1. flag assignment flag pin description alternate function krm0 controls kr0 signal. p50 krm1 controls kr1 signal. p51 krm2 controls kr2 signal. p52 krm3 controls kr3 signal. p53 krm4 controls kr4 signal. p54 krm5 controls kr5 signal. p55 krm6 controls kr6 signal. p90 krm7 controls kr7 signal. p91 figure 22-1. key re turn block diagram intkr key return mode register (krm) krm7 krm6 krm5 krm4 krm3 krm2 krm1 krm0 kr7 kr6 kr5 kr4 kr3 kr2 kr1 kr0
v850es/jg3-l chapter 22 key interrupt function r01uh0165ej0700 rev.7.00 page 826 of 1113 sep 22, 2011 22.2 pin functions the key input pins that are used as key interrupt s are also used for the other functions shown in table 22-2 . to use these pins as key interrupts, this function must be specified by setting the relevant registers (see table 4-15 settings when pins are used for alternate functions ). table 22-2. pin functions pin no. port function key input function other functions 37 p50 kr0 p50/tiq01/toq01/rtp00 38 p51 kr1 p51/tiq02/toq02/rtp01 39 p52 kr2 p52/tiq03/toq03/rtp02/ddi 40 p53 kr3 p53/sib2/tiq00/toq00/rtp03/ddo 41 p54 kr4 p54/sob2/rtp04/dck 42 p55 kr5 p55/sckb2/rtp05/dms 61 p90 kr6 p90/a0/txda1/sda02 62 p91 kr7 p91/a1/rxda1/scl02 22.3 registers (1) key return mode register (krm) the krm register controls the kr0 to kr7 signals by using the krm0 to krm7 bits. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. krm7 do not detect key return signal detect key return signal krmn 0 1 control of key return mode krm krm6 krm5 krm4 krm3 krm2 krm1 krm0 after reset: 00h r/w address: fffff300h caution clear the krm register to 00h before rewriting it.
v850es/jg3-l chapter 22 key interrupt function r01uh0165ej0700 rev.7.00 page 827 of 1113 sep 22, 2011 22.4 cautions (1) if a low level is input to any of the kr0 to kr7 pins, the intkr signal is not generat ed even if the falling edge is input to another pin. (2) the rxda1 and kr7 pins must not be used at the same time. when using the rxda1 pin, do not use the kr7 pin. when using the kr7 pin, do not use the rxda1 pin (it is recommended to set the pfc91 bit to 1 and clear pfce91 bit to 0). (3) if the krm register is changed, an interrupt reques t signal (intkr) may be generated. to prevent this, change the krm register after disabling (di) or masking interrupts, then clear the interrupt request flag (kric.krif bit) to 0, and enable (ei) or unmask interrupts. (4) to use the key interrupt function, be sure to set the f unction of the port pin to ?key return pin? and then enable the key interrupt function by using the krm register. to s witch the pin function from key return pin to port pin, disable the key interrupt function by using the krm register and then set pin function to ?port pin?.
v850es/jg3-l chapter 23 standby function r01uh0165ej0700 rev.7.00 page 828 of 1113 sep 22, 2011 chapter 23 standby function 23.1 overview the power consumption of the system c an be effectively reduced by using t he standby modes in combination and selecting the appropriate mode for the application. the available sta ndby modes are listed in table 23-1. table 23-1. standby modes mode functional outline halt mode mode in which only the operating clock of the cpu is stopped. the total current consumption of the system can be reduced by using this mode in combination with the normal operation mode for intermittent operation. idle1 mode mode in which all the operations of the internal circuits except the oscillator, pll note1 , and flash memory are stopped. this mode can reduce the power consumption to a level lower than the halt mode because it stops the operation of the on-chip peripheral functions. idle2 mode mode in which all the operations of the internal circuits except the oscillator are stopped. this mode can reduce the power consumption to a level lower than the idle1 mode because it stops the operations of the on-chip peripheral functions, pll, and flash memory. stop mode mode in which all the operations of the internal circuits except the subclock oscillator are stopped. this mode can reduce the power consumption to a level lower than the idle2 mode. two modes are available: stop mode and low-voltage stop mode. the power consumption decreases further in the low-voltage stop mode because the voltage of the regulator is lowered. subclock operation mode mode in which the subclock is used as the internal system clock. this mode can reduce the power consumption to a level lower than the normal operation mode. two modes are available: subclock operation mode and low-voltage subclock operation mode. the power consumption decreases further in the low-voltage subclock operation mode because the voltage of the regulator is lowered. sub-idle mode mode in which all the operations of the internal circuits except the oscillator, pll operation note1 , and flash memory are stopped, in the subclock operation mode. this mode can reduce the power consumption to a level lower than the subclock operation mode. two modes are available: sub-idle mode and low-voltage sub-idle mode. the power consumption decreases further in the low-voltage sub-idle mode because the voltage of the regulator is lowered. rtc backup mode note2 mode in which the rtc continues counting on the subclock based the supply of backup voltage to the rv dd pin when v dd falls below the operating voltage while the subclock oscillator and rtc are separated from other internal circuits. the power consumption in this mode is even lower than in low-voltage stop mode. note that the data of the internal ram and the va lues of the cpu register s cannot be held in rtc backup mode, so when restoring the system from this mode, be sure to stop reset signal input after resupplying v dd . notes1. in the idle1 or sub-idle mode, the pll retains the operating status immediately before mode transition. if the pll operation is not necessary, stop the pll to lower the power consumptio n. in the idle2 mode, mode transition causes the pll to stop automatically. 2. pd70f3792, 70f3793, 70f 3841, 70f3842 only
v850es/jg3-l chapter 23 standby function r01uh0165ej0700 rev.7.00 page 829 of 1113 sep 22, 2011 figure 23-1. status transition reset subclock operation mode (f x operates, pll operates) subclock operation mode (f x stops, pll stops) sub-idle mode (f x operates, pll operates) sub-idle mode (f x stops, pll stops) stop mode (f x stops, pll stops) idle2 mode (f x operates, pll stops) idle1 mode (f x operates, pll operates) idle1 mode (f x operates, pll stops) halt mode (f x operates, pll stops) low-voltage subclock operation mode (f x stops, pll stops) low-voltage sub-idle mode (f x stops, pll stops) halt mode (f x operates, pll operates) normal operation mode oscillation stabilization wait note1 clock through mode (pll operates) clock through mode (pll stops) pll mode (pll operates) oscillation stabilization wait by software pll lockup time wait oscillation stabilization wait oscillation stabilization wait note1 low-voltage stop mode (f x stops, pll stops) oscillation stabilization wait note1 rtc backup mode note2, 3 notes1. if a wdt overflow occurs during an oscillation stabili zation time, the cpu operates on the internal oscillator clock. 2. the system will enter the rtc backu p mode while the interface of the rtc backup area is separated as long as the following two conditions are met: ? v dd is lower than the operating voltage. ? backup power is being supplied to rv dd . 3. pd70f3792, 70f3793, 70f 3841, 70f3842 only remark f x : main clock oscillation
v850es/jg3-l chapter 23 standby function r01uh0165ej0700 rev.7.00 page 830 of 1113 sep 22, 2011 23.2 registers (1) power save control register (psc) the psc register is an 8-bit register t hat controls the standby function. the stp bit of this register is used to specify the standby mode. this regist er is a special register that can only be written in a specific sequence (see 3.4.7 special registers ). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 psc nmi1m nmi0m intm 0 0 stp 0 7 <6> <5> <4> 3 2 <1> 0 after reset: 00h r/w address: fffff1feh standby mode release by intwdt2 signal enabled standby mode release by intwdt2 signal disabled nmi1m 0 1 standby mode release control upon occurrence of intwdt2 signal standby mode release by nmi pin input enabled standby mode release by nmi pin input disabled nmi0m 0 1 standby mode release control by nmi pin input standby mode release by maskable interrupt request signal enabled standby mode release by maskable interrupt request signal disabled intm 0 1 standby mode release control via maskable interrupt request signal normal operation mode standby mode stp 0 1 standby mode note setting note standby mode set by stp bit: idle1, idle2, stop, or sub-idle mode cautions 1. before setting one of the sta ndby modes (excluding th e halt mode), specify the mode by using the psmr.psm1 and psmr.psm0 bits and then set the stp bit. 2. the settings of the nmi1m, nmi0m, a nd intm bits are invalid when halt mode is released. 3. if the nmi1m, nmi0m, or intm bit is set to 1 at the same ti me the stp bit is set to 1, the setting of nmi1m, nmi0m, or in tm bit becomes invalid . if there is an unmasked interrupt request signal being held pending when the idle1/idle2/stop mode is set, set th e bit corresponding to the interrupt request signal (nmi1m, nmi0m, or intm) to 1, and then set the stp bit to 1.
v850es/jg3-l chapter 23 standby function r01uh0165ej0700 rev.7.00 page 831 of 1113 sep 22, 2011 (2) power save mode register (psmr) the psmr register is an 8-bit register that controls the operation status in the po wer save mode and the clock operation. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 idle1, sub-idle modes stop mode idle2, sub-idle modes stop mode psm1 0 0 1 1 specification of operation in software standby mode psmr 0 0 0 0 0 psm1 psm0 after reset: 00h r/w address: fffff820h psm0 0 1 0 1 < > < > cautions 1. be sure to cl ear bits 2 to 7 to ?0?. 2. the psm0 and psm1 bits are valid only when the psc.stp bit is 1. remark idle1: in this mode, all operati ons except the oscillat or operation and some other circuits (flash memory and pll) are stopped. after the idle1 mode is released, the norma l operation mode is restored without needing to secure the oscillation stabilization time, like the halt mode. idle2: in this mode, all operations ex cept the oscillator operation are stopped. after the idle2 mode is released, the nor mal operation mode is restored following the lapse of the setup time specified by the osts register (flash memory and pll). stop: in this mode, all operations except the subclock oscillator operation are stopped. after the stop mode is released, the nor mal operation mode is restored following the lapse of the oscillation stabilization time specified by the osts register. sub-idle: in this mode, all other operations are halted e xcept for the oscillator. after the idle mode has been released by the interrupt request signal, the subclock operation mode will be restored after 12 cycles of t he subclock have been secured.
v850es/jg3-l chapter 23 standby function r01uh0165ej0700 rev.7.00 page 832 of 1113 sep 22, 2011 (3) oscillation stabilization time select register (osts) the wait time until the oscillation stabilizes after the stop mode is re leased or the setup time until the internal flash memory stabilizes after the idle2 mode is released is controlled by the osts register. the osts register can be read or written 8-bit units. reset sets this register to 06h. 0 osts 0 0 0 0 osts2 osts1 osts0 osts2 0 0 0 0 1 1 1 1 selection of oscillation stabilization time/setup time note osts1 0 0 1 1 0 0 1 1 osts0 0 1 0 1 0 1 0 1 after reset: 06h r/w address: fffff6c0h 2 10 /f x 2 11 /f x 2 12 /f x 2 13 /f x 2 14 /f x 2 15 /f x 2 16 /f x 4 mhz 0.256 ms 0.512 ms 1.024 ms 2.048 ms 4.096 ms 8.192 ms 16.38 ms 5 mhz 0.205 ms 0.410 ms 0.819 ms 1.638 ms 3.277 ms 6.554 ms 13.107 ms f x setting prohibited note the oscillation stabilization time and setup time are required when the stop mode and idle2 mode are released, respectively. cautions 1. the wait time fo llowing the release of stop mode does not include the time until the clock oscillation starts (?a? in the figure below, regardless of whether the stop mode is released by a reset or an interrupt). a stop mode release voltage waveform of x1 pin v ss 2. be sure to clear bits 3 to 7 to ?0?. 3. the oscillation stabilization time foll owing reset release di ffers depending on the option byte. for details, see chapter 29 option byte. remark f x = main clock oscillation frequency
v850es/jg3-l chapter 23 standby function r01uh0165ej0700 rev.7.00 page 833 of 1113 sep 22, 2011 (4) regulator protection register (regpr) the regpr register is used to protec t the regulator output voltage level c ontrol register 0 (regovl0) so that illegal data is not written to regovl0. data cannot be written to the regovl0 register unless enabling data (c9h) is written to the regpr register. only two types of data, c9h (enabling data) and 00h (protection data), can be written to t he regpr register. writing any other value is prohibited. (if a value other than c9h or 00h is written to the regpr register, the written value is set to prohibit a write access to the regovl0 register, but the operation is not guaranteed.) this register can be read or written only in 8-bi t units (accessing it in 1-bit units is prohibited). reset sets this register to 00h (protection data status). pr7 pr6 pr5 pr4 pr3 pr2 pr1 pr0 regpr after reset: 00h r/w address: fffff331h ? protection data status: regpr = 00h in this status, the regovl0 regist er is protected from an illegal writ e access. in the protection data status, a value is not written to the regovl0 regi ster even if an attempt is made to write it, and the regovl0 register holds the previous value. be sure to set regpr to 00h, except when changing t he value of the regovl0 register, in order to avoid unexpected malfunction. ? enabling data status: regpr = c9h in this status, a write access to the regovl0 register is enabled. ? transition from normal mode low-voltage stop mode see 23.6.1 setting and operation status. ? transition of subclock operation mode low-voltage subclock operation mode see 23.7.1 setting and operation status. ? transition of subclock operation mode low-voltage sub-idle mode see 23.8.1 setting and operation status.
v850es/jg3-l chapter 23 standby function r01uh0165ej0700 rev.7.00 page 834 of 1113 sep 22, 2011 (5) regulator output voltage level control register 0 (regovl0) this register is used to select the low-voltage stop mode, low-voltage subclock operation mode, or low-voltage sub-idle mode. the power consumption c an be reduced by lowering the output voltage of the regulator. this register can be read or written only in 8-bi t units (accessing it in 1-bit units is prohibited). reset sets this register to 00h. this register must be always written in pairs wit h the regulator protection register (regpr). 0 stop mode low-voltage stop mode stpmd 0 1 output mode selection of regulator in stop mode 0 0 0 0 0 submd stpmd subclock operation mode/sub-idle mode low-voltage subclock operation mode/low-voltage sub-idle mode submd 0 1 output mode selection of regulator in subclock operation mode/sub-idle mode regovl0 after reset: 00h r/w address: fffff332h ? write operation of regovl0 register writing the regovl0 register is enabled only w hen c9h is written to the regpr register (see 23.2 (4) regulator protection register (regpr) ). this register can be set only to 00h, 01h, and 02h. setting 03h is prohibited. if 03h is set, the operation is not guaranteed. ? read operation of regovl0 register the default value of the regovl0 regi ster is 00h. after a value has been written to this register in the correct procedure note , the written value is read. the procedure fo r reading this register is not restricted. note ? transition from normal mode low-voltage stop mode see 23.6.1 setting and operation status. ? transition of subclock operation mode low-voltage subclock operation mode see 23.7.1 setting and operation status. ? transition of subclock operation mode low-voltage sub-idle mode see 23.8.1 setting and operation status. caution be sure to stop the main clock and pll when setting the low-voltage subclock mode and low-voltage sub-idle mode.
v850es/jg3-l chapter 23 standby function r01uh0165ej0700 rev.7.00 page 835 of 1113 sep 22, 2011 23.3 halt mode 23.3.1 setting and operation status the halt mode is set when a dedicated instruction (halt) is executed in the normal operation mode. in the halt mode, the clock oscillat or continues operating. only cloc k supply to the cpu is stopped; clock supply to the other on-chip pe ripheral functions continues. as a result, program execution is stopped, and the internal ram retains the contents before the halt mode was set. the on-chip peripheral functions t hat are independent of instru ction processing by the cpu continue operating. table 23-3 shows the operating status in the halt mode. the average current consumpt ion of the system can be reduced by usi ng the halt mode in combination with the normal operation mode. cautions 1. insert five or more nop in structions after the halt instruction. 2. if the halt instruction is executed while an unmasked interrupt request signal is being held pending, the status shifts to halt mode, but the halt mode is then released immediately by the pending interrupt request. 23.3.2 releasing halt mode the halt mode is released by a non-maskable interru pt request signal (nmi pin input, intwdt2 signal), unmasked external interrupt request signal (intp0 to intp 7 pin input), unmasked internal interrupt request signal from a peripheral function operable in the halt mode, or reset signal (reset by reset pin input, wdt2res signal, low-voltage detector (lvi), or clock monitor (clm)). after the halt mode has been released, the normal operation mode is restored. (1) releasing halt mode by non-maskable interrupt request si gnal or unmasked maskable interrupt request signal the halt mode is released by a non-maskable interr upt request signal or an unmasked maskable interrupt request signal, regardless of the prio rity of the interrupt request. if the halt mode is set in an interrupt servicing routine, however, an interrupt request that is issued later is serviced as follows. table 23-2. releasing halt mode and operation after release release source interrupt acknowledgment status status after release operation after release disabled (di) reset enabled (ei) ? normal reset operation disabled (di) non-maskable interrupt request signal (excluding multiple interrupts) enabled (ei) ? the interrupt request is acknowledged when the halt mode is released. disabled (di) ? the halt mode is released but the interrupt request that is the release source is not acknowledged. the interrupt request itself is retained. the processing that was being executed before shifting to the halt mode is executed. ? an interrupt request with a priority higher than that of the release source is being serviced. the halt mode is released but the interrupt request that is the release source is not acknowledged. the interrupt request itself is retained. the interrupt that was being serviced before shifting to t he halt mode is serviced. maskable interrupt request signal enabled (ei) ? an interrupt request with a priority lower than that of the release source is being serviced. the interrupt request is acknowledged when the halt mode is released.
v850es/jg3-l chapter 23 standby function r01uh0165ej0700 rev.7.00 page 836 of 1113 sep 22, 2011 table 23-3. operating status in halt mode setting of halt mode operating status item when subclock is not used when subclock is used lvi operable main clock oscillator oscillates subclock oscillator ? oscillates internal oscillator oscillation enabled pll operable cpu stops operation dma operable interrupt controller operable timer p (tmp0 to tmp5) operable timer q (tmq0) operable timer m (tmm0) operable when a clock other than f xt is selected as the count clock operable watch timer(/rtc) note operable when f x (divided brg) is selected as the count clock operable watchdog timer 2 operable when a clock other than f xt is selected as the count clock operable csib0 to csib4 operable i 2 c00 to i 2 c02 operable uarta0 to uarta5 operable serial interface uartc0 note operable a/d converter operable d/a converter operable real-time output function (rto) operable key interrupt function (kr) operable crc operation circuit operable (in the status in which data is not input to the crcin register to stop the cpu) external bus interface see 2.2 pin states . port function retains status before halt mode was set cpu register set internal ram retains status before halt mode was set note pd70f3792, 70f3793, 70f 3841, 70f3842 only
v850es/jg3-l chapter 23 standby function r01uh0165ej0700 rev.7.00 page 837 of 1113 sep 22, 2011 23.4 idle1 mode 23.4.1 setting and operation status the idle1 mode is set by clearing the psmr.psm1 and psm r.psm0 bits to 00 and setting the psc.stp bit to 1 in the normal operation mode. in the idle1 mode, the clock oscillato r, pll, and flash memory continue operating but clock supply to the cpu and other on-chip peripheral functions stops. as a result, program execution stops and the contents of the internal ram before the idle1 mode was set are retained. the cpu and other on-chip peripheral functi ons stop operating. however, the on-chip peripheral functions that can operate with the subclock or an extern al clock continue operating. table 23-5 shows the operating status in the idle1 mode. the idle1 mode can reduce the power consumption more t han the halt mode because it stops the operation of the on-chip peripheral functions. the main clock o scillator does not stop, so t he normal operation mode can be restored without waiting for the oscillation stabilization ti me after the idle1 mode has been released, in the same manner as when the halt mode is released. cautions 1. insert five or more nop instructions after the instruction th at stores data in the psc register to set the idle1 mode. 2. if the idle1 mode is set while an unmasked interrupt request signal is being held pending, the cpu does not shift to the idle1 m ode but executes the next instruction.
v850es/jg3-l chapter 23 standby function r01uh0165ej0700 rev.7.00 page 838 of 1113 sep 22, 2011 23.4.2 releasing idle1 mode the idle1 mode is released by a non-maskable interrupt request signal (nmi pin input, intwdt2 signal), unmasked external interrupt request signal (intp0 to intp 7 pin input), unmasked internal interrupt request signal from a peripheral function operable in the idle1 mode, or reset signal (reset by reset pin input, wdt2res signal, low-voltage detector (lvi), or clock monitor (clm)). after the idle1 mode has been released, the normal operation mode is restored. (1) releasing idle mode by n on-maskable interrupt request signa l or unmasked maskable interrupt request signal the idle mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the prio rity of the interrupt request. if the idle1 mode is set in an interrupt servicing routine, however, an interrupt request that is issued later is processed as follows. table 23-4. operation after releasing id le1 mode by interrupt request signal release source interrupt acknowledgment status status after release operation after release disabled (di) reset enabled (ei) ? normal reset operation disabled (di) non-maskable interrupt request signal (excluding multiple interrupts) enabled (ei) ? the interrupt request is acknowledged when the idle1 mode is released. disabled (di) ? the idle1 mode is released but the interrupt request that is the release source is not acknowledged. the interrupt request itself is retained. the processing that was being executed before shifting to the idle1 mode is executed. ? an interrupt request with a priority higher than that of the release source is being serviced. the idle1 mode is released but the interrupt request that is the release source is not acknowledged. the interrupt request itself is retained. the interrupt that was being serviced before shifting to t he idle1 mode is serviced. maskable interrupt request signal enabled (ei) ? an interrupt request with a priority lower than that of the release source is being serviced. the interrupt request is acknowledged when the idle1 mode is released. caution an interrupt request signal that is disabled by setting the psc.nmi2m, psc.nmi0m, and psc.intm bits to 1 (interrupt disabled) is invalid and cannot release the idle1 mode.
v850es/jg3-l chapter 23 standby function r01uh0165ej0700 rev.7.00 page 839 of 1113 sep 22, 2011 table 23-5. operating status in idle1 mode setting of idle1 mode operating status item when subclock is not used when subclock is used lvi operable main clock oscillator oscillates subclock oscillator ? oscillates internal oscillator oscillation enabled pll operable cpu stops operation dma stops operation interrupt controller stops operation (but standby mode release enabled) timer p (tmp0 to tmp5) stops operation timer q (tmq0) stops operation timer m (tmm0) operable when f r /8 is selected as the count clock operable when f r /8 or f xt is selected as the count clock watch timer(/rtc) note1 operable when f x (divided brg) is selected as the count clock operable watchdog timer 2 operable when f r /8 is selected as the count clock operable when f r /8 or f xt is selected as the count clock csib0 to csib4 operable when the sckbn input cloc k is selected as the count clock (n = 0 to 4) i 2 c00 to i 2 c02 stops operation uarta0 to uarta5 stops operation (but uarta0 is operable when the ascka0 input clock is selected) serial interface uartc0 note1 stops operation a/d converter holds operation (conversion result held) note2 d/a converter holds operation (output held note2 ) real-time output function (rto) stops operation (output held) key interrupt function (kr) operable crc operation circuit stops operation external bus interface see 2.2 pin states . port function retains status before idle1 mode was set cpu register set internal ram retains status before idle1 mode was set notes1. pd70f3792, 70f3793, 70f3841, 70f3842 only 2. to realize low power consumption, stop the a/d converter and d/a conv erter before shifting to the idle1 mode.
v850es/jg3-l chapter 23 standby function r01uh0165ej0700 rev.7.00 page 840 of 1113 sep 22, 2011 23.5 idle2 mode 23.5.1 setting and operation status the idle2 mode is set by setting the psmr.psm1 and ps mr.psm0 bits to 10 and setting the psc.stp bit to 1 in the normal operation mode. in the idle2 mode, the clock oscillator continues operation but clock supply to the cpu, pll, flash memory, and other on-chip peripheral functions stops. as a result, program execution stops and the contents of the internal ram before the idle2 mode was set are retained. the cpu, pll, and other on- chip peripheral functions stop operatin g. however, the on-chip peripheral functions that can operate with the subclock or an extern al clock continue operating. table 23-7 shows the operating status in the idle2 mode. the idle2 mode can reduce the power consumption more than the idle1 mode because it stops the operations of the on-chip peripheral functions, p ll, and flash memory. however, because the pll and flash memory are stopped, a setup time for the pll and flash memo ry is required when idle2 mode is released. cautions 1. insert five or more nop instructions after the instruction th at stores data in the psc register to set the idle2 mode. 2. if the idle2 mode is set while an unmasked interrupt request signal is being held pending, the cpu does not shift to the idle2 m ode but executes the next instruction.
v850es/jg3-l chapter 23 standby function r01uh0165ej0700 rev.7.00 page 841 of 1113 sep 22, 2011 23.5.2 releasing idle2 mode the idle2 mode is released by a non-maskable interrupt request signal (nmi pin input, intwdt2 signal), unmasked external interrupt request signal (intp0 to intp 7 pin input), unmasked internal interrupt request signal from the peripheral functions operable in the idle2 mode, or reset signal (reset by reset pin input, wdt2res signal, low-voltage detector (lvi), or clock monitor (clm)). the pll returns to the operat ing status it was in before the idle2 mode was set. after the idle2 mode has been released, the normal operation mode is restored. (1) releasing idle2 mode by non- maskable interrupt request signal or unmasked maskable interrupt request signal the idle mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the prio rity of the interrupt request. if the idle2 mode is set in an interrupt servicing routine, however, an interrupt request that is issued later is processed as follows. table 23-6. operation after releasing idle2 mode by interrupt request signal release source interrupt acknowledgment status status after release operation after release disabled (di) reset enabled (ei) ? normal reset operation disabled (di) non-maskable interrupt request signal (excluding multiple interrupts) enabled (ei) ? the idle2 mode is released, and after securing the specified setup time, the interrupt request is acknowledged. disabled (di) ? the idle2 mode is released but the interrupt request that is the release source is not acknowledged. the interrupt request itself is retained. after securing the specified setup time, the interrupt that was being serviced before shifting to the idle2 mode is serviced. ? an interrupt request with a priority higher than that of the release source is being serviced. the idle2 mode is released but the interrupt request that is the release source, is not acknowledged. the interrupt request itself is retained. after securing the specified setup time, the processing that was being executed before shifting to the idle2 mode is executed. maskable interrupt request signal enabled (ei) ? an interrupt request with a priority lower than that of the release source is being serviced. the idle2 mode is released, and after securing the specified setup time, the interrupt request is acknowledged. caution an interrupt request signal that is disabled by setting the psc.nmi2m, psc.nmi0m, and psc.intm bits to 1 (interrupt disabled) is invalid and cannot release the idle2 mode.
v850es/jg3-l chapter 23 standby function r01uh0165ej0700 rev.7.00 page 842 of 1113 sep 22, 2011 table 23-7. operating status in idle2 mode setting of idle2 mode operating status item when subclock is not used when subclock is used lvi operable main clock oscillator oscillates subclock oscillator ? oscillates internal oscillator oscillation enabled pll stops operation cpu stops operation dma stops operation interrupt controller stops operation (but standby mode release is possible) timer p (tmp0 to tmp5) stops operation timer q (tmq0) stops operation timer m (tmm0) operable when f r /8 is selected as the count clock operable when f r /8 or f xt is selected as the count clock watch timer(/rtc) note1 operable when f x (divided brg) is selected as the count clock operable watchdog timer 2 operable when f r /8 is selected as the count clock operable when f r /8 or f xt is selected as the count clock csib0 to csib4 operable when the sckbn input cloc k is selected as the count clock (n = 0 to 4) i 2 c00 to i 2 c02 stops operation uarta0 to uarta5 stops operation (but uarta0 is operable when the ascka0 input clock is selected) serial interface uartc0 note1 stops operation a/d converter holds operation (conversion result held) note2 d/a converter holds operation (output held note2 ) real-time output function (rto) stops operation (output held) key interrupt function (kr) operable crc operation circuit stops operation external bus interface see 2.2 pin states . port function retains status before idle2 mode was set cpu register set internal ram retains status before idle2 mode was set notes1. pd70f3792, 70f3793, 70f3 841, 70f3842 only 2. to realize low power consumption, stop the a/d and d/a converters before shifting to the idle2 mode.
v850es/jg3-l chapter 23 standby function r01uh0165ej0700 rev.7.00 page 843 of 1113 sep 22, 2011 23.5.3 securing setup time when releasing idle2 mode setting the idle2 mode stops the operation of blocks other than the main clock oscillator, so the setup time specified by the osts register for t he pll or the flash memory is automatic ally secured after the idle2 mode is released. (1) releasing idle2 mode by non-maskable interrupt request signa l or unmasked maskable interrupt request signal secure the specified setup time by setting the osts register. when the releasing source is generated, the dedicated in ternal timer starts counting according to the osts register setting. when it overflows, the normal operation mode is restored. oscillation waveform rom circuit stopped setup time count main clock idle mode status interrupt request (2) release by reset (reset pin input, wdt2r es generation) this operation is the same as that of a normal reset. the oscillation stabilization time differs de pending on the option byte. for details, see chapter 29 option byte .
v850es/jg3-l chapter 23 standby function r01uh0165ej0700 rev.7.00 page 844 of 1113 sep 22, 2011 23.6 stop mode/low-voltage stop mode 23.6.1 setting and operation status the stop mode is set by setting the psmr.psm1 and psmr .psm0 bits to 01 or 11 and setting the psc.stp bit to 1 in the normal operation mode. the low-volt age stop mode is set by setting the psmr.psm1 and psmr.psm0 bits to 01 or 11 and setting the psc.stp bit to 1 after setting the regovl0 register to 01h in normal operation mode. in the stop mode, the subclock oscillator continues oper ating but the main clock oscillator stops. clock supply to the cpu and the on-chip peripheral functions is stopped. as a result, program execution stops, and the contents of the internal ram before the stop mode was set are retained. clock supply to the cpu and the on-chip peri pheral functions is stopped, but the subclock oscillator continues operating. in the stop mode, csibn and uarta0, which can o perate on the external clock, also continue operating. in the low-volt age stop mode, however, stop supplying the external clock to csibn and uarta0 (n = 0 to 4) because these blocks cannot continue operating. table 23-8 shows the operating stat us in the stop mode and table 23-9 shows the operating status in the low-voltage stop mode. because the stop mode stops operation of the main clock oscillator, it reduc es the power consumption to a level lower than the idle2 mode. if the subclock oscillator, inte rnal oscillator, low-voltage detector (lvi), and external clock are not used, the power consumption can be minimized with only leakage current flowing. the power consumption decreases further in the low-voltage stop mode because the voltage of the regulator is lowered. be sure to set the low-voltage stop mode using the following procedure.
v850es/jg3-l chapter 23 standby function r01uh0165ej0700 rev.7.00 page 845 of 1113 sep 22, 2011 (1) procedure for switching from norma l mode to low-voltage stop mode specify the following settings in the normal operation m ode (while the main clock is operating). in addition, set up the osts register as necessary. <1> stop the functions whose operat ion is specified as stopped in table 23-9 operating status in low-voltage stop mode . be especially sure to stop the following, because they are signals from external sources. ? stop the sckbn input clock when the sckbn input clock to csibn is selected (n = 0 to 4). ? stop the ascka0 input clock when the ascka0 input clock to uarta0 is selected. <2> disable dma. <3> ? disable maskable interrupts by using the di instruction. ? disable the nmi interrupt (intf02 = 0, intr02 = 0). ? create a status in which the intwdt2 signal is not generated (create a status in which the intwdt2 signal is not generated immediately after watchdog timer 2 has been cleared). <4> write c9h (enabling data) to the regpr register. <5> write 01h to the regovl0 register. at this time, the output voltage of the regulator is at the normal level. <6> write 00h (protection data) to the regpr register. <7> as necessary, enable maskable interrupts, the nmi in terrupt, or the intwdt2 interrupt by using the ei instruction (restore the settings in <2> and <3> above). <8> set the stop mode. psmr.psm1, psmr.psm0 bits = 01 or 11 psc.stp bit = 1 in the stop mode, the output volt age of the regulator dr ops, decreasing the curr ent consumption to an extremely low level. be sure to observe the above sequence. note, however, that step <7> may be performed at any time as long as it is done after step <6>. (the setting in step <7> may be made without problem, even afte r the low-voltage stop mode has been released.) cautions 1. insert five or more nop instructions after the instruction th at stores data in the psc register to set the stop mode/low-voltage stop mode. 2. if the stop mode/low-voltage stop mode is set while an unmasked interrupt request signal is being held pending, the cpu does not shift to the stop mode/low-voltage stop mode but executes the next instruction.
v850es/jg3-l chapter 23 standby function r01uh0165ej0700 rev.7.00 page 846 of 1113 sep 22, 2011 table 23-8. operating status in stop mode setting of stop mode operating status item when subclock is not used when subclock is used lvi operable main clock oscillator stops oscillation subclock oscillator ? oscillates internal oscillator oscillation enabled pll stops operation cpu stops operation dma stops operation interrupt controller stops operation (but standby mode release is possible) timer p (tmp0 to tmp5) stops operation timer q (tmq0) stops operation timer m (tmm0) operable when f r /8 is selected as the count clock operable when f r /8 or f xt is selected as the count clock watch timer(/rtc) note1 stops operation operable when f xt is selected as the count clock watchdog timer 2 operable when f r /8 is selected as the count clock operable when f r /8 or f xt is selected as the count clock csib0 to csib4 operable when the sckbn input cloc k is selected as the count clock (n = 0 to 4) i 2 c00 to i 2 c02 stops operation uarta0 to uarta5 stops operation (but uarta0 is operable when the ascka0 input clock is selected) serial interface uartc0 note1 stops operation a/d converter stops operation (conversion result undefined) notes 2, 3 d/a converter stops operation notes 4, 5 (high impedance is output) real-time output function (rto) stops operation (output held) key interrupt function (kr) operable crc operation circuit stops operation external bus interface see 2.2 pin states . port function retains status before stop mode was set cpu register set internal ram retains status before stop mode was set notes1. pd70f3792, 70f3793, 70f3841, 70f3842 only 2. if the stop mode is set while the a/d converter is operating, the a/d conv erter is automatically stopped and starts operating again afte r the stop mode is released. however, in that case, the first a/d conversion result after the stop mode is rel eased is invalid. the a/d conversion result before the stop mode is set is also invalid. 3. even if the stop mode is set while the a/d converte r is operating, the power consumption is reduced equivalently to when the a/d converter is stopped before the stop mode is set. 4. if the stop mode is set while the d/a converter is operating, the d/a conv erter is automatically stopped and the pin status becom es high impedance. after the stop mode is released, d/a conversion resumes, the setting time elapses, and the status returns to the output level before the stop mode was set. 5. even if the stop mode is set while the d/a converte r is operating, the power consumption is reduced equivalently to when the d/a converter is stopped before the stop mode is set.
v850es/jg3-l chapter 23 standby function r01uh0165ej0700 rev.7.00 page 847 of 1113 sep 22, 2011 table 23-9. operating status in low-voltage stop mode operating status setting of low-voltage stop mode item when subclock is not used when subclock is used lvi operable main clock oscillator stops oscillation subclock oscillator ? oscillates internal oscillator oscillation enabled pll stops operation cpu stops operation dma stops operation interrupt controller stops operation (but standby mode release is possible) timer p (tmp0 to tmp5) stops operation timer q (tmq0) stops operation timer m (tmm0) operable when f r /8 is selected as the count clock operable when f r /8 or f xt is selected as the count clock watch timer(/rtc) note1 stops operation operable when f xt is selected as the count clock watchdog timer 2 operable when f r /8 is selected as the count clock operable when f r /8 or f xt is selected as the count clock csib0 to csib4 stops operation (when the sckbn input clock is selected as the count clock, be sure to stop the sckbn input clock (n = 0 to 4).) i 2 c00 to i 2 c02 stops operation uarta0 to uarta5 stops operation (when the ascka0 input clock to uarta0 is selected, be sure to stop the ascka0 input clock.) serial interface uartc0 note1 stops operation a/d converter stops operation (conversion result undefined) notes 2, 3 d/a converter stops operation notes 4, 5 (high impedance is output) real-time output function (rto) stops operation (output held) key interrupt function (kr) operable crc operation circuit stops operation external bus interface see 2.2 pin states . port function retains status before low-voltage stop mode was set cpu register set internal ram retains status before low-voltage stop mode was set notes 1. pd70f3792, 70f3793, 70f3841, 70f3842 only 2. if the low-voltage stop mode is set while the a/ d converter is operating, the a/d converter is automatically stopped and starts operating again after the low-voltage stop mode is released. however, in that case, the a/d conversion result s after the low-voltage stop mode is released are invalid. all the a/d conversi on results before the low-voltage stop mode is set are invalid. 3. even if the low-voltage stop mode is set while the a/d converter is operating, the power consumption is reduced equivalently to when the a/d converter is stopped before the low-vo ltage stop mode is set. 4. if the low-voltage stop mode is set while the d/ a converter is operating, the d/a converter is automatically stopped. after the low-voltage stop mode is releas ed, d/a conversion resumes, the setting time elapses, and the status returns to t he output level before the lo w-voltage stop mode was set. 5. even if the low-voltage stop mode is set while the d/a converter is operating, the power consumption is reduced equivalently to when the d/a converter is stopped before the low-vo ltage stop mode is set.
v850es/jg3-l chapter 23 standby function r01uh0165ej0700 rev.7.00 page 848 of 1113 sep 22, 2011 23.6.2 releasing stop mode /low-voltage stop mode the stop mode/low-voltage stop mode is released by a non-maskable interrupt request signal (nmi pin input, intwdt2 signal), unmasked external interrupt request si gnal (intp0 to intp7 pin input), unmasked internal interrupt request signal from the peripheral functions oper able in the stop mode/low- voltage stop mode, or reset signal (reset by reset pin input, wdt2res signal, or low-volt age detector (lvi)). after the stop mode/low-voltage stop mode has been released, the normal operation mode is restored after the oscillation stabilization time has been secured. for re-set after releasing the low-voltage stop mode, see 23.6.3 re-setting after release of low-voltage stop mode . (1) releasing stop mode by non-maskable interrupt request si gnal or unmasked maskable interrupt request signal the stop mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interr upt request. if the stop mode/low-voltage stop mode is set in an interrupt servicing routine, however, an interru pt request that is issued later is serviced as follows. table 23-10. operation after releasing stop mode/low -voltage stop mode by interrupt request signal release source interrupt acknowledgment status status after release operation after release disabled (di) reset enabled (ei) ? normal reset operation disabled (di) non-maskable interrupt request signal (excluding multiple interrupts) enabled (ei) ? the stop mode/low-voltage stop mode is released, and after securing the oscillation st abilization time, the interrupt request is acknowledged. disabled (di) ? the stop mode/low-voltage stop mode is released but the interrupt request that is the release source is not acknowledged. the interrupt request itself is retained. after securing the oscillation stabilization time, the processing that was being exec uted before shifting to the stop mode/low-voltage stop mode is executed. ? an interrupt request with a priority higher than that of the release source is being serviced. the stop mode/low-voltage stop mode is released but the interrupt request that is the release source is not acknowledged. the interrupt request itself is retained. after securing the oscillation stabilization time, the interrupt servicing that was being executed before shifting to the stop mode/low-voltage stop mode is executed. maskable interrupt request signal enabled (ei) ? an interrupt request with a priority lower than that of the release source is being serviced. the stop mode/low-voltage stop mode is released, and after securing the oscillation st abilization time, the interrupt request is acknowledged. caution an interrupt request signal that is disabled by setting the psc.nmi2m, psc.nmi0m, and psc.intm bits to 1 (interrupt disabled) is invalid and cannot release the stop mode/low-voltage stop mode.
v850es/jg3-l chapter 23 standby function r01uh0165ej0700 rev.7.00 page 849 of 1113 sep 22, 2011 23.6.3 re-setting after release of low-voltage stop mode (1) if low-voltage stop mode is released by interrupt the status after the low-voltage stop mode has been released is as follows. ? regulator: automatically re turns to the normal level. the oscillation stabilization time specified by the osts register is secured. ? regovl0 register = 01h (low-voltage stop mode): value described in 23.6.1 (1) <5> is retained. ? regpr register = 00h (protection data): value described in 23.6.1 (1) <6> is retained. (a) to continuously use the regovl0 register = 01h (low-voltage stop mode), the other registers do not have to be set again. (b) follow this procedure when returning the regovl0 register = 00h. <1> disable the dma. <2> ? disable the maskable interrupt by the di instruction. ? disable the nmi interrupt (intf02 = 0, intr02 = 0). ? create a status in which the intwdt2 signal is not generated (stop watchdog timer 2 or set a mode other than the intwdt2 mode. create a st atus in which the intwdt2 signal is not generated immediately after watchdog timer 2 has been cleared). <3> write c9h (enabling data) to the regpr register. <4> write 00h to the regovl0 register. <5> write 00h (protection data) to the regpr register. <6> as necessary, enable the maskable interrupt, nm i interrupt, or intwdt2 interrupt by enabling dma or the ei instruction (restore the settings <1> and <2> above). be sure to observe the above sequence. (2) if low-voltage stop mode is released by reset the cpu shifts to the normal operation mode immediat ely after the reset ends, and the regovl0 register is initialized to 00h and the regpr register to 00h (pro tection data). be sure to secure the oscillation stabilization time that follows immediately after a re set ends by setting the option byte. for details, see chapter 29 option byte . caution interrupt requests that are set to 1 (disabled) by the psc.nmi1m, psc.nmi0m, and psc.intm bits are invalid and cannot release the low-voltage stop mode.
v850es/jg3-l chapter 23 standby function r01uh0165ej0700 rev.7.00 page 850 of 1113 sep 22, 2011 23.6.4 securing oscillation stabilizati on time when releasing stop mode secure the oscillation stabilization time for the main cl ock oscillator after releasing the stop mode because the operation of the main clock oscillator stops after stop mode is set. (1) releasing stop m ode by non-maskable interrupt request signal or unmasked maskable interrupt request signal secure the oscillation stabilization time by setting the osts register. when the releasing source is generated, the dedicated in ternal timer starts counting according to the osts register setting. when it overflows, the normal operation mode is restored. oscillation waveform rom circuit stopped setup time count main clock stop status interrupt request (2) release by reset this operation is the same as that of a normal reset. the oscillation stabilization time differs de pending on the option byte. for details, see chapter 29 option byte .
v850es/jg3-l chapter 23 standby function r01uh0165ej0700 rev.7.00 page 851 of 1113 sep 22, 2011 23.7 subclock operation mode/low-vol tage subclock operation mode 23.7.1 setting and operation status the subclock operation mode is set by setting the p cc.ck3 bit to 1 in the normal operation mode. the low-voltage subclock operation mode is set by setting the regovl0 register to 02h in the subclock operation mode. when the subclock operation mode is set, the internal s ystem clock is changed from the main clock to the subclock. check whether the clock has been switched by using the pcc.cls bit. when the pcc.mck bit is set to 1, the operation of the main clock oscillator is stopped. as a result, the system operates only on the subclock. in the subclock operation mode, power consumption can be reduced to a level lower than in the normal operation mode because the subclock is used as the internal system cl ock. in addition, power consumption can be further reduced to the level of the stop mode by stopping the operat ion of the main clock oscillator. power consumption decreases further in the low-voltage subclock operation mode because the volt age of the regulator is lowered. when the main clock oscillator is stopped in the subclock operation mode, csibn and uarta0, which can operate on the external clock, also c ontinue operating. in the low-voltage subclock operation mode, however, stop supplying the external clock input to csibn and uarta0 be cause these blocks cannot continue operating (n = 0 to 4). cautions 1. when manipulating the ck3 bit, do not change the set values of the pcc.ck2 to pcc.ck0 bits (using a bit manipulation instruction to manipulate the bit is recommended). for details of the pcc register, see 6.3 (1) processor clock control register (pcc). 2. if the following condition s are not satisfied, change the ck2 to ck0 bits so that the conditions are satisfied and set the subclock operation mode. internal system clock (f clk ) > subclock (f xt = 32.768 khz) 4 remark internal system clock (f clk ): clock generated from main clock (f xx ) in accordance with the settings of the ck2 to ck0 bits be sure to set the low-voltage subclock oper ation mode using the following procedure.
v850es/jg3-l chapter 23 standby function r01uh0165ej0700 rev.7.00 page 852 of 1113 sep 22, 2011 (1) procedure for switching from subclock operation mode to low- voltage subclock operation mode make the following settings in the subclock operation mode. <1> stop the main clock and pll. <2> stop the functions whose operat ion is specified as stopped in table 23-14 operating status in low-voltage sub-idle mode . be especially sure to stop the following, because they are signals from external sources. ? stop the sckbn input clock when the sckbn input clock to csibn is selected (n = 0 to 4). ? stop the ascka0 input clock when the ascka0 input clock to uarta0 is selected. <3> disable dma (if dma is enabled). <4> ? disable maskable interrupts by using the di instruction. ? disable the nmi interrupt (intf02 = 0, intr02 = 0). ? create a status in which the intwdt2 signal is not generated (create a status in which the intwdt2 signal is not generated immediately after watchdog timer 2 has been cleared). <5> write c9h (enabling data) to the regpr register. <6> write 02h to the regovl0 register. at this time, the output voltage of the regulator is at the low level, decreasing power consumption to an extremely low level. <7> write 00h (protection data) to the regpr register. <8> as necessary, enable maskable interrupts, the nmi in terrupt, or the intwdt2 interrupt by using the ei instruction (restore the setting in <4> above). be sure to observe the above sequence. for the setting of the subclock operation mode, see 23.7.1 setting and operation status . table 23-11 shows the operating st atus in the subclock operation mo de and table 23-12 shows the operating status in the low-voltag e subclock operation mode.
v850es/jg3-l chapter 23 standby function r01uh0165ej0700 rev.7.00 page 853 of 1113 sep 22, 2011 table 23-11. operating status in subclock operation mode operating status setting of subclock operation mode item when main clock is oscillating when main clock is stopped lvi operable subclock oscillator oscillates internal oscillator oscillation enabled pll operable stops operation note1 cpu operable dma operable interrupt controller operable timer p (tmp0 to tmp5) operable stops operation timer q (tmq0) operable stops operation timer m (tmm0) operable operable when f r /8 or f xt is selected as the count clock watch timer(/rtc) note2 operable operable when f xt is selected as the count clock watchdog timer 2 operable operable when f r or f xt is selected as the count clock csib0 to csib4 operable operable when the sckbn input clock is selected as the count clock (n = 0 to 4) i 2 c00 to i 2 c02 operable stops operation uarta0 to uarta5 operable stops operation (but uarta0 is operable when the ascka0 input clock is selected) serial interface uartc0 note2 operable stops operation a/d converter operable stops operation d/a converter operable real-time output function (rto) oper able stops operation (output held) key interrupt function (kr) operable crc operation circuit operable external bus interface see 2.2 pin states . port function settable cpu register set internal ram settable notes 1. be sure to stop the pll (pllctl.pllon bit = 0) before stopping the main clock. 2. pd70f3792, 70f3793, 70f3841, 70f3842 only caution when the cpu is operating on the subclock and main clock oscilla tion is stopped, a register for which a wait has been specified must not be accessed. if a wait is generated, it can only be canceled by a reset (see 3.4.8 (2)).
v850es/jg3-l chapter 23 standby function r01uh0165ej0700 rev.7.00 page 854 of 1113 sep 22, 2011 table 23-12. operating status in low-voltage subclock operation mode operating status setting of low-voltage subclock operation mode item main clock is stopped (must be stopped) lvi operable subclock oscillator oscillates internal oscillator oscillation enabled pll stops operation note1 cpu operable dma stops operation (must stop) interrupt controller operable timer p (tmp0 to tmp5) stops operation timer q (tmq0) stops operation timer m (tmm0) operable when f r /8 or f xt is selected as the count clock watch timer(/rtc) note2 operable when f xt is selected as the count clock watchdog timer 2 operable when f r /8 or f xt is selected as the count clock csib0 to csib4 stops operation (when the sckbn input clock is selected as the count clock, be sure to stop the sckbn input clock (n = 0 to 4).) i 2 c00 to i 2 c02 stops operation uarta0 to uarta5 stops operation (when the ascka0 input clock to uarta0 is selected, be sure to stop the ascka0 input clock.) serial interface uartc0 note2 stops operation a/d converter stops operation d/a converter stops operation (must stop) real-time output function (rto) stops operation (output held) key interrupt function (kr) operable crc operation circuit stops operation (must stop) external bus interface see 2.2 pin states . port function settable cpu register set internal ram settable notes 1. be sure to stop the pll (pllctl.pllon bit = 0). 2. pd70f3792, 70f3793, 70f 3841, 70f3842 only caution when the cpu is operating on the subclock and main clock oscilla tion is stopped, a register for which a wait is specified must not be accessed. if a wait is generated, it can only be canceled by a reset (see 3.4.8 (2)).
v850es/jg3-l chapter 23 standby function r01uh0165ej0700 rev.7.00 page 855 of 1113 sep 22, 2011 23.7.2 releasing subc lock operation mode the subclock operation mode is released by a reset signal (reset by reset pin input, wdt2res signal, low-voltage detector (lvi), or clock monitor (clm)) when the ck3 bit is set to 0. if the main clock is stopped (mck bit = 1), set the mck bit to 1, secure the oscillation stabilization time of the main clock by software, and set the ck3 bit to 0. the normal operation mode is restored when the subclock operation mode is released. caution when manipulating the ck3 bit, do not change the set values of the ck2 to ck0 bits (using a bit manipulation instruction to manipulate the bit is recommended). for details of the pcc register, see 6.3 (1) processor clock control register (pcc). 23.7.3 releasing low-voltag e subclock operation mode in low-voltage subclock mode, the subclock operation mode is set by setting the regovl0 register to 00h. after that, transit to the normal mode according to 23.7.2 releasing subclock operation mode . be sure to follow this procedure to transit the mode from the lo w-voltage subclock operation mode to the subclock operation mode. (1) procedure for setting ?low-vol tage subclock ope ration mode? ?subclock operation mode? make the following settings in the low-voltage subclock operation mode. <1> ? disable the maskable interrupt by the di instruction. ? disable the nmi interrupt (intf02 = 0, intr02 = 0). ? create a status in which the intwdt2 signal is not generated (create a status in which the intwdt2 signal is not generated immediately after watchdog timer 2 has been cleared). <2> write c9h (enabling data) to the regpr register. <3> write 00h to the regovl0 register (transit to the subclock operation mode). <4> write 00h (protection data) to the regpr register. <5> wait for at least 800 s by software. <6> as necessary, enable the maskable interrupt, nmi inte rrupt, or intwdt2 interrupt by the ei instruction (restore the setting <1> above). <7> enable the dma if necessary. <8> start the functions to be used, from among thos e that have been stopped in steps <1> and <2> in section 23.7.1 (1) procedure for setting ?subclock operation mode? ?low-voltage subclock operation mode? . be sure to observe the above sequence. note, however, that <6>, <7>, and <8> may be performed at any time as long as it is done after <5>. (2) if low-voltage subclock operati on mode is released by reset when the low-voltage subclock operat ion mode is released by a reset signal (reset by reset pin input, wdt2res signal, low-voltage detector (l vi), or clock monitor (clm)), the cpu shifts to the normal operation mode immediately after the reset ends, and the regov l0 register is initialized to 00h and the regpr register to 00h (protection data). be sure to secure the oscillation stabilization time that follows immediately after a reset ends by setting the option byte. for details, see chapter 29 option byte .
v850es/jg3-l chapter 23 standby function r01uh0165ej0700 rev.7.00 page 856 of 1113 sep 22, 2011 23.8 sub-idle mode/low-voltage sub-idle mode 23.8.1 setting and operation status the sub-idle mode is set by setting the psmr.psm1 and psmr.psm0 bits to 00 or 10 and setting the psc.stp bit to 1 in the subclock operation mode. the low-volt age sub-idle mode is set by setting the psmr.psm1 and psmr.psm0 bits to 00 or 10 and setting the psc.stp bit to 1 after setting the regovl0 register to 02h in the subclock operation mode. in this mode, the clock oscillator continues operating but clock supply to the cpu, flash memory, and the other on-chip peripheral functions is stopped. as a result, program execution stops and the contents of the internal ram before the sub-idle mode was set are retained. the cpu and the other on-chip peripheral fu nctions are stopped. however, the on-chip peripheral functions that can operate with the subc lock or an external clock, continue operating. in the subclock operation mode, csibn and uarta0 that can operate with the external clock also continue operating. in the low-voltage subclock operation mode, however, stop supplying the exter nal clock input to csibn and uarta0 because these blocks cannot continue operating (n = 0 to 4). because the sub-idle mode stops operat ion of the cpu, flash memory, and ot her on-chip peripheral functions, it can reduce the power consumption more than the subclock operation mode. if the sub-idle mode is set after the main clock has bee n stopped, the current consum ption can be reduced to a level as low as that in the stop mode. the power consumpt ion decreases further in the low-voltage sub-idle mode because the voltage of t he regulator is lowered. table 23-13 shows the operating status in the sub-idle mode and table 23- 14 shows the operating status in the low-voltage sub-idle mode. be sure to set the low-voltage sub-idle mode in the following procedure. (1) procedure for setting ?subclock operation mode? ?low-voltage subc lock operation mode? ?low-voltage sub-idle mode? make the following settings in the subclock operation mode. <1> stop the main clock and pll. <2> stop the functions that ar e specified to be stopped in table 23-14 operating status in low-voltage sub-idle mode . be especially sure to stop the following functions, because they are signals from external sources. ? stop sckbn input clock when the sckbn input clock to csibn is selected (n = 0 to 4). ? stop ascka0 input clock when the ascka0 input clock to uarta0 is selected. <3> disable the dma operation (if the dma operation is enabled). <4> ? disable the maskable interrupt by the di instruction. ? disable the nmi interrupt (intf02 = 0, intr02 = 0). ? create a status in which the intwdt2 signal is not generated (set a status in which the intwdt2 signal is not generated immediately after watchdog timer 2 has been cleared). <5> write c9h (enabling data) to the regpr register. <6> write 02h to the regovl0 register. at this time, the output voltage of the regulator is at the low level, decreasing the power consumption to an extremely low level. <7> write 00h (protection data) to the regpr register. <8> as necessary, enable the maskable interrupt, nmi inte rrupt, or intwdt2 interrupt by the ei instruction (restore the settings in step <4>). <9> set the sub-idle mode. psmr.psm1, psmr.psm0 bits = 00 or 10 psc.stp bit = 1
v850es/jg3-l chapter 23 standby function r01uh0165ej0700 rev.7.00 page 857 of 1113 sep 22, 2011 be sure to observe the above sequence. for the setting of the subclock operation mode, see 23.7.1 setting and operation status . cautions 1. following the store instruction to the psc register for setting the sub-idle mode/low-voltage sub-idle mode, insert the five or more nop instructions. 2. if the sub-idle mode/low-voltage sub-id le mode is set while an unmasked interrupt request signal is being he ld pending, the cpu does not shift to the sub-idle mode/low-voltage sub-id le mode but executes th e next instruction. table 23-13. operating status in sub-idle mode setting of sub-idle mode operating status item when main clock is oscillating when main clock is stopped lvi operable subclock oscillator oscillates internal oscillator oscillation enabled pll operable stops operation note 1 cpu stops operation dma stops operation interrupt controller stops operation (but standby mode release is possible) timer p (tmp0 to tmp5) stops operation timer q (tmq0) stops operation timer m (tmm0) operable when f r /8 or f xt is selected as the count clock watch timer(/rtc) note2 operable operable when f xt is selected as the count clock watchdog timer 2 operable when f r /8 or f xt is selected as the count clock csib0 to csib4 operable when the sckbn input cloc k is selected as the count clock (n = 0 to 4) i 2 c00 to i 2 c02 stops operation uarta0 to uarta5 stops operation (but uarta0 is operable when the ascka0 input clock is selected) serial interface uartc0 note2 stops operation a/d converter holds operation (conversion result held) note 3 d/a converter holds operation (output held note 3 ) real-time output function (rto) stops operation (output held) key interrupt function (kr) operable crc operation circuit stops operation external bus interface see 2.2 pin states (same operation status as idle1 and idle2 modes). port function retains status before sub-idle mode was set cpu register set internal ram retains status before sub-idle mode was set notes 1. be sure to stop the pll (pllctl.pllon bit = 0) before stopping the main clock. 2. pd70f3792, 70f3793, 70f3841, 70f3842 only 3. to realize low power consumption, stop the a/d and d/ a converters before shifting to the sub-idle mode.
v850es/jg3-l chapter 23 standby function r01uh0165ej0700 rev.7.00 page 858 of 1113 sep 22, 2011 table 23-14. operating status in low-voltage sub-idle mode operating status setting of low-voltage sub-idle mode item main clock is stopped (must be stopped) lvi operable subclock oscillator oscillates internal oscillator oscillation enabled pll stops operation note1 cpu stops operation dma stops operation interrupt controller stops operation (but standby mode release is possible) timer p (tmp0 to tmp5) stops operation timer q (tmq0) stops operation timer m (tmm0) operable when f r /8 or f xt is selected as the count clock watch timer(/rtc) note2 operable when f xt is selected as the count clock watchdog timer 2 operable when f r /8 or f xt is selected as the count clock csib0 to csib4 stops operation (when the sckbn input clock is selected as the count clock, be sure to stop the sckbn input clock (n = 0 to 4).) i 2 c00 to i 2 c02 stops operation uarta0 to uarta5 stops operation (when the ascka0 input clock to uarta0 is selected, be sure to stop the ascka0 input clock.) serial interface uartc0 note2 stops operation a/d converter stops operation d/a converter stops operation (must stop) real-time output function (rto) stops operation (output held) key interrupt function (kr) operable crc operation circuit stops operation external bus interface see 2.2 pin states (same operation status as idle1 and idle2 modes). port function retains status before low-voltage sub-idle mode was set cpu register set internal ram retains status before low-voltage sub-idle mode was set notes1. be sure to stop the pll (pllctl.pllon bit = 0). 2. pd70f3792, 70f3793, 70f3841, 70f3842 only
v850es/jg3-l chapter 23 standby function r01uh0165ej0700 rev.7.00 page 859 of 1113 sep 22, 2011 23.8.2 releasing sub-idle mode /low-voltage sub-idle mode the sub-idle mode/low-voltage sub-id le mode is released by a non-maskable interrupt request signal (nmi pin input, intwdt2 signal), unmasked external interrupt reques t signal (intp0 to intp7 pin input), unmasked internal interrupt request signal from the peripheral functions operable in the sub-idle mode/low-voltage sub-idle mode, or reset signal (reset by reset pin input, wdt2res signal, low-voltage detector (l vi), or clock monitor (clm)). the pll returns to the operating status it was in before the sub-idle mode was set. it returns to the stop status in the low-voltage sub-idle mode. when the sub-idle mode is released by an interrupt request signal, the subclock operation mode is set. when the low-voltage sub-idle mode is released by an interrupt request signal, the low-voltage subclock operation mode is set. for releasing low-voltage subclock operation mode, see 23.7.3 releasing low-voltage subclock operation mode . (1) releasing sub-idle m ode/low-voltage sub-idle mode by non-maskable inte rrupt request signal or unmasked maskable interru pt request signal the sub-idle mode/low-voltage sub-id le mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request. if the sub-idle mode/low-voltage sub-idle mode is set in an interrupt servicing routine, however, an interrupt request signal that is issued later is serviced as follows. table 23-15. operation after releasing sub-idle mo de/low-voltage idle mode by interrupt request signal release source interrupt acknowledgment status status after release operation after release disabled (di) reset enabled (ei) ? normal reset operation disabled (di) non-maskable interrupt request signal (excluding multiple interrupts) enabled (ei) ? the interrupt request is acknowledged when the sub-idle mode/low-voltage sub-idle mode is released. disabled (di) ? the sub-idle mode/low-voltage sub-idle mode is released but the interrupt request that is the release source is not acknowledged. the interrupt request itself is retained. the processing that was being executed before shifting to the sub-idle mode/low-voltage sub-idle mode is executed. ? an interrupt request with a priority higher than that of the release source is being serviced. the sub-idle mode/low-voltage sub-idle mode is released but the interrupt request that is the release source is not acknowledged. the interrupt request itself is retained. the interrupt that was being serviced before shifting to the sub-idle mode/low-voltage sub-idle mode is serviced. maskable interrupt request signal enabled (ei) ? an interrupt request with a priority lower than that of the release source is being serviced. the interrupt request is acknowledged when the sub-idle mode/low-voltage sub-idle mode is released. cautions1. an interrupt request signal that is disabled by setting the psc.nmi2m, psc.nmi0m, and psc.intm bits to 1 (interrupt disabled) is invalid and cannot release the sub-idle mode/low-voltage sub-idle mode. 2. when the sub-idle mode/low-voltage sub-idle mode are released, 12 cycles of the subclock (about 366 s) elapse from when the interrupt request signal that releases the sub-idle mode is generated to when the mode is released.
v850es/jg3-l chapter 23 standby function r01uh0165ej0700 rev.7.00 page 860 of 1113 sep 22, 2011 23.9 rtc backup mode ( pd70f3792, 70f3793, 70f3841, 70f3842 only) the pd70f3792, 70f3793, 70f3841, and 70f3842 can be swit ched to the rtc backup mode by stopping power supplies other than the rtc backup power supply (rv dd ) after the settings for pre-rtc backup mode have been specified. a nd this mode can reduce current consumption much. in the rtc backup mode, the rtc counts and the subclock o scillator operates by usi ng a regulator dedicated to the rtc backup area that uses rv dd as the power supply. for detail, see chapter 11 real-time counter ( pd70f3792, 70f3793, 70f3841, 70f3842) . 23.9.1 registers the registers that control the rt c backup mode are as follows. ? rtc backup control register 0 (rtcbumctl0) ? subclock low-power operation c ontrol register (soscamctl)
v850es/jg3-l chapter 23 standby function r01uh0165ej0700 rev.7.00 page 861 of 1113 sep 22, 2011 (1) rtc backup control register 0 (rtcbumctl0) the rtcbumctl0 register is the register that contro ls rtc backup mode. this register is a special register that can only be written in a specific sequence (see 3.4.7 special registers ). this register can be read or written in 8-bit or 1-bit units. rbmen using rtc backup mode is disabled using rtc backup mode is enabled rbmen 0 1 rtc backup mode control rtcbumctl0 0 0 0 0 0 0 rbmset 654321 after reset: note r/w address: fffffb00h exiting the pre-rtc backup mode setting the pre-rtc backup mode when the rbmset bit is set (to 1), switch the rtc status to the following. ? select the division clock of subclock (f xt ) as rtc input clock ? rtc interrupt function stop ? rtc pin output function stop ? rtc time error correction function stop rbmset 0 1 rtc backup mode setting <0> <7> note rv dd power-on reset : 00h other kind of reset : previous value retained cautions1. do not set the rbmen and rbmset bits (to 1) at the same time. if they are set (to 1) at the same time, the rtc backup mode might not operate correctly. set the rbmen bit (to 1) first, and then set the rbmset bit (to 1). 2. do not set the rbmset bit (to 1) while the rbmen bit is 0. if the rbmset bit is set (to 1) at this time, the bit is set (to 1), but the pre-rtc backup mode is not specified.
v850es/jg3-l chapter 23 standby function r01uh0165ej0700 rev.7.00 page 862 of 1113 sep 22, 2011 (2) subclock low-power operation control register (soscamctl) the soscamctl register is used to select t he low-power control method of the subclock (f xt ) to perform even lower power operations in the rtc backup mode.. this register is a special re gister that can only be written in a specific sequence (see 3.4.7 special registers ). this register can be read or written in 8-bit or 1-bit units. this register is cleared to 00h when a power-on reset operation is executed for rv dd . 0 normal oscillation ultra low consumption oscillation amphs 0 1 subclock (f xt ) oscillator mode select soscamctl 0 0 0 0 0 0 amphs 654321 after reset: note r/w address: fffffb03h <0> 7 note rv dd power-on reset : 00h other kind of reset : previous value retained caution be sure to set bits 7 to 1 to ?0?. remark when the subclock (f xt ) is oscillating in the ultra low consumpt ion mode, the effects of noise can more easily cause the incorrect number of oscillation cycle counting. before deciding to use this mode, thoroughly evaluate the effects of noise. 23.9.2 rtc backup mode setting conditions the rtc backup mode can be entered by stopping power supplies ot her than the rtc backup power supply (rv dd ) after the settings for the pre-rtc backup m ode have been specified. the procedures for setting and exiting pre-rtc backup mode are described below. (1) conditions for setting pre-rtc backup mode if the following conditions are satisfi ed, the pre-rtc backup mode is set. <1> rtcbumctl0.rbmen = 1 (using rtc backup mode is enabled.) <2> soscamctl.amphs = 1 (this setting is necessary for subclock (f xt ) oscillation in the ultra low consumption mode, but the setting is not necessary for the rtc backup mode.) <3> rtcbumctl0.rbmset = 1 (pre-rtc backup mode setting.) (2) conditions for exiting pre-rtc backup mode if the following conditions are satisfied, the pre-rtc backup mode is exited. <1> soscamctl.amphs = 0 (the norma l oscillation of the subclock.) <2> rtcbumctl0.rbmset = 0 (pre-rtc backup mode exiting.)
v850es/jg3-l chapter 23 standby function r01uh0165ej0700 rev.7.00 page 863 of 1113 sep 22, 2011 23.9.3 rtc backup mode setting procedure the rtc backup mode setting/exiting procedure as follows. (1) setting the rtc backup mode caution in the subclock operation, the rtc backup mode is prohibited. in the main clock operation, be sure to set the rtc backup mode. (a) initial settings before entering the rtc backup mode, execute the setting mode below. initial settings for rtc backup mode ? set rtcbumctl0 to 1 (specific sequence), and se t up the status in which rtc backup mode is enabled. ? set soscamctl.amphs to 0 (specific sequence) , and specify normal oscillation for the subclock (f xt ). ? set rtcbumctl0.rbmset to 0 (specific se quence), and exit the pre-rtc backup mode. ? nop initial settings for peripheral functions ? specify that the lvi be used as an interrupt. (use the lvis register to set the low-voltage detection level to 2.8 v (typ.) or 2.3 v (typ.).) ? if the rtc is in the initial state (rc1cc0.rc1pwr = 0), sp ecify the rtc initial settings. caution use the rc1cc0.rc1cks bit to specify the subclock (f xt ) as the rtc operating clock and start rtc operation. (for ho w to start rtc operation, see chapter 11 real-time counter ( pd70f3792, 70f3793, 70f 3841, and 70f3842)).
v850es/jg3-l chapter 23 standby function r01uh0165ej0700 rev.7.00 page 864 of 1113 sep 22, 2011 (b) intlvi interrupt servicing routine after the v dd decreases and intlvi interrupt occurrs, use the intlvi interrupt servicing routine to execute the following processing. <1> read the low-voltage detection flag (lvim.lvif ) and confirm that lvim.lvif = 1. if lvim.lvif = 1, perform step <2> and the following steps. if lvim.lvif = 0, the v dd voltage has not decreased to the lvi detection level, so do not specify the pre-rt c backup mode (step <2> and subsequent steps), and exec ute the exit processing in (3) exiting the rtc backup mode (when no external reset has occurred) . <2> set the operation clock in accordance with v dd voltage (2.2 v@5 mhz, 2.0 v@2.5 mhz, etc). <3> disable the dma note1 . <4> prohibit nmis (by clearing intf02 and intr02 to 0) and set up a status in which intwd2 is not immediately generated (by clearing wdt2), or stop wdt2 or the wdt2 source clock note 2, 3, 4. <5> mask maskable interrupts other than intlvi by using interrupt mask registers 0 to 3. <6> set soscamctl.amphs to 1 (specif ic sequence), and set the subclock (f xt ) to ultra low consumption mode. <7> set rtcbumctl0.rbmset to 1 (specific sequence), and set the pre-rtc backup mode. <8> set the stop mode. (the system enters rtc backup mode once the v dd voltage supply stops.) <9> reti. notes1. in the intlvi interrupt servicing routine, if a dma operation occurs before disabling dma operations and the v dd voltage reaches the minimum guaranteed voltage before the dma transfer finishes, it becomes impossible to specify the pre-rtc backup mode. 2. in the intlvi interrupt servicing routine, if an nmi or intwdt2 interrupt occurs while specifying the settings in <4>, interrupt servicing starts . if this servicing takes a while, the v dd voltage reaches the minimum guaranteed voltage during the servicing a nd it becomes impossible to specify the pre-rtc backup mode. 3. if the option function is used to set wdtmd1 to 1 and fix wdt2 to the reset mode, wdt2 cannot be stopped. if a reset occurs while these settings are s pecified, the pre-rtc back up mode is exited according to the initial settings of the pre-rtc backup m ode specified in the reset initialization flow. 4. in <4> above, if intwdt2 is generated by clear ing wdt2, and then intwdt2 is generated in the pre-rtc backup mode without the power supplies other than the rtc backup power supply (rv dd ) being stopped (that is, without an external reset being generated), the pre-rtc backup mode is exited. remark if a system reset occurs before the processing in step <7 > in the intlvi interrupt servicing ro utine above is carried out, the system will not ent er rtc backup mode even if the v dd voltage drops.
v850es/jg3-l chapter 23 standby function r01uh0165ej0700 rev.7.00 page 865 of 1113 sep 22, 2011 (2) exiting the rtc backup mode (whe n an external reset has occurred) after entering the rtc backup mode, if an external reset signal (reset) is generated, execute the settings described in (1) (a) initial setti ngs for rtc backup mode . if the v dd voltage goes outside the guaranteed operating range, it is necessary to gener ate an external reset signal (reset). restore the v dd voltage to greater than 2.3 v. (3) exiting the pre-rtc backup mode (when an external reset has not occurred) if the v dd voltage has not dropped to the level at which an external reset signal (reset) is generated after setting the pre-rtc backup mode, the v dd voltage will rise, and once it reaches the level of the lvi voltage, an intlvi interrupt request signal will be generated, c ausing the system to exit stop mode. the reti instruction that is subsequent ly executed in step <9> in (1) (b) intlvi interrupt servicing routine causes the processing to exit the intlvi inte rrupt servicing routine, at which poin t the intlvi interrupt that was held pending when the lvim.lvif bit was set to 0 will be acknowledged. at this time, execute the following processing: (a) intlvi interrupt servicing routine after an intvi interrupt is generated and the norma l stop mode is exited, execute the following processing routine. <1> read the low-voltage detection flag (l vim.lvif) and confirm that lvim.lvif = 0. <2> clear soscamctl.amphs to 0 (specif ic sequence), and set the subclock (f xt ) to normal oscillation. <3> clear rtcbumctl0.rbmset to 0 (specific sequence), and exit the pre-rtc backup mode. <4> nop <5> if necessary, allow eis and nmis. figure 23-2 shows the rtc backup mode state transit ion diagram, and figures 23-3 and 23-4 show the rtc backup mode setting flow charts.
v850es/jg3-l chapter 23 standby function r01uh0165ej0700 rev.7.00 page 866 of 1113 sep 22, 2011 figure 23-2. rtc backup mode status transition reset start normal operaiton rtc backup mode note1 (cpu is reset) stopmode rtc stopped initial settings - initial settings for rtc backup mode - on-chip peripheral settings (bus waits when accessing on-chip peripheral i/o registers, etc.) - lvi settings - rtc settings (not required after returning from rtc backup mode) lvi interrupt occurrs and lvif = 1 /setting pre-rtc backup mode lvi interrupt occurrs and lvif = 0 /exiting pre-rtc backup mode restore v dd voltage and cancel external reset (v dd > 2.3 v) note2 restore v dd voltage and cancel external reset (v dd > 2.3 v) note2 stop power supplies other than rv dd stop power supplies the rv dd notes1. be sure to initialize the rtc (by clearing the rc1cc0.rc1pwr bit (0)) once rv dd is restored (to 1.8 v or higher) after having fallen below 1.8 v. for details, see 33.3 operating conditions or 34.3 operating conditions . 2. to use an operation clock that is greater than 5 mhz afte r restoring the system from the rtc backup mode, be sure to restore v dd to greater than 2.7 v. remark (trigger for shifting state) / (proce ssing executed when state is shifted)
v850es/jg3-l chapter 23 standby function r01uh0165ej0700 rev.7.00 page 867 of 1113 sep 22, 2011 figure 23-3. setting the rtc backup mode (1/2) reset start is the rtc in the initial state? (rc1cc0.rc1pwr = 0?) normal operaiton set rtcbumctl0 to 1 (specific sequence), and rtc backup mode is enabled. set soscamctl.amphs to 0 (specific sequence), and specify normal oscillation for the subclock (f xt ). set rtcbumctl0.rbmset to 0 (specific sequence), and exit the pre-rtc backup mode. nop initial settings for peripheral functions specify that the lvi be used as an interrupt. (use the lvis register to set the low- voltage detection level to 2.8 v.) note initial settings for the rtc ye s no initial settings for rtc backup mode note the detection voltage can be set to 2.30 v (by setting the lvis register to 01h) when an operation clock of f xx = 2.5 to 5 mhz is used. remark in rtc backup mode , do not set the low-vo ltage detection level to 2.10 v (lvis = 02h).
v850es/jg3-l chapter 23 standby function r01uh0165ej0700 rev.7.00 page 868 of 1113 sep 22, 2011 figure 23-4. setting the rtc backup mode (2/2) intlvi interrupt servicing v dd < lvi detection voltage? (lvim.lvif = 1?) lvi detection voltage = 2.8 v? (lvis = 00h?) reti set soscamctl.amphs to 1 (specific sequence), and set the subclock (f xt ) to ultra low consumption mode. set rtcbumctl0.rbmset to 1 (specific sequence), and set the pre-rtc backup mode. disable the dma operation set operation clock to 5 mhz mask maskable interrupts other than intlvi by using interrupt mask registers 0 to 3. unmask maskable interrupts, enable ei and nmi, and return clock settings to original values, as required. prohibit nmis (by clearing intf02 and intr02 to 0) and set up a status in which intwd2 is not immediately generated, or stop wdt2 or the wdt2 source clock. set the stop mode. set soscamctl.amphs to 0 (specific sequence), and specify normal oscillation for the subclock (f xt ). note set rtcbumctl0.rbmset to 0 (specific sequence), and exit the pre-rtc backup mode. ye s no ye s no setting pre-rtc backup mode exiting pre-rtc backup mode power supplies other than rv dd are stopped, and the system enters rtc backup mode. set operation clock to 2.5 mhz nop note this setting is required to specify ultr a-low-power oscillation for the subclock (f xt ), but it is not a requisite setting for rtc backup mode. remark in stop mode, once the v dd voltage rises to above the lvi det ection voltage level, an intlvi interrupt request signal is generated, and stop m ode is exited. the current intlvi interrupt servicing is then canceled by t he execution of the reti inst ruction. the newly generated (pending) intlvi is then immediately serviced, and the processing br anches to the pre-rtc backup mode cancellation processing when the answer to the first query (lvim.lvif = 1?) is no .
v850es/jg3-l chapter 23 standby function r01uh0165ej0700 rev.7.00 page 869 of 1113 sep 22, 2011 figure 23-5. rtc backup mode power supply configuration example (simple power supply) pd70f3792, 70f3793, 70f3841,70f3842 rtc v dd v dd rv dd v ss pd70f3792, 70f3793, 70f3841,70f3842 rtc v dd v dd rv dd v ss (a) normal operation (b) rtc backup mode the charge current limit resistor note super capacitor (electric double-layer capacitor) super capacitor (electric double-layer capacitor) the charge current limit resistor note note add a limit on the char ge current if necessary. figure 23-6. rtc backup mode power supply configuration example (double power supply) pd70f3792, 70f3793, 70f3841,70f3842 rtc v dd v dd rv dd v aa (a) normal operation (b) rtc backup mode pd70f3792, 70f3793, 70f3841,70f3842 rtc v dd v dd rv dd v aa battery switch battery switch
v850es/jg3-l chapter 24 reset function r01uh0165ej0700 rev.7.00 page 870 of 1113 sep 22, 2011 chapter 24 reset function 24.1 overview the reset function is used to initializ e the settings of the v850 es/jg3-l functions. this function is used, for example, to stop operation at power-on until the supply voltage reaches the operation voltage le vel, or to initialize the settings of the v850es/jg3-l functions at any time. the v850es/jg3-l starts operat ing at address 00000000h immediately after a reset ends. the following sources cause a reset: (1) four reset sources ? external reset input via the reset pin ? reset via a watchdog timer 2 (wdt2) overflow (wdt2res) ? system reset based on comparison of the low-volt age detector (lvi) supply voltage and detected voltage ? system reset based on detecting that osci llation of clock monitor (clm) has stopped the source of the reset can be confirmed by using th e reset source flag register (resf) immediately after a reset ends. (2) emergency operation mode if wdt2 overflows during the main clock oscillation stab ilization time inserted after a reset, the main clock oscillation is judged as abnormal and the cpu star ts operating on the internal oscillator clock. caution in the emergency operation mode, do not access on-chip peripheral i/o registers other than those for the interrupt function, port function, wdt2, and timer m, which can operate on the internal oscillator clock. in addition, operating csib0 to csib4 and uarta0 by using an external clock is also prohibited.
v850es/jg3-l chapter 24 reset function r01uh0165ej0700 rev.7.00 page 871 of 1113 sep 22, 2011 24.2 configuration figure 24-1. block di agram of reset function clmrf lvirf wdt2rf reset source flag register (resf) internal bus wdt2 reset signal clm reset signal reset lvi reset signal reset signal (active-low) reset signal to lvim/lvis register clear set set clear clear set caution an lvi circuit internal reset does not reset the lvi circuit. remarks 1. lvim: low-voltage detection register 2. lvis: low-voltage detection level select register
v850es/jg3-l chapter 24 reset function r01uh0165ej0700 rev.7.00 page 872 of 1113 sep 22, 2011 24.3 register to check reset source the v850es/jg3-l has four reset source s. the source of the reset that occurred can be checked by using the reset source flag register (resf) immediately after a reset ends. (1) reset source flag register (resf) the resf register is a special regi ster that can be written only in a co mbination of specific sequences (see 3.4.7 special registers ). the resf register indicates the s ource that generated a reset signal. this register is read or written in 8-bit or 1-bit units. reset pin input clears this register to 00h. the default value differs if the source of the reset is other than the reset pin signal. 0 wdt2rf 0 1 not generated generated resf 0 0 wdt2rf 0 0 clmrf lvirf after reset: 00h note r/w address: fffff888h reset signal from wdt2 lvirf 0 1 not generated generated reset signal from lvi clmrf 0 1 not generated generated reset signal from clm note the value of the resf register is cleared to 00h when a reset is executed via the reset pin. when a reset is executed by watchdog timer 2 (wdt2), the low- voltage detector (lvi), or the clock monitor (clm), the reset flags of this register (wdt2rf bit, clmrf bit, and lvirf bit) are set. however, other sources are retained. caution only ?0? can be written to each bit of this register. if writing ?0? conflicts with setting the flag (occurrence of reset), se tting the flag takes precedence.
v850es/jg3-l chapter 24 reset function r01uh0165ej0700 rev.7.00 page 873 of 1113 sep 22, 2011 24.4 operation 24.4.1 reset operation via reset pin when a low level is input to the reset pin, the syst em is reset, and each hardware unit is initialized. when the level of the reset pin is changed from low to high, the reset status ends. the reset pin has an internal noise elimination circui t that uses analog delay (60 ns (typ.)) to prevent malfunction caused by noise. table 24-1. hardware status on reset pin input item during reset after reset main clock oscillator (f x ) oscillation stops oscillation starts subclock oscillator (f xt ) oscillation continues internal oscillator oscillation stops oscillation starts peripheral clock (f x to f x /1,024) operation stops operation starts after securing oscillation stabilization time internal system clock (f clk ), cpu clock (f cpu ) operation stops operation starts after securing oscillation stabilization time (initialized to f xx /8) cpu initialized program execution starts at address 00000000h after securing oscillation stabilization time watchdog timer 2 operation stops (initialized to 0) counts up from 0 with internal oscillator clock as source clock. rtc note 1 operation continues internal ram undefined if power-on reset or cpu access and reset input conflict (data is damaged). otherwise value imm ediately after reset input is retained. i/o lines (ports/alternate-function pins) high impedance note 2 on-chip peripheral i/o registers initialized to sp ecified status, ocdm register is set (01h). other on-chip peripheral functions operation stops operation can be started after securing oscillation stabilization time notes 1. pd70f3792, 70f3793, 70f3841, 70f3842 only. 2. when the power is turned on, the following pins may output an undefined level temporarily even during reset. ? p10/ano0 pin ? p11/ano1 pin ? p53/sib2/kr3/tiq00/toq00/rtp03/ddo pin caution the ocdm register is initia lized by the reset pin input. the refore, note with caution that, if a high level is input to the p05/drst pin immediately after a reset ends before the ocdm.ocdm0 bit is cleared, the on-chip debug mode may be entered. for details, see chapter 4 port functions.
v850es/jg3-l chapter 24 reset function r01uh0165ej0700 rev.7.00 page 874 of 1113 sep 22, 2011 figure 24-2. timing of reset operation by reset pin input counting of oscillation stabilization time initialized to f xx /8 oscillation stabilization timer overflows internal system reset signal analog delay (eliminated as noise) analog delay analog delay (eliminated as noise) reset f x f clk analog delay cpu operation
v850es/jg3-l chapter 24 reset function r01uh0165ej0700 rev.7.00 page 875 of 1113 sep 22, 2011 figure 24-3. timing of power-on reset operation oscillation stabilization time count on-chip regulator stabilization time note overflow of timer for oscillation stabilization internal system reset signal reset f x v dd f clk analog delay initialized to f xx /8 cpu operation note time after v dd reaches 2.2 v: 3.5 ms (max.) time after v dd reaches 2.7 v: 1.0 ms (max.) caution do not disable reset until the volt age of the on-chip regulator stabilizes.
v850es/jg3-l chapter 24 reset function r01uh0165ej0700 rev.7.00 page 876 of 1113 sep 22, 2011 24.4.2 reset operation by watchdog timer 2 when watchdog timer 2 is set to the reset operati on mode due to overflow, upon watchdog timer 2 overflow (wdt2res signal generati on), a system reset is executed and the hardware is initialized to the initial status. following watchdog timer 2 overflow, the reset status is entered and lasts the predetermined time (analog delay), and then the reset status ends automatically. the main clock oscillator is stopped during the reset period. table 24-2. hardware status duri ng watchdog timer 2 reset operation item during reset after reset main clock oscillator (f x ) oscillation stops. oscillation starts. subclock oscillator (f xt ) oscillation continues. internal oscillator oscillation stops. oscillation starts. peripheral clock (f xx to f xx /1,024) operation stops. operation starts after securing oscillation stabilization time. internal system clock (f xx ), cpu clock (f cpu ) operation stops. operation starts after securing oscillation stabilization time (initialized to f xx /8). cpu initialized program execution after securing oscillation stabilization time watchdog timer 2 operation stops (initialized to 0). counts up from 0 with internal oscillator clock as source clock. rtc note operation continues internal ram undefined if power-on reset or cpu access a nd reset input conflict (data is damaged). otherwise value imm ediately after reset input is retained. i/o lines (ports/alternate-function pins) high impedance on-chip peripheral i/o register initialized to spec ified status, ocdm register retains its value. on-chip peripheral functions other than above operation stops. operation can be started after securing oscillation stabilization time. note pd70f3792, 70f3793, 70f3841, 70f3842 only.
v850es/jg3-l chapter 24 reset function r01uh0165ej0700 rev.7.00 page 877 of 1113 sep 22, 2011 figure 24-4. timing of reset oper ation by wdt2res signal generation counting of oscillation stabilization time initialized to f xx /8 cpu operation oscillation stabilization timer overflow internal system reset signal wdt2res f x f clk analog delay
v850es/jg3-l chapter 24 reset function r01uh0165ej0700 rev.7.00 page 878 of 1113 sep 22, 2011 24.4.3 reset operation by low-voltage detector if the supply voltage falls below the volt age detected by the low-voltage detect or when lvi operation is enabled, a system reset is executed (when the lvim.lvimd bit is set to 1), and the hardware is initia lized to the initial status. the reset status lasts from when a supply voltage drop has been detected unt il the supply voltage rises above the lvi detection voltage. the main clock oscillator is stopped during the reset period. when the lvimd bit is cleared to 0, an interrupt request signal (intlvi) is generated if the supply voltage falls below or exceeds the detected voltage. table 24-3. hardware status during reset operation by low-voltage detector item during reset after reset main clock oscillator (f x ) oscillation stops. oscillation starts. subclock oscillator (f xt ) oscillation continues. internal oscillator oscillation stops. oscillation starts. peripheral clock (f x to f x /1,024) operation stops. operation starts after securing oscillation stabilization time. internal system clock (f xx ), cpu clock (f cpu ) operation stops operation starts after securing oscillation stabilization time (initialized to f xx /8). cpu initialized program execution starts after securing oscillation stabilization time watchdog timer 2 operation stops (initialized to 0). counts up from 0 with internal oscillator clock as source clock. rtc note operation continues internal ram undefined i/o lines (ports/alternate-function pins) high impedance on-chip peripheral i/o register initialized to spec ified status, ocdm register retains its value. lvi operation stops. on-chip peripheral functions other than above operation stops. operation can be started after securing oscillation stabilization time. note pd70f3792, 70f3793, 70f3841, 70f3842 only. remark for the reset timing of the low-voltage detector, see chapter 26 low-voltage detector (lvi) .
v850es/jg3-l chapter 24 reset function r01uh0165ej0700 rev.7.00 page 879 of 1113 sep 22, 2011 24.4.4 operation immediately after reset ends (1) immediately after reset ends normally immediately after a reset ends, the main clock starts oscillating, the oscillati on stabilization time (which differs depending on the option byte; for details, see chapter 29 option byte ) is secured, and then the cpu starts executing the program. wdt2 begins to operate immediately after a reset ends usin g the internal oscillator clock as the source clock. figure 24-5. operation immediately after reset ends main clock reset counting of oscillation stabilization time normal operation (f cpu = main clock) operation stops operation in progress operation stops operation in progress clock monitor internal oscillator clock v850es/jg3-l wdt2 software-based clock monitoring starts.
v850es/jg3-l chapter 24 reset function r01uh0165ej0700 rev.7.00 page 880 of 1113 sep 22, 2011 (2) emergency operation mode if an anomaly occurs in the main clock before the oscilla tion stabilization time is secured, wdt2 overflows before the cpu starts executing the program. at this time, the cpu starts executing the program by using the internal oscillator clock as the source clock. caution in the emergency operation mode, do not access on-chip peripheral i/o registers other than those for the interrupt function, port function, wdt2, and timer m, which can operate on the internal oscillator clock. in addition, operating csib0 to csib4 and uarta0 by using an external clock is also prohibited. figure 24-6. operation immediately after reset ends main clock reset counting of oscillation stabilization time wdt overflows emergency operation mode (f cpu = internal oscillator clock) operation stops operation in progress operation in progress (re-count) operation stops clock monitor internal oscillator clock v850es/jg3-l wdt2 the cpu operation clock states can be checked by using the cpu operati on clock status register (ccls).
v850es/jg3-l chapter 24 reset function r01uh0165ej0700 rev.7.00 page 881 of 1113 sep 22, 2011 24.4.5 reset function operation figure 24-7. reset function operation start (reset source generated) main clock oscillation stabilization time secured? no ccls.cclsf bit = 1? yes no yes (in normal operation mode) wdt2 overflow? no yes (in emergency operation mode) set resf register note 1 reset occurs reset ends emergency operation software processing normal operation cpu starts operation at 00000000h (f cpu = f x /8, f r ) f cpu = f x f cpu = f r note 2 ccls.cclsf bit 1 wdt2 restart internal oscillation and main clock oscillation start, wdt2 count up starts (reset mode) notes 1. the bit to be set differs depending on the reset source. reset source wdt2rf bit crmrf bit lvirf bit reset pin 0 0 0 wdt2 1 value before reset is retained. value before reset is retained. clm value before reset is retained. 1 value before reset is retained. lvi value before reset is retained. value before reset is retained. 1 2. the internal oscillator cannot be stopped.
v850es/jg3-l chapter 24 reset function r01uh0165ej0700 rev.7.00 page 882 of 1113 sep 22, 2011 24.5 cautions when executing a power-on reset operation, the supply voltage must be within the guaranteed operating range immediately after the reset ends. the usable range of the internal operating fr equency of the v850es/jg3-l depends on the supply voltage (2.5 mhz (max.) @ 2.0 to 2.2 v or 5 mhz (max.) @ 2.2 to 2.7 v or 20 mhz (max.) @ 2.7 to 3.6 v). (1) at less than 2.0 v imme diately after reset ends use prohibited (2) at 2.0 v or more to less than 2.2 v immediately after reset ends ( pd70f3792, 70f3793, 70f3841, 70f3842 only) ? input f x = 2.5 mhz to the main clock oscillator and set the clock-through mode (pllctl.selpll = 0). ? inputting 2.5 mhz or more to the main clock oscillator is prohibited. ? be sure to stop the pll (pllctl.pllo n = 0) in the initialization routine. pd70f3737, 70f3738 cannot be used. (3) at 2.2 v or more to less than 2.7 v immediately after reset ends ? input f x = 2.5 to 5 mhz to the main clock oscillator and set the clock-through mode (pllctl.selpll = 0). ? inputting 5 mhz or more to the main clock oscillator is prohibited. ? be sure to stop the pll (pllctl.pllo n = 0) in the initialization routine. (4) at 2.7 to 3.6 v imme diately after reset ends ? both the clock-through mode and pll mode can be used. remarks 1. the voltage value (v) is the value of v dd . 2. a reset ends at the following timing. for the relationship between the rising of v dd and when the reset signal generated by the reset pin ends, see 32.7.4 power on/power off/reset timing and 33.7.4 power on/power off/reset timing . v dd reset ends reset
v850es/jg3-l chapter 25 clock monitor r01uh0165ej0700 rev.7.00 page 883 of 1113 sep 22, 2011 chapter 25 clock monitor 25.1 functions the clock monitor monitors the main clock by using t he internal oscillator clock and generates a reset request signal when oscillation of the main clock is stopped. once the operation of the clock monitor has been enabled by an operation enable flag, it cannot be cleared to 0 by any means other than a reset. when a reset by the clock monitor occurs, the resf.clmrf bit is set. for details on the resf register, see 24.3 registers to check reset source . the clock monitor automatically stops under the following conditions. ? during oscillation stabilization time after stop mode is released ? when the main clock is stopped (from when the pcc. mck bit = 1 during subclock operation, until the pcc.cls bit = 0 during main clock operation) ? when the monitoring clock (internal oscillator clock) is stopped ? when the cpu operates with the internal oscillator clock 25.2 configuration the clock monitor includes the following hardware. table 25-1. configuration of clock monitor item configuration control register clock monitor mode register (clm) figure 25-1. block diagram of clock monitor operation mode controller main clock main clock oscillation monitor internal reset signal clock monitor operation enable signal (clm.clme bit) main clock oscillation enable signal (pcc.mck bit) internal oscillator clock
v850es/jg3-l chapter 25 clock monitor r01uh0165ej0700 rev.7.00 page 884 of 1113 sep 22, 2011 25.3 registers the clock monitor is controlled by the clock monitor mode register (clm). (1) clock monitor mode register (clm) the clm register is a special register that can only be written in a combination of specific sequences (see 3.4.7 special registers ). this register is used to set the operation mode of the clock monitor. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. after reset: 00h r/w address: fffff870h 7 6 5 4 3 2 1 <0> clm 0 0 0 0 0 0 0 clme clme clock monitor operation enable or disable 0 disable clock monitor operation. 1 enable clock monitor operation. cautions 1. once the clme bit has b een set to 1, it cannot be cleared to 0 by any means other than a reset. 2. when a reset by the clock monitor occu rs, the clme bit is cleared to 0 and the resf.clmrf bit is set to 1.
v850es/jg3-l chapter 25 clock monitor r01uh0165ej0700 rev.7.00 page 885 of 1113 sep 22, 2011 25.4 operation this section describes the clock monitor operation. the monitoring start and monitoring stop conditions are as follows. enabling operation by setting the clm.clme bit to 1 ? while oscillation stabilization time is being counted after stop mode is released ? when the main clock is stopped (from when pcc.mck bi t is set to 1 during subclock operation to when pcc.cls bit is set to 0 during main clock operation) ? when the sampling clock (internal oscillator clock) is stopped ? when the cpu operates on the internal oscillator clock table 25-2. operation status of cl ock monitor (when clm.clme bit = 1) cpu operating clock operation mode status of main clock status of internal oscillator clock status of clock monitor halt mode oscillates oscillates note 1 operates idle1, idle2 modes oscillates oscillates note 1 operates main clock stop mode stops oscillates note 1 stops subclock (mck bit of pcc register = 0) sub-idle mode oscillates oscillates note 1 operates subclock (mck bit of pcc register = 1) sub-idle mode stops oscillates note 1 stops internal oscillator clock emergency operation mode note 2 stops oscillates note 3 stops during reset ? stops stops stops notes 1. the internal oscillator can be stopped by setting the rcm.rstop bit to 1. 2. see 24.4.4 (2) emergency operation mode . 3. the internal oscillator cannot be stopped by software.
v850es/jg3-l chapter 25 clock monitor r01uh0165ej0700 rev.7.00 page 886 of 1113 sep 22, 2011 (1) operation when main clock osc illation is stopped (clme bit = 1) if oscillation of the main clock is stopped when the clme bit is 1, an internal reset signal is generated as shown in figure 25-2. figure 25-2. reset period due to st oppage of main clock oscillation four internal oscillator clocks main clock internal oscillator clock internal reset signal (active-low) clm.clme bit resf.clmrf bit (2) clock monitor status after reset input reset input clears the clm.clme bit to 0 and stops the clock monitor operation. when the clme bit is set to 1 by software after the normal operati on is started, monitoring is started. figure 25-3. clock monitor status after reset input (clm.clme bit = 1 is set after reset is input and normal operation is started) cpu operation clock monitor status clme reset internal oscillator clock main clock reset oscillation stabilization time normal operation clock supply stopped normal operation monitoring monitoring stopped monitoring set to 1 by software
v850es/jg3-l chapter 25 clock monitor r01uh0165ej0700 rev.7.00 page 887 of 1113 sep 22, 2011 (3) operation in stop mode or after stop mode is released if the stop mode is set with the clm.clme bit = 1, the monitor operation is stopped in the stop mode and while the oscillation stabilization time is being counted. after the osci llation stabilization time, the monitor operation is automatically started. figure 25-4. operation in stop mode or after stop mode is released clock monitor status during monitor monitor stops during monitor clme internal oscillator clock main clock cpu operation normal operation stop oscillation stabilization time normal operation oscillation stops oscillation stabilization time (set by osts register) (4) operation when main cl ock is stopped (arbitrary) during subclock operation (pcc.cls bit = 1) or when the main clock is stopped by setting the pcc.mck bit to 1, the monitor operation is stopped until the main clock operation is started (pcc.cls bit = 0). the monitor operation is automatically started when the main clock operation is started. figure 25-5. operation when main clock is stopped (arbitrary) clock monitor status during monitor monitor stops monitor stops during monitor clme internal oscillator clock main clock cpu operation oscillation stops subclock operation main clock operation oscillation stabilization time count by software pcc.mck bit = 1 (5) operation while cpu is operating on inte rnal oscillator clock (ccls.cclsf bit = 1) the monitor operation is not stopped when the cclsf bi t is 1, even if the clme bit is set to 1.
v850es/jg3-l chapter 26 low-voltage detector (lvi) r01uh0165ej0700 rev.7.00 page 888 of 1113 sep 22, 2011 chapter 26 low-voltage detector (lvi) 26.1 functions the low-voltage detector (lvi) has the following functions. ? if interrupt occurrence at low-voltage detection is sele cted as the operation mode, the low-voltage detector compares the supply voltage (v dd ) and the detection voltage (v lv i ), and generates an internal interrupt signal when the supply voltage drops below or rises above the detection voltage. ? if reset occurrence at low-voltage detection is se lected as the operation mode , the low-voltage detector generates an internal reset signal when the supply voltage (v dd ) drops below the detection voltage (v lv i ). ? the level of the supply voltage to be detected can be changed by software. two steps: pd70f3737, 70f3738 three steps : pd70f3792, 70f3793, 70f3841, 70f3842 ? interrupt or reset signal c an be selected by software. ? the low-voltage detector is operable in the standby mode. if a reset occurs when the low-voltage detector is selected to generate a reset signal, the resf.lvirf bit is set to 1. for details about the resf register, see 24.3 register to check reset source . 26.2 configuration the block diagram of the low-vo ltage detector is shown below. figure 26-1. block diagram of low-voltage detector lvis0 lvis1 note lvion detected voltage source (v lvi ) v dd v dd intlvi internal bus n-ch low voltage detection level select register (lvis) low voltage detection register (lvim) lvimd lvif internal reset signal selector low voltage detection level selector ? + note pd70f3792, 70f3793, 70f3841, 70f3842 only
v850es/jg3-l chapter 26 low-voltage detector (lvi) r01uh0165ej0700 rev.7.00 page 889 of 1113 sep 22, 2011 26.3 registers the low-voltage detector is contro lled by the following registers. ? low voltage detection register (lvim) ? low voltage detection level select register (lvis) (1) low voltage detection register (lvim) the lvim register is a special register. this can be written only in a combination of specific sequences (see 3.4.7 special registers ). the lvim register is used to enable or disable low vo ltage detection, and to set the operation mode of the low-voltage detector. this register can be read or written in 8-bit or 1- bit units. however, the lvif bit is read-only. after reset: note 1 r/w address: fffff890h <7> 6 5 4 3 2 <1> <0> lvim lvion 0 0 0 0 0 lvimd lvif lvion low voltage detection enable or disable 0 disable operation. 1 enable operation. lvimd selection of operation mode of low-voltage detector 0 generate interrupt request signal intlvi when supply voltage drops below or rises above detection voltage. 1 generate internal reset signal lvires when supply voltage drops below detection voltage. lv i f notes 2, 3, 4 low voltage detection flag 0 supply voltage rises above detection voltage, or operation is disabled. 1 supply voltage of connected power supply is lower than detection voltage. notes 1. reset by low-voltage detection: 82h reset due to other source: 00h 2. do not change the lvion bit from 1 to 0 while the supply voltage (v dd ) is lower than the detection voltage (v lvi ) (lvim.lvif bit = 1). 3. after the lvi operation has started (lvion bit = 1), check the lvif bit. 4. when the intlvi signal is generated, check t he lvif bit to see whether the supply voltage has fallen below or exceeds the detection voltage. cautions 1. when the lvion and lvimd bits are set to 1, the low-voltage detector cannot be stopped until a reset request due to ot her than low-voltage detection is generated. 2. when the lvion bit is set to 1, the comparat or in the lvi circuit starts operating. wait at least 0.2 ms, set by software, before checking the voltage by using the lvif bit after the lvion bit is set. 3. be sure to set bits 6 to 2 to ?0?.
v850es/jg3-l chapter 26 low-voltage detector (lvi) r01uh0165ej0700 rev.7.00 page 890 of 1113 sep 22, 2011 (2) low voltage detection l evel select register (lvis) the lvis register is used to select the level of voltage to be detected. this register can be read or written in 8-bit units. after reset: note1 r/w address: fffff891h 7 6 5 4 3 2 <1> <0> lvis 0 0 0 0 0 0 lvis1 note2 lv i s 0 lv i s 1 note2 lvis0 low-voltage detection level 0 0 2.80 v (typ.) 0 1 2.30 v (typ.) 1 0 2.10 v (typ.) 1 1 setting prohibited notes 1. reset by low-voltage detection: retained reset due to other source: 00h 2. pd70f3792, 70f3793, 70f3841, 70f3842 only cautions 1. this register cannot be written until a reset request due to something other than low-voltage detection is generated after the lvim.lvion and lvim.lvimd bits are set to 1. 2. be sure to clear bits 7 to 1 to ?0? only in the pd70f3737, 70f3738. 3. be sure to clear bits 7 to 2 to ?0? only in the pd70f3792, 70f3793, 70f3841, 70f3842.
v850es/jg3-l chapter 26 low-voltage detector (lvi) r01uh0165ej0700 rev.7.00 page 891 of 1113 sep 22, 2011 26.4 operation depending on the setting of the lvim.vimd bit, an interrupt signal (intlvi) or an internal reset signal is generated. how to specify each operation is described below, together with timing charts. 26.4.1 to use for internal reset signal <1> mask the interrupt of lvi. <2> select the voltage to be detected by using the lvis.lvis0 bit. <3> set the lvim.lvion bit to 1 (to enable operation). <4> insert a wait cycle of 0.2 ms or more by software. <5> by using the lvim.lvif bit, check if the s upply voltage is lower than the detection voltage. <6> set the lvimd bit to 1 (to generate an internal reset signal). caution if the lvimd bit is set to 1, the contents of the lvim and lvis registers cannot be changed until a reset request other than lvi is generated. figure 26-2. timing of low-voltage detector operation (lvimd bit = 1, low-voltage detection level: 2.80 v) supply voltage (v dd ) lvi detection voltage (2.80 v (typ.)) lvion bit internal reset signal (active low) lvi reset request signal (active-low) time
v850es/jg3-l chapter 26 low-voltage detector (lvi) r01uh0165ej0700 rev.7.00 page 892 of 1113 sep 22, 2011 26.4.2 to use for interrupt <1> mask the interrupt of lvi. <2> select the voltage to be detected by using the lvis.lvis0 bit. <3> set the lvim.lvion bit to 1 (to enable operation). <4> insert a wait cycle of 0.2 ms (max.) or more by software. <5> by using the lvim.lvif bit, check if the s upply voltage is higher than the detection voltage. <6> clear the interrupt request flag of lvi. <7> unmask the interrupt of lvi. <1> by using the lvim.lvif bit, check if the s upply voltage is higher than the detection voltage. <2> clear the lvion bit to 0. figure 26-3. timing of low-voltage detector operation (lvimd bit = 0, low-voltage detection level: 2.80 v) supply voltage (v dd ) lvi detection voltage (2.80 v (typ.)) external resetic detection voltage lvion bit reset pin intlvi signal time caution when the intlvi signal is generated, conf irm, by using the lvim.lvif bit, whether the intlvi signal was generated due to the supply voltage dropping below or rising above the detection voltage.
v850es/jg3-l chapter 27 crc function r01uh0165ej0700 rev.7.00 page 893 of 1113 sep 22, 2011 chapter 27 crc function 27.1 functions ? generation of crc (cyclic redundancy check) c ode for detecting errors in communication data ? generation of crc code for detecting errors in data blocks ? generation of 16-bit crc code using a crc-ccitt (x 16 + x 12 + x 5 + 1) generation polynomial for blocks of data of any length in 8-bit units ? crc code is set to the crc data register each time 1-by te data is transferred to the crcin register, after the initial value is set to the crcd register. 27.2 configuration the crc function includes the following hardware. table 27-1. crc configuration item configuration control registers crc input register (crcin) crc data register (crcd) figure 27-1. block diagram of crc function crc data register (crcd) (16 bits) crc input register (crcin) (8 bits) internal bus internal bus crc code generator
v850es/jg3-l chapter 27 crc function r01uh0165ej0700 rev.7.00 page 894 of 1113 sep 22, 2011 27.3 registers (1) crc input register (crcin) the crcin register is an 8-bi t register for setting data. this register can be read or written in 8-bit units. reset sets this register to 00h. crcin 654321 after reset: 00h r/w address: fffff310h 7 0 (2) crc data register (crcd) the crcd register is a 16-bit register t hat stores the crc-ccitt operation results. this register can be read or written in 16-bit units. reset sets this register to 0000h. caution accessing the crcd register is prohibited in the following statuses. if a wait cycle is generated, it can only be cleared by a reset. for details, see 3.4.9 (1) accessing specific on-chip peripheral i/o registers. ? when the cpu operates on the subclock and main clock oscillation is stopped ? when the cpu operates on the internal oscillator clock crcd 12 10 8 6 4 2 after reset: 0000h r/w address: fffff312h 14 0 13 11 9 7 5 3 15 1
v850es/jg3-l chapter 27 crc function r01uh0165ej0700 rev.7.00 page 895 of 1113 sep 22, 2011 27.4 operation an example of the operation of the crc circuit is shown below. figure 27-2. crc circuit operation example (lsb first) (1) setting of crcin to 01h 1189h b15 b0 b0 b7 crc code is stored (2) reading the crcd register 01h remark this is an example when 0000h is written to the crcd register as the initial value. the code when 01h is sent lsb first is (1000 00 00). therefore, the crc code calculated by using the generation polynomial x 16 + x 12 + x 5 + 1 is the remainder when sixteen digits of zero are appended to (1000 0000) to make the code become (1000 0000 0000 0000 0000 0000) and the code is divided by (1 0001 0000 0010 0001) by using a modulo-2 operation formula. a modulo-2 operation is performed based on the following formula. 0 + 0 = 0 0 + 1 = 1 1 + 0 = 1 1 + 1 = 0 ? 1 = 1 1 0001 0000 0010 0001 1000 0000 0000 0000 0000 0000 1000 1000 0001 0000 1 1000 0001 0000 1000 0 1000 1000 0001 0000 1 1001 0001 1000 1000 1000 1000 lsb lsb msb msb therefore, the crc code becomes . since lsb-first is used, this corresponds to 1189h in hexadecimal notation. 1001 9811 0001 1000 1000
v850es/jg3-l chapter 27 crc function r01uh0165ej0700 rev.7.00 page 896 of 1113 sep 22, 2011 27.5 usage how to use the crc logic circuit is described below. figure 27-3. crc operation start write 0000h to crcd register read crcd register write crcin register yes no input data exists? end [basic usage] <1> write 0000h to the crcd register. <2> write the required quantity of data to the crcin register. <3> read the crcd register.
v850es/jg3-l chapter 27 crc function r01uh0165ej0700 rev.7.00 page 897 of 1113 sep 22, 2011 communication errors can easily be detected if the crc code is transmitted/received along with transmit/receive data when transmitting/receiving data consisting of several bytes. the following figure shows an example when all of the data 12345678h (0001 0010 0011 0100 0101 0110 0111 1000b) is transmitted lsb-first. figure 27-4. crc transmission example 78 transmit/receive data (12345678h) crc code (08f6h) 56 34 12 f6 08 processing on transmitting side <1> write the initial value 0000h to the crcd register. <2> write the 1 byte of data to be trans mitted first to the transmit buffer register. (at this time, also write the same data to the crcin register.) <3> when transmitting several bytes of data, write the same data to the crcin register each time transmit data is written to the transmit buffer register. <4> after all the data has been transmitted, write the contents of the crcd regi ster (crc code) to the transmit buffer register and transmit them. (the dat a is transmitted lsb-first, starting from the lower bytes, and then the higher bytes.) <5> if a resend is requested by the transmitting side, resend the data. processing on receiving side <1> write the initial value 0000h to the crcd register. <2> when reception of the first 1 byte of data is co mplete, write that receive data to the crcin register. <3> if receiving several bytes of data, write the receive data to the crcin register every time reception ends. (in the case of normal reception, when all the receive data has been written to the crcin register, the contents of the crcd register on the receiving side and the contents of the crcd register on the transmitting side are the same.) <4> next, the crc code is transmitted from the transmi tting side, so write this data to the crcin register similarly to receive data. <5> when reception of all the data, including the crc code, has been completed, reception was normal if the contents of the crcd r egister are 0000h. if the contents of the crcd register are other than 0000h, this indicates a communication error, so tr ansmit a resend request to the transmitting side.
v850es/jg3-l chapter 28 regulator r01uh0165ej0700 rev.7.00 page 898 of 1113 sep 22, 2011 chapter 28 regulator 28.1 outline the v850es/jg3-l includes a regulator to reduce power consumption and noise. this regulator supplies a stepped-down v dd power supply voltage to the oscillator block and internal logic circuits (except the a/d converter, d/a converter, and output buffers). and these supply a stepped-down rv dd power supply voltage to the rtc and sub-oscillator block ( pd70f3792, 70f3793, 70 f3841, 70f3842 only). figure 28-1. regulator ( pd70f3737, 70f3738) d/a converter av ref0 av ref1 flmd0 ev dd v dd regc ev dd i/o buffer regulator a/d converter main, sub- oscillator internal digital circuits flash memory bidirectional level shifter caution use the regulator with a setting of v dd = ev dd = av ref0 = av ref1 .
v850es/jg3-l chapter 28 regulator r01uh0165ej0700 rev.7.00 page 899 of 1113 sep 22, 2011 figure 28-2. regulator ( pd70f3792, 70f3793, 70f3841, 70f3842) d/a converter av ref0 av ref1 flmd0 ev dd v dd rv dd regc ev dd i/o buffer regulator a/d converter main-oscillator internal digital circuits flash memory bidirectional level shifter regulator sub- oscillator rtc rtc back up area cautions1. use the regulator with a setting of v dd = ev dd = av ref0 = av ref1 . 2. rv dd can be used at a different potential to that used by the other power supplies.
v850es/jg3-l chapter 28 regulator r01uh0165ej0700 rev.7.00 page 900 of 1113 sep 22, 2011 28.2 operation the regulator connected to v dd always operates in modes other than rt c backup mode (normal operation mode, halt mode, idle1 mode, idle2 mode, stop mode, subclock operation mode, sub-idle mode, or during reset). the regulator connected to rv dd always operates in all modes. the output voltage of the regulator can be lowered in th e stop mode, subclock operation mode, and sub-idle mode to reduce the power consumption. for details, see chapter 23 standby function . be sure to connect a capacitor (4.7 f (recommended value)) to the regc pin to stabilize the regulator output. a diagram of the regulator pin connection method is shown below. figure 28-3. regc pin connection reg input voltage = 2.7 to 3.6 v voltage supply to oscillator/internal logic v dd regc 4.7 f (recommended value) v ss
v850es/jg3-l chapter 29 option byte r01uh0165ej0700 rev.7.00 page 901 of 1113 sep 22, 2011 chapter 29 option byte the option byte is stored at address 000 007ah of the internal flash memory (internal rom area) as 8-bit data. this 8-bit data is used to specify the mode for watchdog ti mer 2, specify whether to enable or disable stopping the internal oscillator, and specify the osc illation stabilization time immediately after a reset ends. after a reset ends, the mode for watchdog timer 2, and whether to enable or disabl e stopping the internal oscillator is specified, and the oscillation stabilization time is secured, in accordance with these set values. when writing a program to the v850 es/jg3-l, specify the option data at address 000007ah in the program, referring to 29.1 program example . the data in this area cannot be re written during program execution.
v850es/jg3-l chapter 29 option byte r01uh0165ej0700 rev.7.00 page 902 of 1113 sep 22, 2011 wdt md1 note 0 1 watchdog timer 2 mode setting operation clock (f x /f t /f r ) selectable intwdt2/wdtres mode selectable internal oscillator clock (f r ) fixed wdtres mode fixed rmo pin note 0 1 option to enable/disable stopping internal oscillator by software can be stopped by software cannot be stopped by software wdt md1 note rmo pin note 00 0 resosts2 resosts1 resosts0 address: 0000007ah 2 10 /f x 2 11 /f x 2 12 /f x 2 13 /f x 2 14 /f x 2 15 /f x 2 16 /f x 2 16 /f x res osts2 0 0 0 0 1 1 1 1 selection of oscillation stabilization time (theoretical value) res osts1 0 0 1 1 0 0 1 1 res osts0 0 1 0 1 0 1 0 1 5 mhz setting prohibited setting prohibited 409.6 s 819.2 s 1.638 ms 3.277 ms 6.554 ms 6.554 ms 409.6 s 819.2 s 1.638 ms 3.277 ms 6.554 ms 13.11 ms 26.21 ms 26.21 ms setting prohibited 409.6 s 819.2 s 1.638 ms 3.277 ms 6.554 ms 13.11 ms 13.11 ms f x 2.5 mhz 10 mhz note pd70f3792, 70f3793, 70f3841, 70f3842 only. remarks 1. the wait time after releasing the stop mode or idle2 mode is set by the osts register. for details of the osts register, see 23.2 (3) oscillation stabilizatio n time select register (osts) . 2. f x : main clock oscillation frequency cautions 1. the actual oscillation stabilization time is longer than the theoretical val ue because the overhead time after power-on is taken in to consideration. the actual oscillation stabilization time is the time shown above, plus up to 260 s. 2. be sure to select an oscillation stab ilization time (theoretical value) of 400 s or longer. if it is set to less than 400 s, the internal status becom es unstable and the operation cannot be guaranteed. 3. be sure to set bits 7 and 6 to ?0? only in the pd70f3737 and 70f3738.
v850es/jg3-l chapter 29 option byte r01uh0165ej0700 rev.7.00 page 903 of 1113 sep 22, 2011 29.1 program example the following shows program exampl es when the ca850 is used. #------------------------------------------------------------------------------ # option_bytes #------------------------------------------------------------------------------ .section "option_bytes" //specifies the option byte at address 0000007a.// .byte 0b00000001 -- 0x7a //specifies 0b00000001 as the option byte.// .byte 0b00000000 -- 0x7b //specifies 0b00000000 at address 0000007b.// .byte 0b00000000 -- 0x7c //specifies 0b00000000 at address 0000007c.// .byte 0b00000000 -- 0x7d //specifies 0b00000000 at address 0000007d.// .byte 0b00000000 -- 0x7e //specifies 0b00000000 at address 0000007e.// .byte 0b00000000 -- 0x7f //specifies 0b00000000 at address 0000007f.// caution be sure to specify 6 option bytes in this section. if less than 6 bytes are specified, an error occurs when linking is executed. error message: f4112: illega l "option_bytes" section size. remark set 0x00 to addresses 007bh to 007fh.
v850es/jg3-l chapter 30 flash memory r01uh0165ej0700 rev.7.00 page 904 of 1113 sep 22, 2011 chapter 30 flash memory the v850es/jg3-l incorporates flash memory. ? pd70f3737: 128 kb of flash memory ? pd70f3738: 256 kb of flash memory ? pd70f3792: 384 kb of flash memory ? pd70f3793: 512 kb of flash memory ? pd70f3841: 768 kb of flash memory ? pd70f3842: 1 mb of flash memory flash memory versions offer the following advantages for development environments and mass production applications. { for altering software after the v850es/ jg3-l is soldered onto the target system. { for data adjustment when starting mass production. { for differentiating software according to the specif ication in small scale production of various models. { for facilitating inventory management. { for updating software after shipment. 30.1 features { capacity: 1 m/768 k/512 k/384 k/256 k/128 kb { rewriting method ? rewriting by communication with dedicated flash memory programmer via serial interface (on-board/off-board programming) ? rewriting flash memory by user program (self programming) { flash memory write prohibit f unction supported (security function) { safe rewriting of entire flash memory area by self programming using boot swap function { interrupts can be acknowledged during self programming. { 4-byte/1-clock access (when instruction is fetched)
v850es/jg3-l chapter 30 flash memory r01uh0165ej0700 rev.7.00 page 905 of 1113 sep 22, 2011 30.2 memory configuration the v850es/jg3-l internal flash memory area is divide d into 64 or 96 or 128 blocks and can be erased in block units. all the blocks can also be erased at once. when the boot swap function is used, the physical memory located at the addresses of blocks 0 to 15 is replaced by the physical memory located at the addresses of blocks 16 to 31. for details of t he boot swap function, see 30.5 rewriting by self programming . figure 30-1. flash memory mapping (1/2) (a) pd70f3737, 70f3738 block 0 (2 kb) block 1 (2 kb) block 15 (2 kb) block 17 (2 kb) block 31 (2 kb) block 32 (2 kb) block 16 (2 kb) block 63 (2 kb) block 125 (2 kb) block 127 (2 kb) block 126 (2 kb) block 0 (2 kb) block 1 (2 kb) block 15 (2 kb) block 17 (2 kb) block 31 (2 kb) block 32 (2 kb) block 16 (2 kb) block 63 (2 kb) 00007ffh 0000800h 0000fffh 0001000h 00087ffh 0008800h 0008f00h 0009000h 000f7ffh 000f800h 000ffffh 0010000h 00107ffh 0010800h 001ffffh 0020000h 001f7ffh 001f800h 003ffffh 003f800h 003f7ffh 003f000h 003efffh 003e800h 003e7ffh 00077ffh 0007800h 0007fffh 0008000h 0000000h pd70f3737 (128 kb) pd70f3738 (256 kb) note 1 note 2 ? notes 1. area to be replaced with the boot area by the boot swap function 2. boot area
v850es/jg3-l chapter 30 flash memory r01uh0165ej0700 rev.7.00 page 906 of 1113 sep 22, 2011 figure 30-1. flash memory mapping (2/2) (b) pd70f3792, 70f3793, 70f3841, 70f3842 pd70f3792 (384 kb) pd70f3793 (512 kb) ? pd70f3841 (768 mb) pd70f3842 (1 mb) ? note 1 note 2 block 0 (4 kb) block 1 (4 kb) block 7 (4 kb) block 9 (4 kb) block 15 (4 kb) block 16 (4 kb) block 8 (4 kb) block 95 (4 kb) block 0 (4 kb) block 1 (4 kb) block 7 (4 kb) block 9 (4 kb) block 15 (4 kb) block 16 (4 kb) block 8 (4 kb) block 95 (4 kb) block 0 (4 kb) block 1 (4 kb) block 7 (4 kb) block 9 (4 kb) block 15 (4 kb) block 16 (4 kb) block 8 (4 kb) block 95 (4 kb) block 0 (4 kb) block 1 (4 kb) block 7 (4 kb) block 9 (4 kb) block 15 (4 kb) block 16 (4 kb) block 8 (4 kb) block 95 (4 kb) 0000fffh 0001000h 0001fffh 0002000h 0008fffh 0009000h 0009fffh 000a000h 000efffh 000f000h 000ffffh 0010000h 0010fffh 0011000h 005ffffh 0060000h 005efffh 005f000h 0006fffh 0007000h 0007fffh 0008000h 0000000h 007ffffh 007f000h 0080000h 007efffh 00bffffh 00bf000h 00c0000h 00befffh 00fffffh 00ff000h 00fefffh block 127 (4 kb) block 127 (4 kb) block 127 (4 kb) block 191 (4 kb) block 191 (4 kb) block 255 (4 kb) notes 1. area to be replaced with the boot area by the boot swap function 2. boot area
v850es/jg3-l chapter 30 flash memory r01uh0165ej0700 rev.7.00 page 907 of 1113 sep 22, 2011 30.3 functional outline the internal flash memory of the v850es/jg3-l can be re written by using the rewrit e function of the dedicated flash memory programmer, regardless of whether the v850es/jg3-l has already b een mounted on the target system or not (off-board/on-board programming). in addition, a security function that prohi bits rewriting the user program written to the internal flash memory is also supported, so that the program c annot be changed by an unauthorized person. the rewrite function using the user program (self programmi ng) is ideal for an applicati on where it is assumed that the program will be changed after production/shipment of the target system. a boot swap function that rewrites the entire flash memory area safely is also supported. in addition, interrupt servicing can be executed during self programming, so that the flash memory can be rewritten under various conditions, such as while communicating with an external device. table 30-1. rewrite method rewrite method functional outline operation mode on-board programming flash memory can be rewritten after the device is mounted on the target system, by using a dedicated flash memory programmer. off-board programming flash memory can be rewritten before the device is mounted on the target system, by using a dedicated flash memory programmer and a dedicated program adapter board (fa series). flash memory programming mode self programming flash memory can be rewritten by executing a user program that has been written to the flash memory in advance by means of off-board/on-board programming. (during self-programming, instructions cannot be fetched from or data access cannot be made to the internal flash memory area. therefore, the rewrite program must be transferred to the internal ram or external memory in advance.) normal operation mode remark the fa series is a product of na ito densei machida mfg. co., ltd.
v850es/jg3-l chapter 30 flash memory r01uh0165ej0700 rev.7.00 page 908 of 1113 sep 22, 2011 table 30-2. basic functions support ( : supported, : not supported) function functional outline on-board/off-board programming self programming blank check the erasure status of the entire memory is checked. chip erasure the contents of the entire memory area are erased all at once. note block erasure the contents of specified memory blocks are erased. program writing to specified addresses, and a verify check to see if the write level is secured, are performed. verify/checksum data read from the flash memory is compared with data transferred from the flash memory programmer. (can be read by user program) read data written to the flash memory is read. security setting use of the block erase command, chip erase command, program command, and read command, and boot area rewrite, are prohibited. (supported only when setting is changed from enable to disable) note this is possible by selecting the entire memory area for the block erase function. the following table lists the security functions. the chip erase command prohibit, block erase command prohibit, program command prohibit, read command prohibit, and boot block cluster rewrite prohibit functions are enabled by default after shipment, and security settings can be specified only by rewriting via on-board/off-board programming. each security function can be used in combination with the others at the same time. table 30-3. security functions function function outline chip erase command prohibit execution of block erase and chip erase commands on all the blocks is prohibited. once prohibition is set, setting of prohibition cannot be initialized because the chip erase command cannot be executed. block erase command prohibit execution of a block erase command on all blocks is prohibited. setting of prohibition can be initialized by execution of a chip erase command. program command prohibit execution of program and block erase commands on all the blocks are prohibited. setting of prohibition can be initialized by execution of the chip erase command. read command prohibit execution of read command on all the blocks is prohibited. setting of prohibition can be initialized by execution of the chip erase command. boot block cluster rewrite prohibit boot block clusters from block 0 to the specified last block can be protected. the protected boot block clusters cannot be rewritten (erased and written). setting of prohibition cannot be initialized by execution of the chip erase command. the following can be specified as the last block: pd70f3737: block 63 pd70f3738: block 127 pd70f3792: block 95 pd70f3793: block 127 pd70f3841: block 191 pd70f3842: block 255
v850es/jg3-l chapter 30 flash memory r01uh0165ej0700 rev.7.00 page 909 of 1113 sep 22, 2011 table 30-4. security settings erase, write, read operations when each security is set ( : executable, : not executable, ? : not supported) notes on security setting function on-board/ off-board programming self programming on-board/ off-board programming self programming chip erase command prohibit chip erase command: block erase command: program command: note 1 read command: chip erasure: ? block erasure (flashblockerase): write (flashwordwrite): read (flashwordread): setting of prohibition cannot be initialized. block erase command prohibit chip erase command: block erase command: program command: read command: chip erasure: ? block erasure (flashblockerase): write (flashwordwrite): read (flashwordread): setting of prohibition can be initialized by chip erase command. program command prohibit chip erase command: block erase command: program command: read command: chip erasure: ? block erasure (flashblockerase): write (flashwordwrite): read (flashwordread): setting of prohibition can be initialized by chip erase command. read command prohibit chip erase command: block erase command: program command: read command: chip erasure: ? block erasure (flashblockerase): write (flashwordwrite): read (flashwordread): setting of prohibition can be initialized by chip erase command. boot area rewrite prohibit chip erase command: block erase command: note 2 program command: note 2 read command: chip erasure: ? block erasure (flashblockerase): note 2 write (flashwordwrite): note 2 read (flashwordread): setting of prohibition cannot be initialized. supported only when setting is changed from enable to prohibit. notes 1. in this case, since the erase command is invalid, data that differs from the data already written in the flash memory cannot be written. 2. this can be executed for other than boot block clusters.
v850es/jg3-l chapter 30 flash memory r01uh0165ej0700 rev.7.00 page 910 of 1113 sep 22, 2011 30.4 rewriting by dedicate d flash memory programmer the flash memory can be rewritten by using a dedicat ed flash memory programmer after the v850es/jg3-l is mounted on the target system (on-board programming). by combining the dedicated flash memory programmer with a dedicated program adapter (fa series), the flash memo ry can also be rewritten before the device is mounted on the target system (off-board programming). 30.4.1 programming environment the following shows the environment required for writing programs to the flash memory of the v850es/jg3-l. figure 30-2. environment required for writing programs to flash memory host machine rs-232c usb dedicated flash memory programmer v850es/jg3-l flmd1 note flmd0 v dd v ss reset uarta0/csib0/csib3 note connect the flmd1 pin to the flash memory programmer or connect to gnd via a pull-down resistor on the board. a host machine is required for controlling the dedicated flas h memory programmer. in some cases, however, it can be used stand-alone. for details, see the user?s manual of the dedicated flash memory programmer. uarta0, csib0, or csib3 is used for the interface between the dedicated flash memory programmer and the v850es/jg3-l to perform writing, erasing, etc. a dedicat ed program adapter (fa series) is required for off-board writing. the following products are recommended: ? fa-70f3738gc-ueu-rx (gc-ueu type) (already wired) ? fa-70f3738gf-gas-rx (gf-gas type) (already wired) ? fa-70f3738f1-cah-rx (f1-cah type) (already wired) ? fa-70f3793gc-ueu-rx (gc-ueu type) (already wired) ? fa-70f3793f1-cah-rx (f1-cah type) (already wired) ? fa-100gc-ueu-b (gc-ueu type) (not wired: wiring required) ? fa-100gf-gas-b (gf-gas type) (not wired: wiring required) remark the fa series is a product of na ito densei machida mfg. co., ltd.
v850es/jg3-l chapter 30 flash memory r01uh0165ej0700 rev.7.00 page 911 of 1113 sep 22, 2011 30.4.2 communication mode communication between the dedicated flash memory pr ogrammer and the v850es/jg3-l is performed by serial communication using the uarta0, csib0, or csib3 interfaces of the v850es/jg3-l. (1) uarta0 transfer rate: 9,600 to 153,600 bps figure 30-3. communication with dedica ted flash memory programmer (uarta0) v850es/jg3-l v dd v ss reset txda0 rxda0 flmd1 flmd1 note flmd0 flmd0 v dd gnd reset rxd txd dedicated flash memory programmer note connect the flmd1 pin to the flash memory programmer or connect to gnd via a pull-down resistor on the board. (2) csib0, csib3 serial clock: 2.4 khz to 5 mhz (msb first) figure 30-4. communication with dedicated flash memory programmer (csib0, csib3) v850es/jg3-l flmd1 note v dd v ss reset sob0, sob3 sib0, sib3 sckb0, sckb3 flmd1 flmd0 flmd0 v dd gnd reset si so sck dedicated flash memory programmer note connect the flmd1 pin to the flash memory programmer or connect to gnd via a pull-down resistor on the board.
v850es/jg3-l chapter 30 flash memory r01uh0165ej0700 rev.7.00 page 912 of 1113 sep 22, 2011 (3) csib0 + hs, csib3 + hs serial clock: 2.4 khz to 5 mhz (msb first) the v850es/jg3-l operates as a slave. figure 30-5. communication with dedicated flash memory programmer (csib0 + hs, csib3 + hs) v850es/jg3-l v dd v ss reset sob0, sob3 sib0, sib3 sckb0, sckb3 pcm0 v dd flmd1 flmd1 note flmd0 flmd0 gnd reset si so sck hs dedicated flash memory programmer note connect the flmd1 pin to the flash memory programmer or connect to gnd via a pull-down resistor on the board.
v850es/jg3-l chapter 30 flash memory r01uh0165ej0700 rev.7.00 page 913 of 1113 sep 22, 2011 30.4.3 interface the dedicated flash memory programmer outputs the transfer clock, and the v850es/jg3-l operates as a slave. when the pg-fp5 is used as the dedicated flash memory programmer, it generates t he following signals for the v850es/jg3-l. for details, refer to the pg-fp5 user?s manual (u18865e) . table 30-5. signal connections of dedi cated flash memory programmer (pg-fp5) pg-fp5 v850es/jg3-l processing for connection signal name i/o pin function pin name uarta0 csib0, csib3 csib0 + hs, csib3 + hs flmd0 output write enable/disable flmd0 flmd1 output write enable/disable flmd1 note 1 note 1 note 1 vdd ? v dd voltage generation/voltage monitor v dd gnd ? ground v ss clk output clock output to v850es/jg3-l x1, x2 note 2 note 2 note 2 reset output reset signal reset si/rxd input receive signal sob0, sob3/ txda0 so/txd output transmit signal sib0, sib3/ rxda0 sck output transfer clock sckb0, sckb3 hs input handshake signal for csib0 + hs, csib3 + hs communication pcm0 notes 1. for off-board programming, wire these pins as shown in figures 30-6 and 30-7, or connect them to gnd via a pull-down resistor on board. for on-board progra mming, wire these pins as shown in figure 30-12. 2. to supply a clock to the v850es/jg 3-l, mount an oscillator on the board, or connect the clk signal of the pg-fp5 with the x1 signal of the v850es/jg3-l. remark : must be connected. : does not have to be connected.
v850es/jg3-l chapter 30 flash memory r01uh0165ej0700 rev.7.00 page 914 of 1113 sep 22, 2011 table 30-6. wiring of v850es/jg 3-l flash writing adapters (fa-10 0gf-gas-b, fa-100gc-ueu-b) (1/2) flash memory programmer (fg-fp5) connection pin csib0 + hs used csib0 used uarta0 used pin no. pin no. pin no. signal name i/o pin function name of fa board pin pin name gf gc pin name gf gc pin name gf gc si/rxd input receive signal si p41/sob0/ scl01 25 23 p41/sob0/ scl01 25 23 p30/txda0/ sob4 27 25 so/txd output transmit signal so p40/sib0/ sda01 24 22 p40/sib0/ sda01 24 22 p31/rxda0/ intp7/sib4 28 26 sck output transfer clock sck p42/sckb0 26 24 p42/sckb0 26 24 not needed ? ? x1 not needed ? ? not needed ? ? not needed ? ? clk output clock to v850es/jg3-l x2 not needed ? ? not needed ? ? not needed ? ? /reset output reset signal /reset reset 16 14 reset 16 14 reset 16 14 flmd0 output write voltage flmd0 flmd0 10 8 flmd0 10 8 flmd0 10 8 flmd1 output write voltage flmd1 pdl5/ad5/ flmd1 78 76 pdl5/ad5/ flmd1 78 76 pdl5/ad5/ flmd1 78 76 hs input handshake signal for csi0 + hs communication reserve/ hs pcm0/wait 63 61 not needed ? ? not needed ? ? v dd 11 9 v dd 11 9 v dd 11 9 ev dd 36, 72 34, 70 ev dd 36, 72 34, 70 ev dd 36, 72 34, 70 rv dd note ? 17 rv dd note ? 17 rv dd note ? 17 av ref0 31av ref0 3 1 av ref0 3 1 vdd ? vdd voltage generation/ voltage monitor vdd av ref1 75av ref1 7 5 av ref1 7 5 v ss 13 11 v ss 13 11 v ss 13 11 av ss 42av ss 4 2 av ss 4 2 gnd ? ground gnd ev ss 35, 71 33, 69 ev ss 35, 71 33, 69 ev ss 35, 71 33, 69 note pd70f3792, 70f3793, 70f 3841, 70f3842 only caution be sure to connect the regc pin to gnd via a 4.7 f (recommended value) capacitor. remark gf: 100-pin plastic lqfp (14 20) gc: 100-pin plastic lqfp (fine pitch) (14 14)
v850es/jg3-l chapter 30 flash memory r01uh0165ej0700 rev.7.00 page 915 of 1113 sep 22, 2011 table 30-6. wiring of v850es/jg3- l flash writing adapters (fa-100gf-gas-b and fa-100gc-ueu-b) (2/2) flash memory programmer (fg-fp5) connection pin csib3 + hs used csib3 used pin no. pin no. signal name i/o pin function name of fa board pin pin name gf gc pin name gf gc si/rxd input receive signal si p911/a11/sob3 56 54 p911/a11/sob3 56 54 so/txd output transmit signal so p910/a10/sib3 55 53 p910/a10/sib3 55 53 sck output transfer clock sck p912/a12/sckb3 57 55 p912/a12/sckb3 57 55 x1 not needed ? ? not needed ? ? clk output clock to v850es/jg3-l x2 not needed ? ? not needed ? ? /reset output reset signal /reset reset 16 14 reset 16 14 flmd0 output write voltage flmd0 flmd0 10 8 flmd0 10 8 flmd1 output write voltage flmd1 pdl5/ad5/flmd1 78 76 pdl5/ad5/flmd1 78 76 hs input handshake signal for csi0 + hs communication reserve/hs pcm0/wait 63 61 not needed ? ? v dd 11 9 v dd 11 9 ev dd 36, 72 34, 70 ev dd 36, 72 34, 70 rv dd note ? 17 rv dd note ? 17 av ref0 3 1 av ref0 3 1 vdd ? vdd voltage generation/ voltage monitor vdd av ref1 7 5 av ref1 7 5 v ss 13 11 v ss 13 11 av ss 4 2 av ss 4 2 gnd ? ground gnd ev ss 35, 71 33, 69 ev ss 35, 71 33, 69 note pd70f3792, 70f3793, 70f 3841, 70f3842 only caution be sure to connect the regc pin to gnd via a 4.7 f (recommended value) capacitor. remark gf: 100-pin plastic lqfp (14 20) gc: 100-pin plastic lqfp (fine pitch) (14 14)
v850es/jg3-l chapter 30 flash memory r01uh0165ej0700 rev.7.00 page 916 of 1113 sep 22, 2011 figure 30-6. wiring example of v850es/jg3-l flash writin g adapter (fa-100gf-gas-b) (in csib0 + hs mode) (1/2) v850es/jg3-l rfu-3 rfu-2 vde flmd1 flmd0 rfu-1 si so sck /reset v pp reserve/hs clkout vdd gnd gnd vdd gnd vdd vdd gnd 1 5 10 15 20 25 30 80 75 70 65 60 55 51 31 35 40 45 50 100 95 90 85 81 note 3 note 4 note 2 note 1 connect this pin to vdd. connect this pin to gnd. 4.7 f
v850es/jg3-l chapter 30 flash memory r01uh0165ej0700 rev.7.00 page 917 of 1113 sep 22, 2011 figure 30-6. wiring example of v850es/jg3-l flash writin g adapter (fa-100gf-gas-b) (in csib0 + hs mode) (2/2) notes 1. corresponding pins when csib3 is used. 2. wire the flmd1 pin as shown below (recommended), or connect it to gnd via a pull-down resistor on board. 3. create an oscillator on the flash writing adapter (shown in broken lines) and supply a clock. here is an example of the oscillator. example: x1 x2 4. corresponding pins when uarta0 is used. caution do not input a high level to the drst pin. remarks 1. the pins that are not used in flash memory pr ogramming remain in the same status as that immediately after a reset ends. handle the pins not shown in accordance with the handling of unused pins (see 2.3 pin i/o circuit types, i/o buffer power supplies, and connection of unused pins ). 2. this adapter is for a 100-pin plastic lqfp package.
v850es/jg3-l chapter 30 flash memory r01uh0165ej0700 rev.7.00 page 918 of 1113 sep 22, 2011 figure 30-7. wiring example of v850es/jg3-l flash writin g adapter (fa-100gc-ueu-b) (in csib0 + hs mode) (1/2) v850es/jg3-l rfu-3 rfu-2 vde flmd1 flmd0 rfu-1 si so sck /reset v pp reserve/hs clkout vdd gnd gnd vdd gnd vdd vdd gnd 1 5 10 15 20 25 75 70 65 60 55 51 26 30 35 40 45 50 100 95 90 85 80 76 note 3 note 5 note 2 note 1 note 4 connect this pin to vdd. connect this pin to gnd. 4.7 f
v850es/jg3-l chapter 30 flash memory r01uh0165ej0700 rev.7.00 page 919 of 1113 sep 22, 2011 figure 30-7. wiring example of v850es/jg3- l flash writing adapte r (fa-100gc-ueu-b) (in csib0 + hs mode) (2/2) notes 1 . corresponding pins when csib3 is used. 2. wire the flmd1 pin as shown below (recommended) , or connect it to gnd via a pull-down resistor on board. 3. create an oscillator on the flash writing adapter (shown in broken lines) and supply a clock. here is an example of the oscillator. example: x1 x2 4. corresponding pins when uarta0 is used. 5. pd70f3792, 70f3793, 70f3841, 70f3842 only. caution do not input a high level to the drst pin. remarks 1. the pins that are not used in flash memory programming remain in the same status as that immediately after a reset ends. handle the pins not shown in accordance with the handling of unused pins (see 2.3 pin i/o circuit types, i/o bu ffer power supplies, and connection of unused pins ). 2. this adapter is for a 100-pin plastic lqfp package.
v850es/jg3-l chapter 30 flash memory r01uh0165ej0700 rev.7.00 page 920 of 1113 sep 22, 2011 30.4.4 flash memory control the following shows the procedure for manipulating the flash memory. figure 30-8. procedure for manipulating flash memory start select communication system manipulate flash memory end? yes supply flmd0 pulse no end switch to flash memory programming mode
v850es/jg3-l chapter 30 flash memory r01uh0165ej0700 rev.7.00 page 921 of 1113 sep 22, 2011 30.4.5 selection of communication mode in the v850es/jg3-l, the communication mode is selected by inputting pulses (12 pulses max.) to the flmd0 pin after switching to the flash memory programming mode. the flmd0 pulse is generated by the dedicated flash memory programmer. the following shows the relationship between the number of pulses and the communication mode. figure 30-9. selection of communication mode v dd v dd reset (input) flmd1 (input) flmd0 (input) rxda0 (input) txda0 (output) v ss v dd v ss v dd v ss v dd v ss v dd v ss v dd v ss (note) power on oscillation stabilized communication mode selected flash control command communication (erasure, write, etc.) reset ends note the number of clocks is as follows according to the communication mode. flmd0 pulse communication mode remarks 0 uarta0 communication rate: 9,600 bps (after reset), lsb first 8 csib0 v850es/jg3-l performs slave operation, msb first 9 csib3 v850es/jg3-l performs slave operation, msb first 11 csib0 + hs v850es/jg3-l performs slave operation, msb first 12 csib3 + hs v850es/jg3-l performs slave operation, msb first other rfu setting prohibited
v850es/jg3-l chapter 30 flash memory r01uh0165ej0700 rev.7.00 page 922 of 1113 sep 22, 2011 30.4.6 communication commands the v850es/jg3-l communicates with the dedicated flash memory programmer by means of commands. the signals sent from the dedicated flas h memory programmer to the v850es/ jg3-l are called ?commands?. the response signals sent from the v850es/jg3-l to the dedicated flash memory programmer are called ?response commands?. figure 30-10. communication commands v850es/jg3-l command response command dedicated flash memory programmer the following shows the commands for flash memory contro l in the v850es/jg3-l. all of these commands are issued from the dedicated flash memory progra mmer, and the v850es/jg3-l performs the processing corresponding to the commands. table 30-7. flash memory control commands support classification command name csib0, csib3 csib0 + hs, csib3 + hs uarta0 function blank check block blank check command checks if the contents of the memory in the specified block have been correctly erased. chip erase command erases the contents of the entire memory. erase block erase command erases the contents of the memory of the specified block. write program command writes the specified address range, and executes a contents verify check. verify command compares the contents of memory in the specified address range with data transferred from the flash memory programmer. verify checksum command reads the checksum in the specified address range. read read command reads the data written to flash memory. silicon signature command reads silicon signature information. system setting, control security setting command prohibits the chip erase command, block erase command, program command, read command, and boot area rewrite.
v850es/jg3-l chapter 30 flash memory r01uh0165ej0700 rev.7.00 page 923 of 1113 sep 22, 2011 30.4.7 pin connection in on-board programming when performing on-board writing, mount a connector on t he target system to connect to the dedicated flash memory programmer. in the flash memory programming mode, all the pins not used for flash memory programming become the same status as that immediately after rese t. therefore, pin handling is required when the external device does not acknowledge the status immediately after a reset. (1) flmd0 pin in the normal operation mo de, input a voltage of v ss level to the flmd0 pin. in the flash memory programming mode, supply a write voltage of v dd level to the flmd0 pin. because the flmd0 pin serves as a write protection pin in the self programming mode, a voltage of v dd level must be supplied to the flmd0 pin via port control, etc., before writing to the flash memory. for details, see 30.5.5 (1) flmd0 pin . figure 30-11. flmd0 pin connection example v850es/jg3-l flmd0 dedicated flash memory programmer connection pin pull-down resistor (r flmd0 ) (2) flmd1 pin when 0 v is input to the flmd0 pin, t he flmd1 pin does not function. when v dd is supplied to the flmd0 pin, the flash memory programming mode is entered, so 0 v must be input to the flmd1 pin. the following shows an example of the connection of the flmd1 pin. figure 30-12. flmd1 pin connection example flmd1 pull-down resistor (r flmd1 ) other device v850es/jg3-l caution if the v dd signal will be input to the flmd1 pin from another device during on-board writing and immediately after reset, isolate this signal.
v850es/jg3-l chapter 30 flash memory r01uh0165ej0700 rev.7.00 page 924 of 1113 sep 22, 2011 table 30-8. relationship between flmd0 and flmd1 pins and operation mode immediately after reset ends flmd0 flmd1 operation mode 0 don?t care normal operation mode v dd 0 flash memory programming mode v dd v dd setting prohibited (3) serial interface pin the following shows the pins used by each serial interface. table 30-9. pins used by serial interfaces serial interface pins used uarta0 txda0, rxda0 csib0 sob0, sib0, sckb0 csib3 sob3, sib3, sckb3 csib0 + hs sob0, sib0, sckb0, pcm0 csib3 + hs sob3, sib3, sckb3, pcm0 when connecting a dedicated flash memory programmer to a serial interface pin that is connected to another device on-board, care should be taken to avoid conflic t of signals and malfunction of the other device. (a) conflict of signals when the dedicated flash memory programmer (output) is connected to a serial interface pin (input) that is connected to another device (output ), a conflict of signals occurs. to avoid the conflict of signals, isolate the connection to the other device or set the other device to the out put high-impedance status. figure 30-13. conflict of signals (serial interface input pin) v850es/jg3-l input pin conflict of signals dedicated flash memory programmer connection pins other device output pin in the flash memory programming mode, the signal that the dedicated flash memory programmer sends out conflicts with signals another device outputs. therefore, isolate the signals on the other device side.
v850es/jg3-l chapter 30 flash memory r01uh0165ej0700 rev.7.00 page 925 of 1113 sep 22, 2011 (b) malfunction of other device when the dedicated flash memory prog rammer (output or input) is conn ected to a serial interface pin (input or output) that is connected to another device (input), the signal is output to the other device, causing the device to malfunction. to avoid this, isolate the connection to the other device. figure 30-14. malfunction of other device v850es/jg3-l pin dedicated flash memory programmer connection pin other device input pin in the flash memory programming mode, if the signal the v850es/jg3-l outputs affects the other device, isolate the signal on the other device side. v850es/jg3-l pin dedicated flash memory programmer connection pin other device input pin in the flash memory programming mode, if the signal the dedicated flash memory programmer outputs affects the other device, isolate the signal on the other device side.
v850es/jg3-l chapter 30 flash memory r01uh0165ej0700 rev.7.00 page 926 of 1113 sep 22, 2011 (4) reset pin when the reset signals of the dedicated flash memory pr ogrammer are connected to the reset pin that is connected to the reset signal generator on-board, a conflic t of signals occurs. to avoid the conflict of signals, isolate the connection to the reset signal generator. when a reset signal is input from the user system in the flash memory programming mode, the programming operation will not be performed correctly. therefore, do not input signals other than the reset signals from the dedicated flash memory programmer. figure 30-15. conflict of signals (reset pin) v850es/jg3-l reset dedicated flash memory programmer connection pin reset signal generator conflict of signals output pin in the flash memory programming mode, the signal the reset signal generator outputs conflicts with the signal the dedicated flash memory programmer outputs. therefore, isolate the signals on the reset signal generator side. (5) port pins (including nmi) when the system shifts to the flash memory programmi ng mode, all the pins t hat are not used for flash memory programming are in the same status as that immediately after reset. if the external device connected to each port does not reco gnize the status of the port immediately after reset, pins require appropriate processing, such as connecting to v dd via a resistor or connecting to v ss via a resistor. (6) other signal pins connect x1, x2, xt1, xt2, and regc in the same status as that in t he normal operation mode. during flash memory programming, input a low level to the drst pin or leave it o pen. do not input a high level. (7) power supply supply the same power (v dd , v ss , ev dd , ev ss , av ref0 , av ref1 , av ss , rv dd ) as in normal operation mode. remark for details about pin connection, see the pg-fp5 user?s manual (u18865e) .
v850es/jg3-l chapter 30 flash memory r01uh0165ej0700 rev.7.00 page 927 of 1113 sep 22, 2011 30.5 rewriting by self programming 30.5.1 overview the v850es/jg3-l supports a flash macr o service that allows the user prog ram to rewrite the internal flash memory by itself. by using this interface and a self prog ramming library that is used to rewrite the flash memory with a user application program, the flash memory can be rewri tten by a user application transferred in advance to the internal ram or external memory. consequently, the user program can be upgraded and constant data note can be rewritten in the field. note be sure not to allocate the program code to the blo ck where the constant data of the rewriting target is allocated. see 30.2 memory configuration for the block configuration. figure 30-16. concept of self programming application program self programming library flash macro service flash memory flash function execution flash information erase, write
v850es/jg3-l chapter 30 flash memory r01uh0165ej0700 rev.7.00 page 928 of 1113 sep 22, 2011 30.5.2 features (1) secure self programming (boot swap function) the v850es/jg3-l supports a boot sw ap function that can be used to exchange the physical memory of blocks 0 to 15 with the physical memory of blocks 16 to 31. by writing the start program to be rewritten to blocks 16 to 31 in advance and then swapping the phy sical memory, the entire area can be safely rewritten even if a power failure occurs during rewriting because t he correct user program always exists in blocks 0 to 15. figure 30-17. rewriting entire memory area (boot swap) block 0 block 1 : block 15 block 16 block 17 : block 31 block 32 : last block block 0 block 1 : block 15 block 16 block 17 : block 31 block 32 : last block block 0 block 1 : block 15 block 16 block 17 : block 31 block 32 : last block boot swap rewriting blocks 16 to 31 (2) interrupt support instructions cannot be fetched from the flash memory during self-programming. consequently, a user handler written to the flash memory cannot be used even if an interrupt has occurred. therefore, to use an interrupt durin g self-programming in the v850es/jg3-l, execution must jump to a specific address note in the internal ram. write a branch instruct ion to execute the user interrupt servicing at the specific address note in the internal ram. note nmi interrupt: start address of internal ram maskable interrupt: start address of internal ram + 4 addresses caution to execute intkr interrupt servicing during self programming, set the interrupt mask flag to disable interrupts (kric.krmk bit = 1) and poll the interrupt request flag (kric.krif flag). setting th e kric.krmk bit to 0 (to enable interrupts) during self programming is prohibited. for details of interrupt servicing, see 21.3.4 interrupt control register (xxicn).
v850es/jg3-l chapter 30 flash memory r01uh0165ej0700 rev.7.00 page 929 of 1113 sep 22, 2011 30.5.3 standard self programming flow the entire processing to rewrite the flash memory by flas h self programming is illustrated below. for details, see the flash memory self-programming library user?s manual (u17819e) . figure 30-18. standard self programming flowchart flash environment initialization processing erase processing write processing internal verify processing flash memory manipulation flash environment end processing end of processing all blocks end? ? disable accessing flash area ? disable stopping clock ? disable setting of a standby mode other than the halt mode ? disable dma transfer yes no
v850es/jg3-l chapter 30 flash memory r01uh0165ej0700 rev.7.00 page 930 of 1113 sep 22, 2011 30.5.4 flash functions table 30-10. flash function list function name outline support flashinit self-programming library initialization flashenv flash environment start/end flashflmdcheck flmd pin check flashstatuscheck hardware proc essing execution status check flashblockerase block erase flashwordwrite data write flashblockiverify internal verification of block flashblockblankcheck blank check of block flashsetinfo flash information setting flashgetinfo flash information acquisition flashbootswap boot swap execution 30.5.5 pin processing (1) flmd0 pin the flmd0 pin is used to set the operation mode imme diately after a reset ends and to protect the flash memory from being written during self rewriting. it is therefore necessary to k eep the voltage applied to the flmd0 pin at 0 v immediately after a reset ends and a nor mal operation is executed. it is also necessary to apply a voltage of v dd level to the flmd0 pin during the self pr ogramming mode period via port control before the memory is rewritten. when self programming has been completed, the volt age on the flmd0 pin must be returned to 0 v. figure 30-19. mode change timing reset signal flmd0 pin v dd 0 v v dd 0 v self programming mode normal operation mode normal operation mode caution make sure that the flmd0 pin is at 0 v immediately after a reset ends.
v850es/jg3-l chapter 30 flash memory r01uh0165ej0700 rev.7.00 page 931 of 1113 sep 22, 2011 30.5.6 internal resources used the following table lists the internal resources used for self programming. these internal resources can also be used freely for purposes ot her than self programming. table 30-11. internal resources used resource name description stack area an extension of the stack used by the user is used by the library (can be used in both the internal ram and external ram). library code note program entity of library (can be used anywhere other than the flash memory block to be manipulated). application program executed as user application. calls flash functions. maskable interrupt can be used in the user application execution status or self-programming status. to use this interrupt in the self-programming status, since the processing transits to the address of the internal ram start address + 4 addresses, allocate the branch instruction that shifts the processing to the user interrupt servicing at the address of the internal ram start address + 4 addresses in advance. nmi can be used in the user application execution status or self-programming status. to use this interrupt in the self-programming status, since the processing transits to the address of the internal ram start address, allocate the branch instruction that shifts the processing to the user interrupt servicing at the internal ram start address in advance. note for details about the resources used, see the flash memory self-programming library user?s manual .
v850es/jg3-l chapter 31 on-chip debug function r01uh0165ej0700 rev.7.00 page 932 of 1113 sep 22, 2011 chapter 31 on-chip debug function on-chip debugging is debugging executed with the v850es/jg3-l mounted on the target system. by using minicube2, on-chip debugging can be performed with a simple interface. figure 31-1. on-chip de bugging using minicube2 target system v850es/jg3-l minicube2 on-chip debugging can be performed for the v 850es/jg3-l by using the following two methods. ? using the dcu (debug control unit) on-chip debugging is performed by the on-chip dcu in the v850es/jg3-l, with the drst, dck, dms, ddi, and ddo pins used as the debug interface pins. ? not using the dcu on-chip debugging can be performed by minicube2, using the user resources instead of the dcu.
v850es/jg3-l chapter 31 on-chip debug function r01uh0165ej0700 rev.7.00 page 933 of 1113 sep 22, 2011 the following table shows the features of the two on-chip debugging methods. table 31-1. overview of on-chip debugging debugging using dcu debugging without using dcu debug interface pins drst, dck, dms, ddi, ddo ? when uarta0 is used rxd0, txd0 ? when csib0 is used sib0, sob0, sckb0, hs (pcm0) ? when csib3 is used sib3, sob3, sckb3, hs (pcm0) allocating user resources not required required hardware break function 2 points 2 points internal rom area 4 points 4 points software break function internal ram area 2000 points 2000 points real-time ram monitor function note 1 available available dynamic memory modification (dmm) function note 2 available available mask function reset, nmi, intwdt2, hldrq, wait reset pin rom security function 10-byte id code aut hentication 10-byte id code authentication hardware used minicube, etc. minicube2, etc. trace function not supported. not supported. debug interrupt interface function (dbint) not supported. not supported. notes 1. this is a function which reads out memo ry contents during program execution. 2. this is a function which rewrites ra m contents during program execution.
v850es/jg3-l chapter 31 on-chip debug function r01uh0165ej0700 rev.7.00 page 934 of 1113 sep 22, 2011 31.1 debugging with dcu by using the debug interface pins (drst, dck, dms, ddi, and ddo) to connect the on-chip emulator (minicube), programs can be debugged without us ing user resources other than these pins. 31.1.1 connection circuit example figure 31-2. circuit connection example when debug interface pins are used for communication interface minicube v850es/jg3-l vdd dck dms ddi ddo drst reset flmd0 gnd ev dd dck dms ddi ddo drst note 2 reset flmd0 note 3 ev ss note 1 status target power notes 1. example of pin connection when minicube is not connected 2. a pull-down resistor is provided on chip. 3. for flash memory rewriting
v850es/jg3-l chapter 31 on-chip debug function r01uh0165ej0700 rev.7.00 page 935 of 1113 sep 22, 2011 31.1.2 interface signals the interface signals are described below. (1) drst this is a reset input signal for the on-chip debug uni t. it is a negative-logic signal that asynchronously initializes the debug control unit. minicube raises the drst si gnal when it detects v dd of the target system after the integrated debugger is started, and starts the on-chip debug unit of the device. when the drst signal goes high, a reset signal is also generated in the cpu. when starting debugging by starti ng the integrated debugger, a cpu reset is always generated. (2) dck this is a clock input signal. it supplies a 20 mhz or 10 mhz clock from minicube. in the on-chip debug unit, the dms and ddi signals are sampled at the rising edge of the dck signal, and the data ddo is output at its falling edge. (3) dms this is a transfer mode select signal. the transfe r status in the debug unit changes depending on the level of the dms signal. (4) ddi this is a data input signal. it is sampled in t he on-chip debug unit at the rising edge of dck. (5) ddo this is a data output signal. it is output from the on-chip debug unit at the fa lling edge of the dck signal. (6) ev dd this signal is used to detect vdd of the target system. if vdd of the target system cannot be detected, minicube makes its out put signals (drst, dck, dms, ddi, flmd0, and reset) high-impedance.
v850es/jg3-l chapter 31 on-chip debug function r01uh0165ej0700 rev.7.00 page 936 of 1113 sep 22, 2011 (7) flmd0 the flash self programming function is used to download data to the flash memory via the integrated debugger (id850qb). during flash self programming, the flmd0 pin must be kept high. in addition, connect a pull-down resistor to the flmd0 pin. the flmd0 pin can be controlled in either of the following two ways. <1> to control from minicube connect the flmd0 signal of minicube to the flmd0 pin. in the normal mode, nothing is dr iven by minicube (high impedance). during a break, minicube raises the flmd0 pin to the high level when the download function of the integrated debugger is executed. in other case s, the flmd0 pin is in a high-impedance state. <2> to control from port use this method when executing self-programming. connect any port of the device to the flmd0 pin. the same port as the one used by the user program to realize the flash self programming function may be used. before executing a download, set the port pin con nected to the flmd0 pin to high level on the console of the integrated debugger. upon completion of the download, reset the port pin to low level. for details, refer to the id850qb ver. 3.40 integrated debugger operation user?s manual (u18604e) . (8) reset this is a system reset input pin. if the drst pin is made invalid by the value of the ocdm.ocdm0 bit set by the user program, on-chip debugging cannot be executed. therefore, a reset is executed by minicube, using the reset pin, to make the drst pin valid (initialization). 31.1.3 mask function the reset, nmi, intwdt2, wait, and hldrq signals can be masked. the maskable signals in the integrat ed debugger (id850qb) and the corres ponding v850es/jg3-l functions are listed below. table 31-2. mask functions maskable signals in debugger (id850qb) corresponding v850es/jg3-l functions nmi0 nmi pin input nmi2 non-maskable interrupt request signal (intwdt2) generation stop non-maskable hold hldrq pin input reset reset signal generation by reset pin input, low-voltage detector, clock monitor, or watchdog timer (wdt2) overflow wait wait pin input
v850es/jg3-l chapter 31 on-chip debug function r01uh0165ej0700 rev.7.00 page 937 of 1113 sep 22, 2011 31.1.4 registers (1) on-chip debug m ode register (ocdm) this register is used to specify whether a pin provided with an on-chip debug function is used as an on-chip debug pin or as an ordinary port/peripher al function pin. it also is used to disconnect the internal pull-down resistor of the p05/intp2/drst pin. this register is a special register and can be writt en only in a combination of specific sequences (see 3.4.7 special registers ). the ocdm register can be written only while a lo w level is input to the p05/intp2/drst pin. this register can be read or written in 8-bit or 1-bit units. 0 ocdm0 0 1 operation mode ocdm 0 0 0 0 0 0 ocdm0 after reset: 01h note r/w address: fffff9fch when p05/intp2/drst pin is low: normal operation mode (in which a pin that functions alternately as an on-chip debug function pin is used as a port/peripheral function pin) when p05/intp2/drst pin is high: on-chip debug mode (in which a pin that functions alternately as an on-chip debug function pin is used as an on-chip debug mode pin) selects normal operation mode (in which a pin that functions alternately as on-chip debug function pin is used as a port/peripheral function pin) and disconnects the on-chip pull-down resistor of the p05/intp2/drst pin. < > note reset input sets this register to 01h. after re set by the wdt2res signal, clock monitor (clm), or low-voltage detector (lvi), however, the va lue of the ocdm register is retained. cautions 1. when using the dd i, ddo, dck, and dms pins not as on-chip debug pi ns but as port pins after external reset, one of th e following actions must be taken. ? input a low level to the p05/intp2/drst pin. ? set the ocdm0 bit. in this case, take the following actions. <1> clear the ocdm0 bit to 0. <2> fix the p05/intp2/drst pin to low level until <1> is completed. 2. the p05/intp2/drst pin h as an on-chip pull-d own resistor. this resistor is disconnected when the ocdm0 fl ag is cleared to 0. ocdm0 flag (1: pull-down on, 0: pull-down off) 10 to 100 k (30 k (typ.)) p05/intp2/drst
v850es/jg3-l chapter 31 on-chip debug function r01uh0165ej0700 rev.7.00 page 938 of 1113 sep 22, 2011 31.1.5 operation the on-chip debug function is made invalid under the conditions shown in the table below. when this function is not used, keep the drst pin low until the ocdm.ocdm0 flag is cleared to 0. ocdm0 flag drst pin 0 1 l invalid invalid h invalid valid remark l: low-level input h: high-level input figure 31-3. timing when on-chip debug function is not used low-level input after the ocdm0 bit is cleared, a high level can be input/output. clearing ocdm0 bit releasing reset reset ocdm0 p05/intp2/drst
v850es/jg3-l chapter 31 on-chip debug function r01uh0165ej0700 rev.7.00 page 939 of 1113 sep 22, 2011 31.1.6 cautions (1) if a reset signal is input (from the target system or from an internal reset source) during program execution, the break function may malfunction. (2) even if the reset signal is masked by the mask function, the i/o buffer (port pin) may be reset if a reset signal is input from a pin. (3) the reset signal from a pin for wh ich a break is specified is masked a nd the cpu and peri pheral i/o are not reset. if a pin-based reset or internal reset is generated as soon as the flash memory is rewritten by dmm or read by the ram monitor function whil e the user program is being exec uted, the cpu and peripheral i/o may not be correctly reset. (4) in the on-chip debug mode, the ddo pin is forcibly set to high-level output. (5) on-chip debugging can be used when the supply voltage (v dd ) is in a range of 2.7 to 3.6 v. it cannot be used at less than 2.7 v. (6) in the on-chip debug mode, the output voltage of t he regulator does not decrease even in the low-voltage stop mode, low-voltage subclock mode, or low-voltage sub-idle mode
v850es/jg3-l chapter 31 on-chip debug function r01uh0165ej0700 rev.7.00 page 940 of 1113 sep 22, 2011 31.2 debugging without using dcu the following describes how to implement an on-chip debug function using minicub e2 with pins for uarta0 (rxda0 and txda0), pins for csib0 (sib0, sob0, sckb0, and hs (pcm0)), or pins for csib3 (sib3, sob3, sckb3, and hs (pcm0)) as the debug in terface, without using the dcu. 31.2.1 circuit connection examples figure 31-4. circuit connection example when uart a0/csib0/csib3 is used for communication interface qb-mini2 v850es/jg3-l gnd v dd v dd reset_out rxd/si note 1 vdd txd/so note 1 sck hs clk note 2 flmd1 note 3 flmd0 note 3 reset_in note 4 v ss txda0/sob0/sob3 v dd rxda0/sib0/sib3 sckb0/sckb3 flmd1 flmd0 port x 100 10 k 1 to 10 k 1 k reset signal 10 k 1 to 10 k 1 to 10 k 3 to 10 k 1 to 10 k v dd note 5 v dd v dd hs (pcm0) reset m in ic u b e 2 m in ic u b e 2 reset circuit notes 1. connect txda0/sob0/sob3 (transmit side) of t he v850es/jg3-l to rxd/si (receive side) of the target connector, and txd/so (transmit side) of the target connector to rxda0/sib0/sib3 (receive side) of the v850es/jg3-l. 2. this pin is not used during on-chip debugging. 3. during debugging, this pin is used as an input (unused) pin and can be used for its alternate functions. a pull-down resistor of 100k is connected to this pin in minicube2. 4. this connection is designed assuming that the reset signal is output from an n-ch open-drain buffer (output resistance: 100 or less). 5. the circuit enclosed by a dashed line is designed fo r flash self programming and controls the flmd0 pin via a port. use a port for inputting or outputting the high level. when flash self programming is not performed, the pull-down resistance for the flmd0 pin can be 1 to 10 k . remark see table 31-3 for the pins used when uarta0, csib0, or csib3 is used for communication interface.
v850es/jg3-l chapter 31 on-chip debug function r01uh0165ej0700 rev.7.00 page 941 of 1113 sep 22, 2011 table 31-3. wiring between v850es/jg3-l and minicube2 pin configuration of minicube2 (qb-mini2) wi th csib0-hs with csib3-hs with uarta0 pin no. pin no. pin no. signal name i/o pin function pin name gc gf f1 pin name gc gf f1 pin name gc gf f1 si/r x d input pin to receive commands and data from v850es/jg3-l p41/sob0 23 25 k2 p911/sob3 54 56 h9 p30/txda0 25 27 l3 so/t x d output pin to transmit commands and data to v850es/jg3-l p40/sib0 22 24 k1 p910/sib3 53 55 h10 p31/rxda0 26 28 k3 sck output clock output pin for 3-wire serial communication p42/sckb0 24 26 l2 p912/sckb3 55 57 g11 not needed ? ? ? clk output pin outputting clock signal to v850es/jg3-l not needed ? ? ? not needed ? ? ? not needed ? ? ? reset_ out output pin outputting reset signal to v850es/jg3-l reset 14 16 h3 reset 14 16 h3 reset 14 16 h3 flmd0 output output pin to set v850es/jg3-l to debug mode or programming mode flmd0 8 10 f3 flmd0 8 10 f3 flmd0 8 10 f3 flmd1 output output pin to set programming mode pdl5/flmd1 76 78 a10 pdl5/flmd1 76 78 a10 pdl5/flmd1 76 78 a10 hs input handshake signal for csi0 + hs communication pcm0/wait 61 63 e9 pcm0/wait 61 63 e9 not needed ? ? ? v ss 11 13 note 1 v ss 11 13 note 1 v ss 11 13 note 1 av ss 24c1, c2 av ss 24c1, c2 av ss 24c1, c2 gnd ? ground ev ss 33, 69 35, 71 note 2 ev ss 33, 69 35, 71 note 2 ev ss 33, 69 35, 71 note 2 reset_in input reset input pin on the target system notes 1. g1, g2, j12. g1, g2, j1 2. a6, e5-e7, e11, f5-f7, g5-g7, l1, l5 remark gc: 100-pin plastic lqfp (fine pitch) (14 14) gf: 100-pin plastic lqfp (14 20) ( pd70f3737, 70f3738 only) f1: 121-pin plastic fbga (8 8)
v850es/jg3-l chapter 31 on-chip debug function r01uh0165ej0700 rev.7.00 page 942 of 1113 sep 22, 2011 31.2.2 mask function only reset signals can be masked. the maskable signals in the debugger (id850qb) and the corresponding v850es/jg3-l functions are listed below. table 31-4. mask functions maskable signals in id850qb corresp onding v850es/jg3-l functions nmi0 ? nmi1 ? nmi2 ? stop ? hold ? reset reset signal generation by reset pin input wait ? 31.2.3 allocation of user resources the user must prepare the following resources to per form communication between minicube2 and the target device and implement each debug function . these items need to be set in the user program or using the compiler options. (1) allocation of memory space the shaded portions in figure 31-5 are the areas rese rved for placing the debug monitor program, so user programs and data cannot be allocated to these spaces. these spaces must be secured so as not to be used by the user program. (2) security id setting the id code must be embedded in the area between 0000 070h and 0000079h in figure 31-5, to prevent the memory from being read by an unauthorized person. for details, see 31.3 rom security function .
v850es/jg3-l chapter 31 on-chip debug function r01uh0165ej0700 rev.7.00 page 943 of 1113 sep 22, 2011 figure 31-5. memory spaces where de bug monitor programs are allocated csi/uart receive interrupt vector (4 bytes) reset vector (4 bytes) interrupt vector for debugging (4 bytes) (2 kb) security id area (10 bytes) : debugging area 00fffffh note 1 0000060h 0000290h note 2 0000070h 0000000h access-prohibited area internal rom (16 bytes) note 3 3ffefffh 3ffeff0h access-prohibited area internal ram internal rom area internal ram area notes 1. the address values vary depending on the product. internal rom size address value pd70f3737 128 kb 001f800h to 001ffffh pd70f3738 256 kb 003f800h to 003ffffh pd70f3792 384 kb 005f800h to 005ffffh pd70f3793 512 kb 007f800h to 007ffffh pd70f3841 768 kb 00bf800h to 00bffffh pd70f3842 1 mb 00ff800h to 00fffffh 2. this is the address when csib0 is used. this va lue is 00002f0h when csib 3 is used, and 0000310h when uarta0 is used. 3. the address values vary depending on the product. internal ram size address value pd70f3737 8 kb 3ffd000h pd70f3738 16 kb 3ffb000h pd70f3792 32 kb 3ff7000h pd70f3793 40 kb 3ff5000h pd70f3841 56 kb 3ff1000h pd70f3842 56 kb 3ff1000h
v850es/jg3-l chapter 31 on-chip debug function r01uh0165ej0700 rev.7.00 page 944 of 1113 sep 22, 2011 (3) reset vector the reset vector includes the jump inst ruction for the debug monitor program. [how to secure the reset vector] it is not necessary to secure this area intenti onally. when downloading a program, however, the debugger rewrites the reset vector in accordance with the followi ng cases. if the rewritten pattern does not match the following cases, the debugger generates an error (f0c34 when using the id850qb). (a) when two nop instructions ar e placed in succession from address 0 before rewriting after rewriting 0x0 nop jumps to debug monitor program at 0x0 0x2 nop 0x4 xxxx 0x4 xxxx (b) when two 0xffff values are successively placed from addr ess 0 (already er ased device) before rewriting after rewriting 0x0 0xffff jumps to debug monitor program at 0x0 0x2 0xffff 0x4 xxxx 0x4 xxxx (c) the jr instruction is placed at address 0 (when using ca850) before rewriting after rewriting 0x0 jr disp22 jumps to debug monitor program at 0x0 0x4 jr disp22 - 4 (d) mov32 and jmp are placed in succession from address 0 (when using iar compiler iccv850) before rewriting after rewriting 0x0 mov imm32,reg1 jumps to debug monitor program at 0x0 0x6 jmp [reg1] 0x4 mov imm32,reg1 0xa jmp [reg1] (e) the jump instruction for the debug monitor program is placed at address 0 before rewriting after rewriting jumps to debug monitor program at 0x0 no change
v850es/jg3-l chapter 31 on-chip debug function r01uh0165ej0700 rev.7.00 page 945 of 1113 sep 22, 2011 (4) allocation of area fo r debug monitor program the shaded portions in figure 31-5 ar e the areas where the debug monitor pr ogram is allocated. the monitor program performs initialization processing for t he debug communication interface and run or break processing for the cpu. the internal rom area must be filled with 0xff. this area must not be rewritten by the user program. [how to secure area for the debug monitor program] it is not necessarily required to secure this area if the user program does not use this area. to avoid problems that may occur duri ng debugger startup, however, it is recommended to secure this area in advance, using the compiler. the following shows examples of securing the area, using the renesas electronics compiler ca850. add the assemble source file and link directive code, as shown below. ? assemble source (add the following code as an assemble source file.) -- secures 2 kb space for monitor rom section .section "monitorrom", const .space 0x800, 0xff -- secures interrupt vector for debugging .section "dbg0" .space 4, 0xff -- secures interrupt vector for serial communication -- change the section name according to the serial communication mode used .section "intcb0r" .space 4, 0xff -- secures 16-byte space for monitor ram section .section "monitorram", bss .lcomm monitorramsym, 16, 4 -- defines symbol monitorramsym ? link directive (add the following code to the link directive file.) the following shows an example when using the pd70f3738 (the internal rom is 256 kb (end address is 003ffffh) and internal ram is 16 kb (end address is 3ffefffh)). mromseg : !load ?r v0x03f800{ monitorrom = $progbits ?a monitorrom; }; mramseg : !load ?rw v0x03ffeff0{ monitorram = $nobits ?aw monitorram; };
v850es/jg3-l chapter 31 on-chip debug function r01uh0165ej0700 rev.7.00 page 946 of 1113 sep 22, 2011 (5) allocation of communication serial interface uarta0, csib0, or csib3 is used for communicati on between minicube2 and the target system. the settings related to the serial interface modes are perfo rmed by the debug monitor program, but if the setting is changed by the user program, a communication error may occur. to prevent such a problem from occurring, the communication serial interface must be secured in the user program. [how to secure the communication serial interface] ? on-chip debug mode register (ocdm) for the on-chip debug function using the uarta0, csib 0, or csib3, set the ocdm register to normal mode. be sure to set as follows. ? input low level to the p05/intp2/drst pin. ? set the ocdm0 bit as shown below. <1> clear the ocdm0 bit to 0. <2> fix the p05/intp2/drst pin input to low level until the processing of <1> is complete. ? serial interface registers do not set the registers related to csib0, csib3, or uarta0 in the user program. ? interrupt mask register when csib0 is used, do not mask the transmit end in terrupt (intcb0r). w hen csib3 is used, do not mask the transmit end interrupt (intcb3r). when uart a0 is used, do not mask the reception complete interrupt (intua0r). (a) when csib0 is used cb0ric 0 6543210 7 (b) when csib3 is used cb3ric 0 6543210 7 (c) when uarta0 is used ua0ric 0 6543210 7 remark : don?t care
v850es/jg3-l chapter 31 on-chip debug function r01uh0165ej0700 rev.7.00 page 947 of 1113 sep 22, 2011 ? port registers when uarta0 is used when uarta0 is used, port registers are set by the debug monitor program to make the txda0 and rxda0 pins valid. do not change the following regi ster settings in the user program during debugging. (the same value can be written again.) pfc3 00 6543210 7 pmc3l 11 6543210 7 remark : don?t care ? port registers when csib0 is used when csib0 is used, port registers are set by the debug monitor program to make the sib0, sob0, sckb0, and hs (pcm0) pins valid. do not change the follow ing register settings in the user program during debugging. (the same value can be written again.) (a) sib0, sob0, and sckb0 settings pfc4 00 6543210 7 pmc4 111 6543210 7 (b) hs (pcm0 pin) settings pmcm 0 6543210 7 pcm note 6543210 7 note writing to this bit is prohibited. the port values corresponding to the hs pin are changed by the monitor program according to the debugger status. to spec ify port register settings in 8-bit units, read-modify-write can usually be used in the user program. if an interrupt for debugging occurs before writing, however, an unexpected operation may be performed. remark : don?t care
v850es/jg3-l chapter 31 on-chip debug function r01uh0165ej0700 rev.7.00 page 948 of 1113 sep 22, 2011 ? port registers when csib3 is used when csib3 is used, port registers are set by the debug monitor program to make the sib3, sob3, sckb3, and hs (pcm0) pins valid. do not change the follow ing register settings in the user program during debugging. (the same value can be written again.) (a) sib3, sob3, and sckb3 settings pfc9h 111 6543210 7 pmc9h 11 1 6543210 7 (b) hs (pcm0 pin) settings pmcm 0 6543210 7 pcm note 6543210 7 note writing to this bit is prohibited. the port values corresponding to the hs pin are changed by the monitor program according to the debugger status. to specif y port register settings in 8-bit units, read-modify-write can usually be used in the user program. if an in terrupt for debugging occurs before writing, however, an unexpected operation may be performed. remark : don?t care
v850es/jg3-l chapter 31 on-chip debug function r01uh0165ej0700 rev.7.00 page 949 of 1113 sep 22, 2011 31.2.4 cautions (1) handling of device that was used for debugging do not mount a device that was used for debugging on a mass-produced product, because the flash memory was rewritten during debugging and the number of rewr ites of the flash memory cannot be guaranteed. moreover, do not embed the debug monitor program into mass-produced products. (2) when breaks cannot be executed forced breaks cannot be executed if one of the following conditions is satisfied. ? interrupts are disabled (di) ? interrupts issued for the serial interface, whic h is used for communication between minicube2 and the target device, are masked ? standby mode is entered while standby releas e by a maskable interrupt is prohibited ? mode for communication between minicube2 and the ta rget device is uarta0, and the main clock has been stopped (3) when pseudo real-time ram monitor (rrm ) function and dmm function do not operate the pseudo rrm function and dmm function do not operat e if one of the following conditions is satisfied. ? interrupts are disabled (di) ? interrupts issued for the serial interface, whic h is used for communication between minicube2 and the target device, are masked ? standby mode is entered while standby releas e by a maskable interrupt is prohibited ? mode for communication between minicube2 and the ta rget device is uarta0, and the main clock has been stopped ? mode for communication between minicube2 and the tar get device is uarta0, and a clock different from the one specified in the debugger is used for communication (4) standby release with pseudo rrm and dmm functions enabled the standby mode is released by the pseudo rrm function and dmm function if one of the following conditions is satisfied. ? mode for communication between minicube2 and the target device is csib0 or csib3 ? mode for communication between minicube2 and the ta rget device is uarta0, and the main clock has been supplied. (5) writing to peripheral i/o registers that r equire a specific sequence, using dmm function peripheral i/o registers that require a specific sequence c annot be written by us ing the dmm function. (6) flash self programming if the space where the debug monitor program is allo cated is rewritten by flash self programming, the debugger can no longer operate normally. (7) on-chip debugging can be used when the supply voltage (v dd ) is in a range of 2.7 to 3.6 v. it cannot be used at less than 2.7 v.
v850es/jg3-l chapter 31 on-chip debug function r01uh0165ej0700 rev.7.00 page 950 of 1113 sep 22, 2011 31.3 rom security function 31.3.1 security id the flash memory versions of the v850es/jg3-l perform authent ication using a 10-byte id code to prevent the contents of the flash memory from being read by an unauthorized person durin g on-chip debugging by the on-chip debug emulator. set the id code in the 10-byte internal flash memo ry area from 0000070h to 0000079h to allow the debugger perform id authentication. if the ids match, the security is released and reading t he flash memory and using the on-chip debug emulator are enabled. ? set the 10-byte id code to 0000070h to 0000079h. ? bit 7 of 0000079h is the on-chip debug emulator enable flag. (0: disable, 1: enable) ? when the on-chip debug emulator is started, the debugger requests id input. when the id code input to the debugger and the id code set in 0000070h to 0000079h match, the debugger starts. ? debugging cannot be performed if the on-chip debug emul ator enable flag is 0, even if the id codes match. figure 31-6. security id area 0000079h 0000070h 0000000h security id (10 bytes) caution after the flash memory is erased, 1 is written to the entire area.
v850es/jg3-l chapter 31 on-chip debug function r01uh0165ej0700 rev.7.00 page 951 of 1113 sep 22, 2011 31.3.2 setting the following shows how to set the id code as shown in table 31-5. when the id code is set as shown in table 31-5, the id code input in the configuratio n dialog box of the id850qb is ?123456789abcdef123d4? (the id code is not case-sensitive). table 31-5. id code address value 0x70 0x12 0x71 0x34 0x72 0x56 0x73 0x78 0x74 0x9a 0x75 0xbc 0x76 0xde 0x77 0xf1 0x78 0x23 0x79 0xd4 the id code can be specified in the compiler common options dialog box in pm+.
v850es/jg3-l chapter 32 el ectrical specif ications ( pd70f3737, 70f3738) r01uh0165ej0700 rev.7.00 page 952 of 1113 sep 22, 2011 chapter 32 electrical specifications ( pd70f3737, 70f3738) 32.1 absolute maximum ratings absolute maximum ratings (t a = 25 c) (1/2) parameter symbol conditions ratings unit v dd v dd = ev dd = av ref0 = av ref1 ? 0.5 to +4.6 v ev dd v dd = ev dd = av ref0 = av ref1 ? 0.5 to +4.6 v av ref0 v dd = ev dd = av ref0 = av ref1 ? 0.5 to +4.6 v av ref1 v dd = ev dd = av ref0 = av ref1 ? 0.5 to +4.6 v v ss v ss = ev ss = av ss ? 0.5 to +0.5 v av ss v ss = ev ss = av ss ? 0.5 to +0.5 v supply voltage ev ss v ss = ev ss = av ss ? 0.5 to +0.5 v v i1 p97 to p915, pdh0 to pdh5, pcm0 to pcm3, pct0, pct1, pct4, pct6, pdl0 to pdl15, reset, flmd0 ? 0.5 to ev dd + 0.5 note 1 v v i2 p10, p11 ? 0.5 to av ref1 + 0.5 note 1 v x1 ? 0.5 to v dd + 0.5 note 1 v v i3 x2 ? 0.5 to v ro note 2 + 0.5 note 1 v i4 p02 to p06, p30 to p39, p40 to p42, p50 to p55, p90 to p96 ? 0.5 to +6.0 v input voltage v i5 xt1, xt2 ? 0.5 to v ro note 2 + 0.5 v analog input voltage v ian p70 to p711 ? 0.5 to av ref0 + 0.5 note 1 v notes 1. be sure not to exceed the absolute maximum ratings (max. value) of each supply voltage. 2. on-chip regulator output voltage cautions 1. do not directly connect the output (or i/o) pi ns of ic pro ducts to each other, or to v dd , v cc , and gnd. open-drain pins or open-collector pins , however, can be direct ly connected to each other. direct connection of the output pins between an ic product and an exter nal circuit is possible, if the output pins can be set to the high-impedance state and th e output timing of the external circuit is designed to avoid output conflict. 2. product quality may suffer if the absolute maximu m rating is exceeded even momentarily for any parameter. that is, the ab solute maximum ratings are rate d values at which the product is on the verge of suffering physical damage, a nd therefore the product must be used under conditions that ensure that the abso lute maximum ratings are not exceeded. the ratings and conditions indicated for dc characteristics, ac charact eristics, and operating conditions represent the quality assuran ce range during normal operation. remark unless specified otherwise, the ratings of alternate-fu nction pins are the same as those of port pins.
v850es/jg3-l chapter 32 el ectrical specif ications ( pd70f3737, 70f3738) r01uh0165ej0700 rev.7.00 page 953 of 1113 sep 22, 2011 absolute maximum ratings (t a = 25 c) (2/2) parameter symbol conditions ratings unit per pin 4 ma p02 to p06, p30 to p39, p40 to p42, p50 to p55, p90 to p915, pdh4, pdh5 total of all pins 50 ma per pin 4 ma pcm0 to pcm3, pct0, pct1, pct4, pct6, pdh0 to pdh3, pdl0 to pdl15 total of all pins 50 ma per pin 4 ma p10, p11 total of all pins 8 ma per pin 4 ma output current, low i ol p70 to p711 total of all pins 20 ma per pin ? 4 ma p02 to p06, p30 to p39, p40 to p42, p50 to p55, p90 to p915, pdh4, pdh5 total of all pins ? 50 ma per pin ? 4 ma pcm0 to pcm3, pct0, pct1, pct4, pct6, pdh0 to pdh3, pdl0 to pdl15 total of all pins ? 50 ma per pin ? 4 ma p10, p11 total of all pins ? 8 ma per pin ? 4 ma output current, high i oh p70 to p711 total of all pins ? 20 ma normal operation mode ? 40 to +85 c operating ambient temperature t a flash memory programming mode ? 40 to +85 c storage temperature t stg ? 40 to +125 c cautions 1. do not directly connect the output (or i/o) pins of ic products to each other, or to v dd , v cc , and gnd. open-drain pins or open-collector pins, however, can be directly connected to each other. direct connection of the output pins between an ic product and an external circuit is possible, if the output pins can be set to th e high-impedance state a nd the output timing of the external circuit is designed to avoid output conflict. 2. product quality may suffer if the absolute maximum rati ng is exceeded even momentarily for any parameter. that is, the absolute m aximum ratings are rate d values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum rati ngs are not exceeded. the ratings and conditions indicated fo r dc characteristics, ac characteristics, and operating conditions represent the quality assurance range duri ng normal operation. remark unless specified otherwise, the ratings of alternate-fu nction pins are the same as those of port pins.
v850es/jg3-l chapter 32 el ectrical specif ications ( pd70f3737, 70f3738) r01uh0165ej0700 rev.7.00 page 954 of 1113 sep 22, 2011 32.2 capacitance capacitance (t a = 25 c, v dd = ev dd = av ref0 = av ref1 = v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit i/o capacitance c io f x = 1 mhz unmeasured pins returned to 0 v 10 pf 32.3 operating conditions (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v) supply voltage operating clock conditions v dd ev dd av ref0 , av ref1 unit f xx = 10 to 20 mhz (main clock) regc = 4.7 f, a/d converter operating, d/a converter operating pll mode v f xx = 2.5 to 10 mhz (main clock) regc = 4.7 f, a/d converter operating, d/a converter operating clock-through mode 2.7 to 3.6 2.7 to 3.6 2.7 to 3.6 v f xx = 2.5 to 5 mhz (main clock) regc = 4.7 f, a/d converter stopped, d/a converter stopped clock-through mode 2.2 to 3.6 2.2 to 3.6 2.2 to 3.6 v f xt = 32.768 khz (subclock) regc = 4.7 f, a/d converter stopped, d/a converter stopped 2.2 to 3.6 2.2 to 3.6 2.2 to 3.6 v
v850es/jg3-l chapter 32 el ectrical specif ications ( pd70f3737, 70f3738) r01uh0165ej0700 rev.7.00 page 955 of 1113 sep 22, 2011 32.4 oscillator characteristics 32.4.1 main clock osc illator characteristics (1) main clock oscilla tor characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v) resonator circuit example paramete r conditions min. typ. max. unit v dd = 2.2 to 3.6 v 2.5 5 mhz clock through mode v dd = 2.7 to 3.6 v 2.5 10 mhz oscillation frequency (f x ) note 1 v dd = 2.7 to 3.6 v in pll mode 2.5 5 mhz v dd = 2.2 to 3.6 v immediately after reset ends note 3 note 4 s v dd = 2.2 to 3.6 v in clock through mode 400 note 5 note 6 s after stop mode is released v dd = 2.7 to 3.6 v in pll mode 400 note 7 note 6 s v dd = 2.2 to 3.6 v in clock through mode 200 note 5 note 6 s ceramic resonator/ crystal resonator x2 x1 oscillation stabilization time note 2 after idle2 mode is released v dd = 2.7 to 3.6 v in pll mode 400 note 7 note 6 s notes 1. the oscillation frequency shown above indicates only os cillator characteristics. use the v850es/jg3-l so that the internal operating condit ions do not exceed the ratings shown in ac characteristics , dc characteristics , and operating conditions . 2. the wait time required from when the resonator starts oscillating until oscillation stabilizes. 3. the oscillation stabilization time after reset release is restricted in accordance with the set value of the option byte. for details, see chapter 29 option byte . 4. the oscillation stabilization time differs depending on the set value of the option byte. for details, see chapter 29 option byte . 5. time required to set up the regulator and flash memory . secure the setup time using the osts register. 6. the value varies depending on the setting of the osts register. 7. time required to set up the regulator, flash memory, and pll. secure the setup time using the osts register. caution 1. when using the main clock oscillator, wire as follows in the ar ea enclosed by th e broken lines in the above figure to avo id an adverse effect from wiring capacitance. ? keep the wiring lengt h as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line th rough which a high fluctuating current flows. ? always make the ground point of the o scillator capacitor the same potential as v ss . ? do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. caution 2. when the main clock is stopped and th e device is operating on the subclock, wait until the oscillation stabilization time has been secured by the program before switching back to the main clock.
v850es/jg3-l chapter 32 el ectrical specif ications ( pd70f3737, 70f3738) r01uh0165ej0700 rev.7.00 page 956 of 1113 sep 22, 2011 (a) kyocera kinseki corporation: crystal resonator (t a = ? 10 to +70 c) recommended circuit constant oscillation voltage range oscillation stabilization time type circuit example part number oscillation frequency f x (mhz) c1 (pf) c2 (pf) rd ( ) min. (v) max. (v) max. (ms) cx49gfwb04000h0peszz 4.000 10 10 1000 2.2 3.6 10.45 cx49gfwb05000h0peszz 5.000 10 10 1000 2.2 3.6 10.08 cx49gfwb06000h0peszz 6.000 10 10 1000 2.2 3.6 9.26 cx49gfwb08000h0peszz 8.000 10 10 0 2.2 3.6 8.98 surface mounting x2 x1 c1 c2 rd cx49gfwb10000h0peszz 10.000 10 10 0 2.2 3.6 8.59 caution this oscillator constant is a reference value based on evalua tion under a specific environment by the resonator manufacturer. if optimization of oscillator characteristics is necessary in the actual application, apply to the resonator manufacturer for evaluation on the implementation circuit. the oscillation voltage and osc illation frequency indicate only osc illator characteris tics. use the v850es/jg3-l so that the internal operating condit ions are within the specifications of the ac characteristics, dc characterist ics, and operating conditions. (b) murata mfg. co. lt d.: ceramic resonator (t a = ? 20 to +80 c) recommended circuit constant oscillation voltage range oscillation stabilization time type circuit example part number oscillation frequency f x (mhz) c1 (pf) c2 (pf) rd ( ) min. (v) max. (v) max. (ms) cstcc2m50g56-r0 2.500 (47) (47) 2200 2.2 3.6 0.09 cstcr4m00g55-r0 4.000 (39) (39) 680 2.2 3.6 0.09 cstcr5m00g55-r0 5.000 (39) (39) 680 2.2 3.6 0.11 cstcr6m00g55-r0 6.000 (39) (39) 470 2.2 3.6 0.11 cstce8m00g55-r0 8.000 (33) (33) 0 2.2 3.6 0.10 surface mounting cstce10m0g55-r0 10.000 (33) (33) 0 2.2 3.6 0.10 cstls4m00g56-b0 4.000 (47) (47) 680 2.2 3.6 0.11 cstls5m00g56-b0 5.000 (47) (47) 680 2.2 3.6 0.13 cstls6m00g56-b0 6.000 (47) (47) 470 2.2 3.6 0.11 cstls8m00g56-b0 8.000 (47) (47) 100 2.2 3.6 0.10 lead x2 x1 c1 c2 rd cstls10m0g56-b0 10.000 (47) (47) 100 2.2 3.6 0.10 caution this oscillator constant is a reference value based on evalua tion under a specific environment by the resonator manufacturer. if optimization of oscillator characteristics is necessary in the actual application, apply to the resonator manufacturer for evaluation on the implementation circuit. the oscillation voltage and osc illation frequency indicate only osc illator characteris tics. use the v850es/jg3-l so that the internal operating condit ions are within the specifications of the ac characteristics, dc characterist ics, and operating conditions. remark figures in parentheses in columns c1 and c2 indi cate the capacitance incorporated in the resonator.
v850es/jg3-l chapter 32 el ectrical specif ications ( pd70f3737, 70f3738) r01uh0165ej0700 rev.7.00 page 957 of 1113 sep 22, 2011 (c) kyocera corporation: ceramic resonator (t a = ? 40 to +85 c) recommended circuit constant oscillation voltage range oscillation stabilization time type circuit example part number oscillation frequency f x (mhz) c1 (pf) c2 (pf) rd ( ) min. (v) max. (v) max. (ms) pbrc2.50hr50x000 2.50 (30) (30) 0 2.2 3.6 0.10 pbrc4.00mr50x000 4.00 (15) (15) 0 2.2 3.6 0.06 pbrc5.00mr50x000 5.00 (15) (15) 0 2.2 3.6 0.06 pbrc6.00mr50x000 6.00 (15) (15) 0 2.2 3.6 0.06 pbrc8.00mr50x000 8.00 (15) (15) 0 2.2 3.6 0.06 surface mounting x2 x1 c1 c2 rd pbrc10.00mr50x000 10.00 (10) (10) 0 2.2 3.6 0.10 caution this oscillator constant is a reference value based on evalua tion under a specific environment by the resonator manufacturer. if optimization of oscillator characteristics is necessary in the actual application, apply to the resonator manufacturer for evaluation on the implementation circuit. the oscillation voltage and osc illation frequency indicate only osc illator characteris tics. use the v850es/jg3-l so that the internal operating condit ions are within the specifications of the ac characteristics, dc characterist ics, and operating conditions.
v850es/jg3-l chapter 32 el ectrical specif ications ( pd70f3737, 70f3738) r01uh0165ej0700 rev.7.00 page 958 of 1113 sep 22, 2011 (2) external clock (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.7 to 3.6 v, v ss = ev ss = av ss = 0 v) resonator circuit example paramete r conditions min. typ. max. unit clock through mode 2.5 5 mhz input frequency (f x ) note pll mode 2.5 5 mhz v ih x1 2.3 v dd v external clock open external clock cmos inverter x2 x1 v il x1 v ss 0.4 v note keep the duty factor of the input waveform to within 45% to 55%. cautions 1. be sure to disconnect the internal feedback resistor after reset (set pcc.mfrc = 1). 2. leave the x2 pin open. 3. make sure that the cmos inverter is as close to the x1 pin as possible.
v850es/jg3-l chapter 32 el ectrical specif ications ( pd70f3737, 70f3738) r01uh0165ej0700 rev.7.00 page 959 of 1113 sep 22, 2011 32.4.2 subclock oscilla tor characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.2 to 3.6 v, v ss = ev ss = av ss = 0 v) resonator circuit example parameter conditions min. typ. max. unit oscillation frequency (f xt ) note 1 32 32.768 35 khz crystal resonator xt2 xt1 oscillation stabilization time note 2 10 s notes 1. the oscillation frequency shown above indicates only os cillator characteristics. use the v850es/jg3-l so that the internal operation condit ions do not exceed the ratings shown in ac characteristics , dc characteristics , and operating conditions. 2. time required from when v dd reaches the oscillation voltage range (2.2 v (min.)) to when the crystal resonator stabilizes. cautions 1. when using the subclo ck oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. ? keep the wiring le ngth as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the oscillator capacitor the same potential as v ss . ? do not ground the capacitor to a groun d pattern through which a high current flows. ? do not fetch signals from the oscillator. 2. the subclock oscillator is designed as a low-amplitude circuit for reducing power consumption, and is mo re prone to malfunction due to noi se than the main clock oscillator. particular care is theref ore required with the wiring met hod when the subclock is used. 3. for the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
v850es/jg3-l chapter 32 el ectrical specif ications ( pd70f3737, 70f3738) r01uh0165ej0700 rev.7.00 page 960 of 1113 sep 22, 2011 (a) seiko instruments inc.: crystal resonator (t a = ? 40 to +85 c) oscillation frequency: f xt = 32.768 khz recommended circuit constant oscillation voltage range type circuit example part number load capacitance of crystal resonator (pf) c1 (pf) c2 (pf) rd ( ) min. (v) max. (v) 6 5 5 0 2.2 3.6 sp-t2a 12.5 18 18 0 2.2 3.6 surface mounting ssp-t7 7 8 8 0 2.2 3.6 6 6 6 0 2.2 3.6 lead xt2 xt1 c1 c2 rd vt-200 12.5 18 18 0 2.2 3.6 caution this oscillator constant is a reference value based on evalua tion under a specific environment by the resonator manufacturer. if optimization of oscillator characteristics is necessary in the actual application, apply to the resonator manufacturer for evaluation on the implementation circuit. the oscillation voltage and osc illation frequency indicate only osc illator characteris tics. use the v850es/jg3-l so that the internal operating condit ions are within the specifications of the ac characteristics, dc characterist ics, and operating conditions. (b) citizen miyota co., ltd.: crystal resonator (t a = ? 40 to +85 c) oscillation frequency: f xt = 32.768 khz recommended circuit constant oscillation voltage range type circuit example part number load capacitance of crystal resonator (pf) c1 (pf) c2 (pf) rd ( ) min. (v) max. (v) cm200s 9 12 12 100 2.2 3.6 cmr200t 9 12 12 100 2.2 3.6 surface mounting cm519 9 12 12 100 2.2 3.6 cm315 9 12 12 100 2.2 3.6 lead xt2 xt1 c1 c2 rd cfs-206 9 12 12 100 2.2 3.6 caution this oscillator constant is a reference value based on evalua tion under a specific environment by the resonator manufacturer. if optimization of oscillator characteristics is necessary in the actual application, apply to the resonator manufacturer for evaluation on the implementation circuit. the oscillation voltage and osc illation frequency indicate only osc illator characteris tics. use the v850es/jg3-l so that the internal operating condit ions are within the specifications of the ac characteristics, dc characterist ics, and operating conditions.
v850es/jg3-l chapter 32 el ectrical specif ications ( pd70f3737, 70f3738) r01uh0165ej0700 rev.7.00 page 961 of 1113 sep 22, 2011 32.4.3 pll characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit input frequency f x 2.5 5 mhz output frequency f xx 10 20 mhz lock time t pll after v dd reaches 2.7 v (min.) 400 s 32.4.4 internal oscillat or characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit output frequency f r 100 220 400 khz 32.5 regulator characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit f xx = 20 mhz (max.) 2.7 3.6 v f xx = 5 mhz (max.) 2.2 3.6 v input voltage v dd data retained (stop mode) 1.9 3.6 v output voltage v ro v dd = 2.7 to 3.6 v 2.5 v after v dd reaches 2.7 v (min.), stabilization capacitance c = 4.7 f (recommended value) connected to regc pin 1 ms regulator output stabilization time t reg after v dd reaches 2.2 v (min.), stabilization capacitance c = 4.7 f (recommended value) connected to regc pin 3.5 ms external capacitance regc permissible error of external capacitance to be connected to regc pin 3.76 4.70 5.64 f v dd v ro t reg reset
v850es/jg3-l chapter 32 el ectrical specif ications ( pd70f3737, 70f3738) r01uh0165ej0700 rev.7.00 page 962 of 1113 sep 22, 2011 32.6 dc characteristics 32.6.1 pin characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.2 to 3.6 v, v ss = ev ss = av ss = 0 v) (1/2) parameter symbol conditions min. typ. max. unit v ih1 reset, flmd0, p97 to p915 0.8ev dd ev dd v v ih2 p02 to p06, p30 to p37, p42, p50 to p55, p92 to p96 0.8ev dd 5.5 v v ih3 p38, p39, p40, p41, p90, p91 0.7ev dd 5.5 v v ih4 pcm0 to pcm3, pct0, pct1, pct4, pct6, pdh0 to pdh5, pdl0 to pdl15 0.7ev dd ev dd v v ih5 p70 to p711 0.7av ref0 av ref0 v input voltage, high v ih6 p10, p11 0.7av ref1 av ref1 v v il1 reset, flmd0, p97 to p915 ev ss 0.2ev dd v v il2 p02 to p06, p30 to p37, p42, p50 to p55, p92 to p96 ev ss 0.2ev dd v v il3 p38, p39, p40, p41, p90, p91 ev ss 0.3ev dd v v il4 pcm0 to pcm3, pct0, pct1, pct4, pct6, pdh0 to pdh5, pdl0 to pdl15 ev ss 0.3ev dd v v il5 p70 to p711 av ss 0.3av ref0 v input voltage, low v il6 p10, p11 av ss 0.3av ref1 v input leakage current, high i lih v i = v dd = ev dd = av ref0 = av ref1 5 a input leakage current, low i lil v i = 0 v ? 5 a output leakage current, high i loh v o = v dd = ev dd = av ref0 = av ref1 5 a output leakage current, low i lol v o = 0 v ? 5 a remark unless specified otherwise, the characteristics of alte rnate-function pins are t he same as those of port pins.
v850es/jg3-l chapter 32 el ectrical specif ications ( pd70f3737, 70f3738) r01uh0165ej0700 rev.7.00 page 963 of 1113 sep 22, 2011 (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.2 to 3.6 v, v ss = ev ss = av ss = 0 v) (2/2) parameter symbol conditions min. typ. max. unit per pin i oh = ? 1.0 ma total of all pins ? 20 ma ev dd ? 1.0 ev dd v v oh1 p02 to p06, p30 to p39, p40 to p42, p50 to p55, p90 to p915, pdh4, pdh5 per pin i oh = ? 100 a total of all pins ? 4.2 ma ev dd ? 0.5 ev dd v per pin i oh = ? 1.0 ma total of all pins ? 20 ma ev dd ? 1.0 ev dd v v oh2 pcm0 to pcm3, pct0, pct1, pct4, pct6, pdh0 to pdh3, pdl0 to pdl15 per pin i oh = ? 100 a total of all pins ? 2.8 ma ev dd ? 0.5 ev dd v per pin i oh = ? 0.4 ma total of all pins ? 4.8 ma av ref0 ? 1.0 av ref0 v v oh3 p70 to p711 per pin i oh = ? 100 a total of all pins ? 1.2 ma av ref0 ? 0.5 av ref0 v per pin i oh = ? 0.4 ma total of all pins ? 0.8 ma av ref1 ? 1.0 av ref1 v output voltage, high v oh4 p10, p11 per pin i oh = ? 100 a total of all pins ? 0.2 ma av ref1 ? 0.5 av ref1 v v ol1 p02 to p06, p30 to p37, p42, p50 to p55, p92 to p915, pdh4, pdh5 per pin i ol = 1.0 ma 0 0.4 v v ol2 p38, p39, p40, p41, p90, p91 per pin i ol = 3.0 ma total of all pins 20 ma 0 0.4 v v ol3 pcm0 to pcm3, pct0, pct1, pct4, pct6, pdh0 to pdh3, pdl0 to pdl15 per pin i ol = 1.0 ma total of all pins 20 ma 0 0.4 v output voltage, low v ol4 p10, p11, p70 to p711 per pin i ol = 0.4 ma total of all pins 5.6 ma 0 0.4 v software pull-down resistor note r 1 p05 v i = v dd 10 20 100 k note drst pin only (controlled by ocdm register) remarks 1. unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins. 2. when the i oh and i ol conditions are not satisfied for a pin but the to tal value of all pins is satisfied, only that pin does not satisfy the dc characteristics.
v850es/jg3-l chapter 32 el ectrical specif ications ( pd70f3737, 70f3738) r01uh0165ej0700 rev.7.00 page 964 of 1113 sep 22, 2011 32.6.2 supply current characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. note 1 max. note 2 unit f xx = 20 mhz (f x = 5 mhz) note 4 12 note 5 20 ma i dd1 normal operation f xx = 10 mhz (f x = 10 mhz), pll off note 4 6 note 5 10 ma i dd2 halt mode f xx = 20 mhz (f x = 5 mhz) note 4 7.5 14 ma i dd3 idle1 mode f xx = 5 mhz (f x = 5 mhz), pll off note 4 0.6 1 ma i dd4 idle2 mode f xx = 5 mhz (f x = 5 mhz), pll off note 4 0.28 0.5 ma i dd5 subclock operation mode f xt = 32.768 khz, main clock stopped, internal oscillator stopped, pll off regovl0 = 02h (low-voltage subclock operation mode) 18 a i dd6 sub-idle mode f xt = 32.768 khz, main clock stopped, internal oscillator stopped, pll off regovl0 = 02h (low-voltage sub-idle mode) 2.5 30 a subclock stopped, internal oscillator stopped regovl0 = 01h (low-voltage stop mode) t a = 25 c 1.5 3.0 a subclock stopped, internal oscillator stopped regovl0 = 01h (low-voltage stop mode) t a = 85 c 25 a i dd7 stop mode subclock operating, internal oscillator stopped regovl0 = 01h (low-voltage stop mode) 2.5 30 a supply current note 3 i dd8 self programming mode f xx = 20 mhz (f x = 5 mhz) 14 24 ma lvi current i lvi 1.2 3 a wdt, internal oscillation current i wdt 5 a notes 1. typ. current is a value at v dd = ev dd = 3.3 v, t a = 25 c. the typ. value is not a value guaranteed for each device. 2. max. current is a value at which the characterist ic in question is at the worst-case value at v dd = ev dd = 3.6 v, t a = ? 40 to +85 c. 3. total of v dd and ev dd currents. currents i lvi and i wdt flowing through the output buffers, a/d converter, d/a converter, and on-chip pull-do wn resistor are not included. 4. typ. value indicates the current value when watch timer + tmm (count by watch timer interrupt) operate as peripheral functions. max. value indicates the current value when all the f unctions operable in a range in which the pin status is not changed operate as peripheral functions. however, i lvi and i wdt are excluded. 5. typ. value of i dd1 is a value when all instructions are executed + ram access 15%. remark for details about the operating voltage, see 32.3 operating conditions .
v850es/jg3-l chapter 32 el ectrical specif ications ( pd70f3737, 70f3738) r01uh0165ej0700 rev.7.00 page 965 of 1113 sep 22, 2011 32.6.3 data retention charact eristics (in stop mode) (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit data retention voltage v dddr stop mode (all functions stopped) 1.9 3.6 v data retention current i dddr subclock stopped, internal oscillator stopped t a = 85 c 45 a supply voltage rise time t rvd 200 s supply voltage fall time t fvd 200 s supply voltage retention time t hvd after stop mode setting 0 ms stop release signal input time t drel after v dd reaches the operating voltage min. (see 32.3 operating conditions ) 0 ms data retention input voltage, high v ihdr v dd = ev dd = v dddr 0.9v dddr v dddr v data retention input voltage, low v ildr v dd = ev dd = v dddr 0 0.1v dddr v caution shifting to stop mode and restoring from stop mode must be performed within the rated operating range. t drel t hvd t fvd t rvd stop release signal input stop mode setting v dddr v ihdr v ihdr v ildr v dd /ev dd reset (input) stop mode release interrupt (nmi, etc.) (released by falling edge) stop mode release interrupt (nmi, etc.) (released by rising edge) operating voltage lower limit
v850es/jg3-l chapter 32 el ectrical specif ications ( pd70f3737, 70f3738) r01uh0165ej0700 rev.7.00 page 966 of 1113 sep 22, 2011 32.7 ac characteristics 32.7.1 measurement conditions (1) ac test input measurement points v dd v ss v ih v il v ih v il measurement points (2) ac test output measurement points v oh v ol v oh v ol measurement points (3) load conditions dut (device under measurement) c l = 50 pf caution if the load capacitance exceeds 50 pf due to the circuit configuration, bring the load capacitance of the device to 50 pf or less by inserting a buffer or by some other means.
v850es/jg3-l chapter 32 el ectrical specif ications ( pd70f3737, 70f3738) r01uh0165ej0700 rev.7.00 page 967 of 1113 sep 22, 2011 32.7.2 clkout output timing (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.7 to 3.6 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit output cycle t cyk <1> 50 ns 31.25 s high-level width t wkh <2> t cyk /2 ? 10 ns low-level width t wkl <3> t cyk /2 ? 10 ns rise time t kr <4> 10 ns fall time t kf <5> 10 ns clkout (output) <1> <2> <3> <4> <5>
v850es/jg3-l chapter 32 el ectrical specif ications ( pd70f3737, 70f3738) r01uh0165ej0700 rev.7.00 page 968 of 1113 sep 22, 2011 32.7.3 bus timing the values for just the access method to be used (syn chronous with or asynchronous to clkout) must be satisfied. it is not necessary to satisfy the values for both methods. (1) in multiplexed bus mode (a) read/write cycle (a synchronous to clkout) (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.7 to 3.6 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit address setup time (to astb ) t sast <6> (0.5 + t asw )t ? 20 ns address hold time (from astb ) t hsta <7> (0.5 + t ahw )t ? 15 ns delay time from rd to address float t frda <8> 16 ns data input setup time from address t said <9> (2 + n + t asw + t ahw )t ? 35 ns data input setup time from rd t srid <10> (1 + n)t ? 25 ns delay time from astb to rd, wrm t dstrdwr <11> (0.5 + t ahw )t ? 15 ns data input hold time (from rd ) t hrdid <12> 0 ns address output time from rd t drda <13> (1 + i)t ? 15 ns delay time from rd, wrm to astb t drdwrst <14> 0.5t ? 15 ns delay time from rd to astb t drdst <15> (1.5 + i + t asw )t ? 15 ns rd, wrm low-level width t wrdwrl <16> (1 + n)t ? 15 ns astb high-level width t wsth <17> (1 + i + t asw )t ? 15 ns data output time from wrm t dwrod <18> 15 ns data output setup time (to wrm ) t sodwr <19> (1 + n)t ? 20 ns data output hold time (from wrm ) t hwrod <20> t ? 15 ns t sawt1 <21> n 1 (1.5 + t asw + t ahw )t ? 35 ns wait setup time (to address) t sawt2 <22> (1.5 + n + t asw + t ahw )t ? 35 ns t hawt1 <23> n 1 (0.5 + n + t asw + t ahw )t ns wait hold time (from address) t hawt2 <24> (1.5 + n + t asw + t ahw )t ns t sstwt1 <25> n 1 (1 + t ahw )t ? 25 ns wait setup time (to astb ) t sstwt2 <26> (1 + n + t ahw )t ? 25 ns t hstwt1 <27> n 1 (n + t ahw )t ns wait hold time (from astb ) t hstwt2 <28> (1 + n + t ahw )t ns address hold time from rd t hrda2 <29> (1 + i)t ? 15 ns address hold time from wrm t hwra2 <30> t ? 15 ns remarks 1. t asw : number of address setup wait clocks (0 or 1) t ahw : number of address hold wait clocks (0 or 1) 2. t = 1/f cpu (f cpu : cpu operating clock frequency) 3. n: number of wait clocks inserted in the bus cycle the sampling timing changes when a programmable wait is inserted. 4. m = 0, 1 5. i: number of idle states inserted after a read cycle (0 or 1) 6. the values in the above specifications are values for when clo cks with a 1:1 duty ratio are input from x1.
v850es/jg3-l chapter 32 el ectrical specif ications ( pd70f3737, 70f3738) r01uh0165ej0700 rev.7.00 page 969 of 1113 sep 22, 2011 read cycle (asynchronous to clkout): in mu ltiplexed bus mode clkout (output) a16 to a21 (output) ad0 to ad15 (i/o) astb (output) rd (output) wait (input) t1 t2 tw t3 data address hi-z <6> <7> <17> <9> <12> <14> <10> <11> <25> <27> <26> <28> <21> <23> <22> <24> <16> <8> <13> <29> <15> remark wr0 and wr1 are high level.
v850es/jg3-l chapter 32 el ectrical specif ications ( pd70f3737, 70f3738) r01uh0165ej0700 rev.7.00 page 970 of 1113 sep 22, 2011 write cycle (asynchronous to clko ut): in multiplexed bus mode clkout (output) ad0 to ad15 (i/o) astb (output) wr0, wr1 (output) wait (input) t1 t2 tw t3 data address <25> <27> <26> <28> <21> <23> <22> <24> <6> <17> <7> <14> <20> <30> <19> <16> <11> <18> a16 to a21 (output) remark rd is high level.
v850es/jg3-l chapter 32 el ectrical specif ications ( pd70f3737, 70f3738) r01uh0165ej0700 rev.7.00 page 971 of 1113 sep 22, 2011 (b) read/write cycle (synchronous with clkout): in multiplexed bus mode (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.7 to 3.6 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit delay time from clkout to address t dka <31> 0 25 ns delay time from clkout to address float t fka <32> 0 19 ns delay time from clkout to astb t dkst <33> ? 12 7 ns delay time from clkout to rd, wrm t dkrdwr <34> ? 5 14 ns data input setup time (to clkout ) t sidk <35> 15 ns data input hold time (from clkout ) t hkid <36> 5 ns data output delay time from clkout t dkod <37> 19 ns wait setup time (to clkout ) t swtk <38> 20 ns wait hold time (from clkout ) t hkwt <39> 5 ns address hold time from clkout t hka2 <40> 0 25 ns data output hold time from clkout t hkdw <41> 0 ns address hold time from clkout t hkaw <42> 0 ns remarks 1. m = 0, 1 2. the values in the above specifications are values for when cl ocks with a 1:1 duty ratio are input from x1. 3. for details about the clkout output timing, see 32.7.2 clkout output timing . read cycle (synchronous with clkout): in multiplexed bus mode clkout (output) a16 to a21 (output) ad0 to ad15 (i/o) astb (output) rd (output) wait (input) t1 t2 tw t3 ti t1 data address hi-z <31> <33> <34> <32> <31> <33> <40> <34> <38> <38> <39> <39> <35> <36> remark wr0 and wr1 are high level.
v850es/jg3-l chapter 32 el ectrical specif ications ( pd70f3737, 70f3738) r01uh0165ej0700 rev.7.00 page 972 of 1113 sep 22, 2011 write cycle (synchronous with clko ut): in multiplexed bus mode clkout (output) ad0 to ad15 (i/o) astb (output) wr0, wr1 (output) wait (input) t1 t2 tw t3 data address <31> <33> <34> <34> <39> <39> <38> <38> <33> <41> <42> <37> a16 to a21 (output) remark rd is high level.
v850es/jg3-l chapter 32 el ectrical specif ications ( pd70f3737, 70f3738) r01uh0165ej0700 rev.7.00 page 973 of 1113 sep 22, 2011 (2) in separate bus mode (a) read cycle (asynchronous to clkout): in separate bus mode (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.7 to 3.6 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit address setup time (to rd ) t sard <43> (0.5 + t asw )t ? 27 ns address hold time (from rd ) t hard <44> it ? 2 note ns rd low-level width t wrdl <45> (1.5 + n + t ahw )t ? 10 ns data setup time (to rd ) t sisd <46> 23 ns data hold time (from rd ) t hisd <47> ? 2 ns data setup time (to address) t said <48> (2 + n + t asw + t ahw )t ? 40 ns t srdwt1 <49> (0.5 + t ahw )t ? 25 ns wait setup time (to rd ) t srdwt2 <50> (0.5 + n + t ahw )t ? 25 ns t hrdwt1 <51> (n ? 0.5 + t ahw )t ns wait hold time (from rd ) t hrdwt2 <52> (n + 0.5 + t ahw )t ns t sawt1 <53> (1 + t asw + t ahw )t ? 45 ns wait setup time (to address) t sawt2 <54> (1 + n + t asw + t ahw )t ? 45 ns t hawt1 <55> (n + t asw + t ahw )t ns wait hold time (from address) t hawt2 <56> (1 + n + t asw + t ahw )t ns data output delay time from rd t drdod1 <57> (1 + i + t asw )t ? 15 ns note the address may be changed during the low-level period of the rd pin. to avoid the address change, insert an idle state. remarks 1. t asw : number of address setup wait clocks t ahw : number of address hold wait clocks 2. t = 1/f cpu (f cpu : cpu operating clock frequency) 3. n: number of wait clocks inserted in the bus cycle the sampling timing changes when a programmable wait is inserted. 4. i: number of idle states inserted after a read cycle (0 or 1) 5. the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1.
v850es/jg3-l chapter 32 el ectrical specif ications ( pd70f3737, 70f3738) r01uh0165ej0700 rev.7.00 page 974 of 1113 sep 22, 2011 read cycle (asynchronous to cl kout): in separate bus mode clkout (output) t1 <48> hi-z hi-z <43> <45> <52> <50> <51> <49> <53> <55> <54> <56> <47> <46> <57> <44> tw t2 rd (output) wr0, wr1 (output) a0 to a21 (output) ad0 to ad15 (i/o) wait (input) remark wr0 and wr1 are high level.
v850es/jg3-l chapter 32 el ectrical specif ications ( pd70f3737, 70f3738) r01uh0165ej0700 rev.7.00 page 975 of 1113 sep 22, 2011 (b) write cycle (asynchronous to clkout): in separate bus mode (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.7 to 3.6 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit address setup time (to wrm ) t sawr <58> (1 + t asw + t ahw )t ? 27 ns address hold time (from wrm ) t hawr <59> 0.5t ? 6 ns wrm low-level width t wwrl <60> (0.5 + n)t ? 10 ns data output time from wrm t dosdw <61> ? 5 ns data setup time (to wrm ) t sosdw <62> (0.5 + n)t ? 20 ns data hold time (from wrm ) t hosdw <63> 0.5t ? 7 ns data setup time (to address) t saod <64> (1 + t asw + t ahw )t ? 25 ns t swrwt1 <65> 22 ns wait setup time (to wrm ) t swrwt2 <66> nt ? 22 ns t hwrwt1 <67> 0 ns wait hold time (from wrm ) t hwrwt2 <68> nt ns t sawt1 <69> (1 + t asw + t ahw )t ? 45 ns wait setup time (to address) t sawt2 <70> (1 + n + t asw + t ahw )t ? 45 ns t hawt1 <71> (n + t asw + t ahw )t ns wait hold time (from address) t hawt2 <72> (1 + n + t asw + t ahw )t ns remarks 1. m = 0, 1 2. t asw : number of address setup wait clocks t ahw : number of address hold wait clocks 3. t = 1/f cpu (f cpu : cpu operating clock frequency) 4. n: number of wait clocks inserted in the bus cycle the sampling timing changes when a programmable wait is inserted. 5. the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1.
v850es/jg3-l chapter 32 el ectrical specif ications ( pd70f3737, 70f3738) r01uh0165ej0700 rev.7.00 page 976 of 1113 sep 22, 2011 write cycle (asynchronous to cl kout): in separate bus mode clkout (output) t1 <64> <58> <61> <60> <68> <66> <67> <65> <69> <71> <70> <72> <63> <62> <59> tw t2 wr0, wr1 (output) a0 to a21 (output) ad0 to ad15 (i/o) wait (input) hi-z hi-z remark rd is high level.
v850es/jg3-l chapter 32 el ectrical specif ications ( pd70f3737, 70f3738) r01uh0165ej0700 rev.7.00 page 977 of 1113 sep 22, 2011 (c) read cycle (synchronous with clkout): in separate bus mode (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.7 to 3.6 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit delay time from clkout to address t dksa <73> 0 27 ns data input setup time (to clkout ) t sisdk <74> 20 ns data input hold time (from clkout ) t hkisd <75> 0 ns delay time from clkout to rd t dksr <76> ? 2 12 ns wait setup time (to clkout ) t swtk <77> 20 ns wait hold time (from clkout ) t hkwt <78> 0 ns remarks 1. the values in the above specif ications are values for when clo cks with a 1:1 duty ratio are input from x1. 2. for details about the clkout output timing, see 32.7.2 clkout output timing . read cycle (synchronous with clkout , 1 wait): in separate bus mode clkout (output) t1 <76> <77> <78> <77> <78> <73> <76> <74> <75> hi-z hi-z tw t2 rd (output) a0 to a21 (output) ad0 to ad15 (i/o) wait (input) <73> remark wr0 and wr1 are high level.
v850es/jg3-l chapter 32 el ectrical specif ications ( pd70f3737, 70f3738) r01uh0165ej0700 rev.7.00 page 978 of 1113 sep 22, 2011 (d) write cycle (synchronous with clkout): in separate bus mode (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.7 to 3.6 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit delay time from clkout to address t dksa <79> 0 27 ns delay time from clkout to data output t dksd <80> 0 18 ns delay time from clkout to wrm t dksw <81> ? 2 12 ns wait setup time (to clkout ) t swtk <82> 20 ns wait hold time (from clkout ) t hkwt <83> 0 ns remarks 1. m = 0, 1 2. the values in the above specifications are values for when cl ocks with a 1:1 duty ratio are input from x1. 3. for details about the clkout output timing, see 32.7.2 clkout output timing . write cycle (synchronous with cl kout): in separate bus mode clkout (output) t1 <80> <81> <83> <82> <81> tw t2 wr0, wr1 (output) a0 to a21 (output) ad0 to ad15 (i/o) wait (input) <79> <79> <83> <82> <80> hi-z hi-z remark rd is high level.
v850es/jg3-l chapter 32 el ectrical specif ications ( pd70f3737, 70f3738) r01uh0165ej0700 rev.7.00 page 979 of 1113 sep 22, 2011 (3) bus hold (a) asynchronous to clkout (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.7 to 3.6 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit hldrq high-level width t whqh <84> t + 10 ns hldak low-level width t whal <85> t ? 15 ns delay time from hldak to bus output t dhac <86> ? 3 ns delay time from hldrq to hldak t dhqha1 <87> (2n + 7.5)t + 26 ns delay time from hldrq to hldak t dhqha2 <88> 0.5t 1.5t + 26 ns remarks 1. t = 1/f cpu (f cpu : cpu operating clock frequency) 2. n: number of wait clocks inserted in the bus cycle the sampling timing changes when a programmable wait is inserted. 3. the values in the above specifications are values for when cl ocks with a 1:1 duty ratio are input from x1. bus hold (asynchronous to clkout) clkout (output) hldrq (input) hldak (output) address bus (output) data bus (i/o) th th th ti ti hi-z astb (output) rd (output), wr0, wr1 (output) hi-z hi-z <84> <88> <85> <86> <87>
v850es/jg3-l chapter 32 el ectrical specif ications ( pd70f3737, 70f3738) r01uh0165ej0700 rev.7.00 page 980 of 1113 sep 22, 2011 (b) synchronous with clkout (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.7 to 3.6 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit hldrq setup time (to clkout ) t shqk <89> 20 ns hldrq hold time (from clkout ) t hkhq <90> 5 ns delay time from clkout to bus float t dkf <91> 19 ns delay time from clkout to hldak t dkha <92> 19 ns remarks 1. the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1. 2. for details about the clkout output timing, see 32.7.2 clkout output timing . bus hold (synchronous with clkout) clkout (output) hldrq (input) hldak (output) address bus (output) data bus (i/o) th th th t2 t3 ti ti hi-z astb (output) rd (output), wr0, wr1 (output) hi-z hi-z <89> <89> <92> <92> <90> <91>
v850es/jg3-l chapter 32 el ectrical specif ications ( pd70f3737, 70f3738) r01uh0165ej0700 rev.7.00 page 981 of 1113 sep 22, 2011 32.7.4 power on/power off/reset timing (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.2 to 3.6 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit ev dd v dd t rel <93> 0 ns ev dd av ref0 , av ref1 t rea <94> 0 t rel ns v dd reset t rer <95> 500 + t reg note ns reset low-level width t wrsl <96> 500 ns reset v dd t fre <97> 500 ns v dd ev dd t fel <98> 0 ns av ref0 ev dd t fea <99> 0 t fel ns note see 32.5 regulator characteristics . remark the reset pin has an analog noise elimination function. v dd ev dd v i v i v i v i av ref0 reset (input) <93> <95> <97> <96> <94> <98> <99>
v850es/jg3-l chapter 32 el ectrical specif ications ( pd70f3737, 70f3738) r01uh0165ej0700 rev.7.00 page 982 of 1113 sep 22, 2011 32.8 peripheral function characteristics 32.8.1 interrupt timing (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.2 to 3.6 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit nmi high-level width t wnih 500 ns nmi low-level width t wnil 500 ns n = 0 to 7 (analog noise elimination) 500 ns intpn note high-level width t with n = 3 (digital noise elimination) 3t smp + 20 ns n = 0 to 7 (analog noise elimination) 500 ns intpn note low-level width t witl n = 3 (digital noise elimination) 3t smp + 20 ns note the characteristics of intpn is the same as the drst pin (p05/intp2/drst). remarks 1. t smp : noise elimination sampling clock cycle 2. the nmi and intpn pins have the analog no ise elimination function (n = 0 to 7). 32.8.2 key return timing (t a = ? 40 to +85 c, v dd = ev dd = av ref 0 = av ref1 = 2.2 to 3.6 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit krn high-level width t wkrh 500 ns krn low-level width t wkrl 500 ns remarks 1. n = 0 to 7 2. the krn pin has an analog noise elimination function. 32.8.3 timer timing (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.2 to 3.6 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit ti high-level width t tih 2t + 20 ns ti low-level width t til tip00, tip01, tip10, tip11, tip20, tip21, tip30, tip31, tip40, tip41, tip50, tip51, tiq00 to tiq03 2t + 20 ns remark t = 1/f xx
v850es/jg3-l chapter 32 el ectrical specif ications ( pd70f3737, 70f3738) r01uh0165ej0700 rev.7.00 page 983 of 1113 sep 22, 2011 32.8.4 uart timing (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit transmit rate v dd = 2.2 to 3.6 v 625 kbps v dd = 2.2 to 3.6 v 5 mhz asck0 frequency v dd = 2.7 to 3.6 v 10 mhz 32.8.5 csib timing (1) master mode (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit 2.7 v v dd 3.6 v 125 ns sckbn cycle time t kcy1 <100> 2.2 v v dd < 2.7 v 800 ns 2.7 v v dd 3.6 v t kcy1 /2 ? 8 ns sckbn high-level width t kh1 <101> 2.2 v v dd < 2.7 v t kcy1 /2 ? 80 ns 2.7 v v dd 3.6 v t kcy1 /2 ? 8 ns sckbn low-level width t kl1 <102> 2.2 v v dd < 2.7 v t kcy1 /2 ? 80 ns 2.7 v v dd 3.6 v 27 ns sibn setup time (to sckbn ) t sik1 <103> 2.2 v v dd < 2.7 v 100 ns 2.7 v v dd 3.6 v 27 ns sibn hold time (from sckbn ) t ksi1 <104> 2.2 v v dd < 2.7 v 100 ns 2.7 v v dd 3.6 v 27 ns delay time from sckbn to sobn output t kso1 <105> 2.2 v v dd < 2.7 v 95 ns remark n = 0 to 4
v850es/jg3-l chapter 32 el ectrical specif ications ( pd70f3737, 70f3738) r01uh0165ej0700 rev.7.00 page 984 of 1113 sep 22, 2011 (2) slave mode (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit 2.7 v v dd 3.6 v 125 ns sckbn cycle time t kcy2 <100> 2.2 v v dd < 2.7 v 800 ns sckbn high-level width t kh2 <101> 2.2 v v dd 3.6 v 54.5 ns sckbn low-level width t kl2 <102> 2.2 v v dd 3.6 v 54.5 ns 2.7 v v dd 3.6 v 27 ns sibn setup time (to sckbn ) t sik2 <103> 2.2 v v dd < 2.7 v 100 ns 2.7 v v dd 3.6 v 27 ns sibn hold time (from sckbn ) t ksi2 <104> 2.2 v v dd < 2.7 v 100 ns 2.7 v v dd 3.6 v 27 ns delay time from sckbn to sobn output t kso2 <105> 2.2 v v dd < 2.7 v 95 ns remark n = 0 to 4 sobn (output) input data output data sibn (input) sckbn (i/o) <100> <101> <102> <103> <104> <105> remark n = 0 to 4
v850es/jg3-l chapter 32 el ectrical specif ications ( pd70f3737, 70f3738) r01uh0165ej0700 rev.7.00 page 985 of 1113 sep 22, 2011 32.8.6 i 2 c bus mode (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.2 to 3.6 v, v ss = ev ss = av ss = 0 v) normal mode high-speed mode parameter symbol min. max. min. max. unit scl0n clock frequency f clk 0 100 0 400 khz bus free time (between start and stop conditions) t buf <106> 4.7 ? 1.3 ? s hold time note 1 t hd:sta <107> 4.0 ? 0.6 ? s scl0n clock low-level width t low <108> 4.7 ? 1.3 ? s scl0n clock high-level width t high <109> 4.0 ? 0.6 ? s setup time for start/restart conditions t su:sta <110> 4.7 ? 0.6 ? s cbus compatible master 5.0 ? ? ? s data hold time i 2 c mode t hd:dat <111> 0 note 2 ? 0 note 2 0.9 note 3 s data setup time t su:dat <112> 250 ? 100 note 4 ? ns sda0n and scl0n signal rise time t r <113> ? 1000 20 + 0.1cb note 5 300 ns sda0n and scl0n signal fall time t f <114> ? 300 20 + 0.1cb note 5 300 ns stop condition setup time t su:sto <115> 4.0 ? 0.6 ? s pulse width of spike suppressed by input filter t sp <116> ? ? 0 50 ns capacitance load of each bus line cb ? 400 ? 400 pf notes 1. at the start condition, the first clock pulse is generated after the hold time. 2. the system requires a minimum of 300 ns hold time internally for the sda0n signal (at v ihmin. of scl0n signal) in order to occupy the undefined area at the falling edge of scl0n. 3. if the system does not extend the scl0n signal low hold time (t low ), only the maximum data hold time (t hd : dat ) needs to be satisfied. 4. the high-speed mode i 2 c bus can be used in the normal-mode i 2 c bus system. in this case, set the high-speed mode i 2 c bus so that it meets the following conditions. ? if the system does not extend the scl0n signal?s low state hold time: t su : dat 250 ns ? if the system extends the scl0n signal?s low state hold time: transmit the following data bit to the sda0n line prior to the scl0n line release (t rmax. + t su:dat = 1,000 + 250 = 1,250 ns: normal mode i 2 c bus specification). 5. cb: total capacitance of one bus line (unit: pf) remark n = 0 to 2
v850es/jg3-l chapter 32 el ectrical specif ications ( pd70f3737, 70f3738) r01uh0165ej0700 rev.7.00 page 986 of 1113 sep 22, 2011 i 2 c bus timing stop condition start condition restart condition stop condition scl0n (i/o) sda0n (i/o) <108> <114> <114> <113> <113> <111> <112> <110> <107> <106> <107> <116> <115> <109> remark n = 0 to 2 32.8.7 a/d converter (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , 2.7 v av ref0 = av ref1 3.6 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit resolution 10 bit overall error note 2.7 v av ref0 3.6 v 0.6 %fsr 3.0 v av ref0 3.6 v 2.6 24 s a/d conversion time t conv 2.7 v av ref0 3.0 v 3.9 24 s zero scale error 0.5 %fsr full scale error 0.5 %fsr non-linearity error 4.0 lsb differential linearity error 4.0 lsb analog input voltage v ian av ss av ref0 v reference voltage av ref0 2.7 3.6 v normal conversion mode 3 6.5 ma high-speed conversion mode 4 10 ma av ref0 current ai ref0 when a/d converter unused 5 a note excluding quantization error ( 0.05 %fsr). caution do not set (read/write) alternate-function ports during a/d conversion; otherwise the conversion resolution may be degraded. remark lsb: least significant bit fsr: full scale range
v850es/jg3-l chapter 32 el ectrical specif ications ( pd70f3737, 70f3738) r01uh0165ej0700 rev.7.00 page 987 of 1113 sep 22, 2011 32.8.8 d/a converter (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 8 bit overall error r = 2 m 1.2 %fsr settling time c = 20 pf 3 s output resistor r o output data 55h 6.42 k reference voltage av ref1 2.7 3.6 v d/a conversion operating 1 2.5 ma av ref1 current note ai ref1 d/a conversion stopped 5 a note value of 1 channel of d/a converter remark r is the output pin load resistance and c is the output pin load capacitance. 32.8.9 lvi circuit characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.2 to 3.6 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit v lvi0 2.7 2.8 2.9 v detection voltage v lvi1 2.2 2.3 2.4 v response time note t ld at rising edge: after v dd reaches v lvi0 /v lvi1 (max.) at falling edge: after v dd has dropped to v lvi0 /v lvi1 (min.) 0.2 2.0 ms minimum pulse width t lw v dd = v lvi0 /v lvi1 (min.) 0.2 ms reference voltage stabilization wait time t lwait after v dd reaches v lvi0 or v lvi1 (max.) 0.1 0.2 ms note time required to detect the detection volta ge and output an interrupt or reset signal. supply voltage (v dd ) time detection voltage (min.) operating voltage (min.) detection voltage (max.) t lwait t lw t ld t ld lvion bit = 0 1
v850es/jg3-l chapter 32 el ectrical specif ications ( pd70f3737, 70f3738) r01uh0165ej0700 rev.7.00 page 988 of 1113 sep 22, 2011 32.9 flash memory programming characteristics (1) basic characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.7 to 3.6 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit operating frequency f cpu 2.5 20 mhz supply voltage v dd 2.5 mhz f xx 20 mhz 2.7 3.6 v used for updating programs when using flash memory programmer and renesas electronics self programming library retained for 15 years 1,000 times number of rewrites c wrt used for updating data when using renesas electronics eeprom emulation library (usable rom size: 12 kb of 6 consecutive blocks, or 6 kb of 3 consecutive blocks) retained for 5 years 10,000 times programming temperature t prg ? 40 +85 c (2) serial write operation characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.7 to 3.6 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit flmd0, flmd1 setup time t mdset 2 3000 ms flmd0 count start time from reset t rfcf f x = 2.5 to 10 mhz 800 s flmd0 counter high-level width/ low-level width t ch /t cl 10 100 s flmd0 counter rise time/fall time t r /t f 1 s flash write mode setup timing v dd flmd1 0 v v dd reset (input) 0 v v dd flmd0 0 v t rfcf t cl t f t r t ch t mdset
v850es/jg3-l chapter 32 el ectrical specif ications ( pd70f3737, 70f3738) r01uh0165ej0700 rev.7.00 page 989 of 1113 sep 22, 2011 (3) programming characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.7 to 3.6 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit chip erase time f xx = 20 mhz (when the chip erase command is executed) 105 ms write time per 256 bytes f xx = 20 mhz 2.0 ms block internal verify time f xx = 20 mhz 10 ms block blank check time f xx = 20 mhz 0.5 ms flash memory information setting time f xx = 20 mhz 30 ms remark block size = 2 kb caution when writing initially to shipped products , it is counted as one rewrite for both ?erase and write? and ?write only?.
v850es/jg3-l chapter 33 el ectrical specifications ( pd70f3792, 70f3793) r01uh0165ej0700 rev.7.00 page 990 of 1113 sep 22, 2011 chapter 33 electrical specifications ( pd70f3792, 70f3793) 33.1 absolute maximum ratings absolute maximum ratings (t a = 25 c) (1/2) parameter symbol conditions ratings unit v dd v dd = ev dd = av ref0 = av ref1 ? 0.5 to +4.6 v ev dd v dd = ev dd = av ref0 = av ref1 ? 0.5 to +4.6 v rv dd v dd = ev dd = av ref0 = av ref1 ? 0.5 to +4.6 v av ref0 v dd = ev dd = av ref0 = av ref1 ? 0.5 to +4.6 v av ref1 v dd = ev dd = av ref0 = av ref1 ? 0.5 to +4.6 v v ss v ss = ev ss = av ss ? 0.5 to +0.5 v av ss v ss = ev ss = av ss ? 0.5 to +0.5 v supply voltage ev ss v ss = ev ss = av ss ? 0.5 to +0.5 v v i1 p97 to p915, pdh0 to pdh4, pcm0 to pcm3, pct0, pct1, pct4, pct6, pdl0 to pdl15, reset, flmd0 ? 0.5 to ev dd + 0.5 note 1 v v i2 p10, p11 ? 0.5 to av ref1 + 0.5 note 1 v x1 ? 0.5 to v dd + 0.5 note 1 v v i3 x2 ? 0.5 to v ro note 2 + 0.5 note 1 v i4 p02 to p06, p30 to p39, p40 to p42, p50 to p55, p90 to p96 ? 0.5 to +6.0 v input voltage v i5 xt1, xt2 ? 0.5 to v ro note 2 + 0.5 v analog input voltage v ian p70 to p711 ? 0.5 to av ref0 + 0.5 note 1 v notes 1. be sure not to exceed the absolute maximum ratings (max. value) of each supply voltage. 2. on-chip regulator output voltage cautions 1. do not directly connect the output (or i/o) pins of ic products to each other, or to v dd , v cc , and gnd. open-drain pins or open-collector pins, however, can be directly connected to each other. direct connection of the output pins between an ic product and an external circuit is possible, if the output pins can be set to th e high-impedance state a nd the output timing of the external circuit is designed to avoid output conflict. 2. product quality may suffer if the absolute maximum rati ng is exceeded even momentarily for any parameter. that is, the absolute m aximum ratings are rate d values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum rati ngs are not exceeded. the ratings and conditions indicated fo r dc characteristics, ac characteristics, and operating conditions represent the quality assurance range duri ng normal operation. remark unless specified otherwise, the ratings of alternate-fu nction pins are the same as those of port pins.
v850es/jg3-l chapter 33 el ectrical specifications ( pd70f3792, 70f3793) r01uh0165ej0700 rev.7.00 page 991 of 1113 sep 22, 2011 absolute maximum ratings (t a = 25 c) (2/2) parameter symbol conditions ratings unit per pin 4 ma p02 to p06, p30 to p39, p40 to p42, p50 to p55, p90 to p915, pdh4 total of all pins 50 ma per pin 4 ma pcm0 to pcm3, pct0, pct1, pct4, pct6, pdh0 to pdh3, pdl0 to pdl15 total of all pins 50 ma per pin 4 ma p10, p11 total of all pins 8 ma per pin 4 ma output current, low i ol p70 to p711 total of all pins 20 ma per pin ? 4 ma p02 to p06, p30 to p39, p40 to p42, p50 to p55, p90 to p915, pdh4 total of all pins ? 50 ma per pin ? 4 ma pcm0 to pcm3, pct0, pct1, pct4, pct6, pdh0 to pdh3, pdl0 to pdl15 total of all pins ? 50 ma per pin ? 4 ma p10, p11 total of all pins ? 8 ma per pin ? 4 ma output current, high i oh p70 to p711 total of all pins ? 20 ma normal operation mode ? 40 to +85 c operating ambient temperature t a flash memory programming mode ? 40 to +85 c storage temperature t stg ? 40 to +125 c cautions 1. do not directly connect the output (or i/o) pins of ic products to each other, or to v dd , v cc , and gnd. open-drain pins or open-collector pins, however, can be directly connected to each other. direct connection of the output pins between an ic product and an external circuit is possible, if the output pins can be set to th e high-impedance state a nd the output timing of the external circuit is designed to avoid output conflict. 2. product quality may suffer if the absolute maximum rati ng is exceeded even momentarily for any parameter. that is, the absolute m aximum ratings are rate d values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum rati ngs are not exceeded. the ratings and conditions indicated fo r dc characteristics, ac characteristics, and operating conditions represent the quality assurance range duri ng normal operation. remark unless specified otherwise, the ratings of alternate-fu nction pins are the same as those of port pins.
v850es/jg3-l chapter 33 el ectrical specifications ( pd70f3792, 70f3793) r01uh0165ej0700 rev.7.00 page 992 of 1113 sep 22, 2011 33.2 capacitance capacitance (t a = 25 c, v dd = ev dd = av ref0 = av ref1 = rv dd = v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit i/o capacitance c io f x = 1 mhz unmeasured pins returned to 0 v 10 pf 33.3 operating conditions (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v) supply voltage operating clock conditions v dd ev dd rv dd note1 av ref0 , av ref1 unit f xx = 10 to 20 mhz (main clock) regc = 4.7 f, a/d converter operating, d/a converter operating pll mode v f xx = 2.5 to 10 mhz (main clock) regc = 4.7 f, a/d converter operating, d/a converter operating clock-through mode 2.7 to 3.6 2.7 to 3.6 2.7 to 3.6 2.7 to 3.6 v f xx = 2.5 to 5 mhz (main clock) regc = 4.7 f, a/d converter stopped, d/a converter stopped clock-through mode 2.2 to 3.6 2.2 to 3.6 2.2 to 3.6 2.2 to 3.6 v f xx = 1.25 to 2.5 mhz note2 (main clock) regc = 4.7 f, a/d converter stopped, d/a converter stopped clock-through mode 2.0 to 3.6 2.0 to 3.6 2.0 to 3.6 2.0 to 3.6 v f xt = 32.768 khz (subclock) regc = 4.7 f, a/d converter stopped, d/a converter stopped 2.0 to 3.6 2.0 to 3.6 2.0 to 3.6 2.0 to 3.6 v f xt = 32.768 khz (subclock) regc = 4.7 f, a/d converter stopped, d/a converter stopped, rtc backup mode 0 to 3.6 0 to 3.6 1.8 to 3.6 0 to 3.6 v notes1. rv dd can be used as a separate potential without any ne ed to set it to the same potential as other power supply voltages. unless otherwise specified, use rv dd in this way under the above operating condition. 2. an operating clock of 1.25 mhz can only be specif ied when the ckthsel register is set to 1 (which specifies the clock-through frequency divided by 2). caution the operating conditions will not be satisfied if rv dd falls below 1.8 v. in this case, therefore, be sure to initialize the rtc (by clearing the rc1cc0.rc1pwr bit (0)) once rv dd is restored (to 1.8 v or higher) after having fallen below 1.8 v during operation. note that the rtc will be initialized if power is applied with rv dd = 0.
v850es/jg3-l chapter 33 el ectrical specifications ( pd70f3792, 70f3793) r01uh0165ej0700 rev.7.00 page 993 of 1113 sep 22, 2011 33.4 oscillator characteristics 33.4.1 main clock osc illator characteristics (1) main clock oscilla tor characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v) resonator circuit example paramete r conditions min. typ. max. unit v dd = 2.0 to 3.6 v 2.5 2.5 mhz v dd = 2.2 to 3.6 v 2.5 5 mhz clock through mode v dd = 2.7 to 3.6 v 2.5 10 mhz oscillation frequency (f x ) note 1 v dd = 2.7 to 3.6 v in pll mode 2.5 5 mhz v dd = 2.0 to 3.6 v immediately after reset ends note 3 note 4 s v dd = 2.0 to 3.6 v in clock through mode 400 note 5 note 6 s after stop mode is released v dd = 2.7 to 3.6 v in pll mode 400 note 7 note 6 s v dd = 2.0 to 3.6 v in clock through mode 200 note 5 note 6 s ceramic resonator/ crystal resonator x2 x1 oscillation stabilization time note 2 after idle2 mode is released v dd = 2.7 to 3.6 v in pll mode 400 note 7 note 6 s notes 1. the oscillation frequency shown above indicates only os cillator characteristics. use the v850es/jg3-l so that the internal operating condit ions do not exceed the ratings shown in ac characteristics , dc characteristics , and operating conditions . 2. the wait time required from when the resonator starts oscillating until oscillation stabilizes. 3. the oscillation stabilization time after reset release is restricted in accordance with the set value of the option byte. for details, see chapter 29 option byte . 4. the oscillation stabilization time differs depending on the set value of the option byte. for details, see chapter 29 option byte . 5. time required to set up the regulator and flash memory . secure the setup time using the osts register. 6. the value varies depending on the setting of the osts register. 7. time required to set up the regulator, flash memory, and pll. secure the setup time using the osts register. caution 1. when using the main clock oscillator, wire as follows in the ar ea enclosed by th e broken lines in the above figure to avo id an adverse effect from wiring capacitance. ? keep the wiring lengt h as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line th rough which a high fluctuating current flows. ? always make the ground point of the o scillator capacitor the same potential as v ss . ? do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. caution 2. when the main clock is stopped and th e device is operating on the subclock, wait until the oscillation stabilization time has been secured by the program before switching back to the main clock.
v850es/jg3-l chapter 33 el ectrical specifications ( pd70f3792, 70f3793) r01uh0165ej0700 rev.7.00 page 994 of 1113 sep 22, 2011 (a) kyocera kinseki corporation: crystal resonator (t a = ? 10 to +70 c) note1 recommended circuit constant oscillation voltage range oscillation stabilizatio n time note2 type circuit example part number oscillation frequency f x (mhz) load capacitan ce (pf) c1 (pf) c2 (pf) rd ( ) min. (v) max. (v) max. (ms) cx49gfnb, cx1255gb, cx8045gb 4.000 8 10 10 0 2.0 3.6 2.26 cx49gfnb, cx1255gb, cx8045gb 5.000 8 10 10 0 2.0 3.6 1.61 cx49gfnb, cx1255gb, cx8045gb 6.000 8 10 10 0 2.0 3.6 1.02 cx49gfnb, cx1255gb, cx8045gb 8.000 8 10 10 0 2.0 3.6 0.87 surface mounting cx49gfnb, cx1255gb, cx8045gb 10.000 8 10 10 0 2.0 3.6 0.57 hc49sfnb 4.000 8 10 10 0 2.0 3.6 2.26 hc49sfnb 5.000 8 10 10 0 2.0 3.6 1.61 hc49sfnb 6.000 8 10 10 0 2.0 3.6 1.02 hc49sfnb 8.000 8 10 10 0 2.0 3.6 0.87 lead x2 x1 c1 c2 rd hc49sfnb 10.000 8 10 10 0 2.0 3.6 0.57 notes1. contact the resonator manufacturer regarding use at a temperature outside this range. 2. the oscillation stabilization time is slightly longer when using the cx8045gb. contact the resonator manufacturer for details. caution this oscillator constant is a reference value based on evalua tion under a specific environment by the resonator manufacturer. if optimization of oscillator characteristics is necessary in the actual application, apply to the resonator manufacturer for evaluation on the implementation circuit. the oscillation voltage and osc illation frequency indicate only osc illator characteris tics. use the v850es/jg3-l so that the internal operating condit ions are within the specifications of the ac characteristics, dc characterist ics, and operating conditions.
v850es/jg3-l chapter 33 el ectrical specifications ( pd70f3792, 70f3793) r01uh0165ej0700 rev.7.00 page 995 of 1113 sep 22, 2011 (b) murata mfg. co. lt d.: ceramic resonator (t a = ? 20 to +80 c) note recommended circuit constant oscillation voltage range oscillation stabilization time type circuit example part number oscillation frequency f x (mhz) c1 (pf) c2 (pf) rd ( ) min. (v) max. (v) max. (ms) cstcc2m50g56-r0 2.500 (47) (47) 2200 2.0 3.6 0.02 cstcr4m00g55-r0 4.000 (39) (39) 680 2.0 3.6 0.02 cstcr5m00g55-r0 5.000 (39) (39) 680 2.0 3.6 0.02 cstcr6m00g55-r0 6.000 (39) (39) 470 2.0 3.6 0.02 cstce8m00g55-r0 8.000 (33) (33) 0 2.0 3.6 0.03 surface mounting cstce10m0g55-r0 10.000 (33) (33) 0 2.0 3.6 0.03 cstls4m00g56-b0 4.000 (47) (47) 680 2.0 3.6 0.02 cstls5m00g56-b0 5.000 (47) (47) 680 2.0 3.6 0.02 cstls6m00g56-b0 6.000 (47) (47) 470 2.0 3.6 0.02 cstls8m00g56-b0 8.000 (47) (47) 0 2.0 3.6 0.03 lead x2 x1 c1 c2 rd cstls10m0g56-b0 10.000 (47) (47) 0 2.1 3.6 0.03 note contact the resonator ma nufacturer regarding use at a temperature outside this range. caution this oscillator constant is a reference value based on evaluati on under a specific environment by the resonator manufacturer. if optimization of oscillator characteristics is necessary in the actual app lication, apply to the resonator manufacturer for evaluation on the implementation circuit. the oscillation voltage and osc illation frequency indicate only osc illator characteris tics. use the v850es/jg3-l so that the intern al operating conditions are withi n the specifications of the ac characteristics, dc characterist ics, and operating conditions. remark figures in parentheses in columns c1 and c2 indi cate the capacitance incorporated in the resonator. (2) external clock (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.7 to 3.6 v, v ss = ev ss = av ss = 0 v) resonator circuit example paramete r conditions min. typ. max. unit clock through mode 2.5 5 mhz input frequency (f x ) note pll mode 2.5 5 mhz v ih x1 2.3 v dd v external clock open external clock cmos inverter x2 x1 v il x1 v ss 0.4 v note keep the duty factor of the input waveform to within 45% to 55%. cautions 1. be sure to disconnect the internal feedback resistor after reset (set pcc.mfrc = 1). 2. leave the x2 pin open. 3. make sure that the cmos inverter is as close to the x1 pin as possible.
v850es/jg3-l chapter 33 el ectrical specifications ( pd70f3792, 70f3793) r01uh0165ej0700 rev.7.00 page 996 of 1113 sep 22, 2011 33.4.2 subclock oscilla tor characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.0 to 3.6 v, v ss = ev ss = av ss = 0 v) resonator circuit example parameter conditions min. typ. max. unit oscillation frequency (f xt ) note 1 32 32.768 35 khz crystal resonator xt2 xt1 oscillation stabilization time note 2 10 s notes 1. the oscillation frequency shown above indicates only os cillator characteristics. use the v850es/jg3-l so that the internal operation condit ions do not exceed the ratings shown in ac characteristics , dc characteristics , and operating conditions. 2. time required from when rv dd reaches the oscillation voltage range (2.0 v (min.)) to when the crystal resonator stabilizes. cautions 1. when using the subclock oscillator, wire as follows in the area enclosed by th e broken lines in the above figures to avo id an adverse effect fr om wiring capacitance. ? keep the wiring le ngth as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the oscillator capacitor the same potential as v ss . ? do not ground the capacitor to a groun d pattern through which a high current flows. ? do not fetch signals from the oscillator. 2. the subclock oscillator is designed as a low-amplitude circuit for reducing power consumption, and is mo re prone to malfunction due to noi se than the main clock oscillator. particular care is theref ore required with the wiring met hod when the subclock is used. 3. for the resonator selection and oscillator constant, custom ers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
v850es/jg3-l chapter 33 el ectrical specifications ( pd70f3792, 70f3793) r01uh0165ej0700 rev.7.00 page 997 of 1113 sep 22, 2011 (a) seiko instruments inc.: crystal resonator (t a = ? 40 to +85 c) oscillation frequency: f xt = 32.768 khz recommended circuit constant oscillation voltage range type circuit example part number load capacitance of crystal resonator (pf) c1 (pf) c2 (pf) rd ( ) min. (v) max. (v) lead xt2 xt1 c1 c2 rd vt-200-f 12.5 22 22 220 1.8 3.6 caution this oscillator constant is a reference value based on evalua tion under a specific environment by the resonator manufacturer. if optimization of oscillator characteristics is necessary in the actual application, apply to the resonator manufacturer for evaluation on the implementation circuit. the oscillation voltage and osc illation frequency indicate only osc illator characteris tics. use the v850es/jg3-l so that the internal operating condit ions are within the specifications of the ac characteristics, dc characterist ics, and operating conditions. (b) citizen miyota co., ltd.: crystal resonator (t a = ? 40 to +85 c) oscillation frequency: f xt = 32.768 khz recommended circuit constant oscillation voltage range type circuit example part number load capacitance of crystal resonator (pf) c1 (pf) c2 (pf) rd ( ) min. (v) max. (v) surface mounting xt2 xt1 c1 c2 rd cmr200t 9 15 18 100 1.8 3.6 caution this oscillator constant is a reference value based on evalua tion under a specific environment by the resonator manufacturer. if optimization of oscillator characteristics is necessary in the actual application, apply to the resonator manufacturer for evaluation on the implementation circuit. the oscillation voltage and osc illation frequency indicate only osc illator characteris tics. use the v850es/jg3-l so that the internal operating condit ions are within the specifications of the ac characteristics, dc characterist ics, and operating conditions.
v850es/jg3-l chapter 33 el ectrical specifications ( pd70f3792, 70f3793) r01uh0165ej0700 rev.7.00 page 998 of 1113 sep 22, 2011 33.4.3 pll characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit input frequency f x 2.5 5 mhz output frequency f xx 10 20 mhz lock time t pll after v dd reaches 2.7 v (min.) 400 s 33.4.4 internal oscillat or characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit output frequency f r 100 220 400 khz
v850es/jg3-l chapter 33 el ectrical specifications ( pd70f3792, 70f3793) r01uh0165ej0700 rev.7.00 page 999 of 1113 sep 22, 2011 33.5 regulator characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit f xx = 20 mhz (max.) 2.7 3.6 v f xx = 5 mhz (max.) 2.2 3.6 v f xx = 2.5 mhz (max.) 2.0 3.6 v input voltage v dd data retained (stop mode) 1.9 3.6 v output voltage v ro v dd = 2.7 to 3.6 v 2.5 v after v dd reaches 2.7 v (min.), stabilization capacitance c = 4.7 f (recommended value) connected to regc pin 1 ms after v dd reaches 2.2 v (min.), stabilization capacitance c = 4.7 f (recommended value) connected to regc pin 3.5 ms regulator output stabilization time t reg after v dd reaches 2.0 v (min.), stabilization capacitance c = 4.7 f (recommended value) connected to regc pin 4.5 ms external capacitance regc permissible error of external capacitance to be connected to regc pin 3.76 4.70 5.64 f v dd v ro t reg reset
v850es/jg3-l chapter 33 el ectrical specifications ( pd70f3792, 70f3793) r01uh0165ej0700 rev.7.00 page 1000 of 1113 sep 22, 2011 33.6 dc characteristics 33.6.1 pin characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.0 to 3.6 v, v ss = ev ss = av ss = 0 v) (1/2) parameter symbol conditions min. typ. max. unit v ih1 reset, flmd0, p97 to p915 0.8ev dd ev dd v v ih2 p02 to p06, p30 to p37, p42, p50 to p55, p92 to p96 0.8ev dd 5.5 v v ih3 p38, p39, p40, p41, p90, p91 0.7ev dd 5.5 v v ih4 pcm0 to pcm3, pct0, pct1, pct4, pct6, pdh0 to pdh4, pdl0 to pdl15 0.7ev dd ev dd v v ih5 p70 to p711 0.7av ref0 av ref0 v input voltage, high v ih6 p10, p11 0.7av ref1 av ref1 v v il1 reset, flmd0, p97 to p915 ev ss 0.2ev dd v v il2 p02 to p06, p30 to p37, p42, p50 to p55, p92 to p96 ev ss 0.2ev dd v v il3 p38, p39, p40, p41, p90, p91 ev ss 0.3ev dd v v il4 pcm0 to pcm3, pct0, pct1, pct4, pct6, pdh0 to pdh4, pdl0 to pdl15 ev ss 0.3ev dd v v il5 p70 to p711 av ss 0.3av ref0 v input voltage, low v il6 p10, p11 av ss 0.3av ref1 v input leakage current, high i lih v i = v dd = ev dd = av ref0 = av ref1 5 a input leakage current, low i lil v i = 0 v ? 5 a output leakage current, high i loh v o = v dd = ev dd = av ref0 = av ref1 5 a output leakage current, low i lol v o = 0 v ? 5 a remark unless specified otherwise, the characteristics of alte rnate-function pins are t he same as those of port pins.
v850es/jg3-l chapter 33 el ectrical specifications ( pd70f3792, 70f3793) r01uh0165ej0700 rev.7.00 page 1001 of 1113 sep 22, 2011 (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.0 to 3.6 v, v ss = ev ss = av ss = 0 v) (2/2) parameter symbol conditions min. typ. max. unit per pin i oh = ? 1.0 ma total of all pins ? 20 ma ev dd ? 1.0 ev dd v v oh1 p02 to p06, p30 to p39, p40 to p42, p50 to p55, p90 to p915, pdh4 per pin i oh = ? 100 a total of all pins ? 4.1 ma ev dd ? 0.5 ev dd v per pin i oh = ? 1.0 ma total of all pins ? 20 ma ev dd ? 1.0 ev dd v v oh2 pcm0 to pcm3, pct0, pct1, pct4, pct6, pdh0 to pdh3, pdl0 to pdl15 per pin i oh = ? 100 a total of all pins ? 2.8 ma ev dd ? 0.5 ev dd v per pin i oh = ? 0.4 ma total of all pins ? 4.8 ma av ref0 ? 1.0 av ref0 v v oh3 p70 to p711 per pin i oh = ? 100 a total of all pins ? 1.2 ma av ref0 ? 0.5 av ref0 v per pin i oh = ? 0.4 ma total of all pins ? 0.8 ma av ref1 ? 1.0 av ref1 v output voltage, high v oh4 p10, p11 per pin i oh = ? 100 a total of all pins ? 0.2 ma av ref1 ? 0.5 av ref1 v v ol1 p02 to p06, p30 to p37, p42, p50 to p55, p92 to p915, pdh4 per pin i ol = 1.0 ma 0 0.4 v v ol2 p38, p39, p40, p41, p90, p91 per pin i ol = 3.0 ma total of all pins 20 ma 0 0.4 v v ol3 pcm0 to pcm3, pct0, pct1, pct4, pct6, pdh0 to pdh3, pdl0 to pdl15 per pin i ol = 1.0 ma total of all pins 20 ma 0 0.4 v output voltage, low v ol4 p10, p11, p70 to p711 per pin i ol = 0.4 ma total of all pins 5.6 ma 0 0.4 v software pull-down resistor note r 1 p05 v i = v dd 10 20 100 k note drst pin only (controlled by ocdm register) remarks 1. unless specified otherwise, the charac teristics of alternate-function pins are the same as those of port pins. 2. when the i oh and i ol conditions are not satisfied for a pin but t he total value of all pins is satisfied, only that pin does not satisf y the dc characteristics.
v850es/jg3-l chapter 33 el ectrical specifications ( pd70f3792, 70f3793) r01uh0165ej0700 rev.7.00 page 1002 of 1113 sep 22, 2011 33.6.2 supply current characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. note 1 max. note 2 unit f xx = 20 mhz (f x = 5 mhz) note 3 12 23 ma i dd1 normal operation f xx = 10 mhz (f x = 10 mhz), pll off note 3 6 10 ma i dd2 halt mode f xx = 20 mhz (f x = 5 mhz) note 3 7.5 14 ma i dd3 idle1 mode f xx = 5 mhz (f x = 5 mhz), pll off note 3 0.6 1 ma i dd4 idle2 mode f xx = 5 mhz (f x = 5 mhz), pll off note 3 0.28 0.5 ma i dd5 subclock operation mode f xt = 32.768 khz, main clock stopped, internal oscillator stopped, pll off note 3 regovl0 = 02h (low-voltage subclock operation mode), csibn stopped note 5 , uarta0 stopped note 5 18 a i dd6 sub-idle mode f xt = 32.768 khz, main clock stopped, internal oscillator stopped, pll off note 3 regovl0 = 02h (low-voltage sub-idle mode), csibn stopped note 5 , uarta0 stopped note 5 3.5 50 a subclock stopped, internal oscillator stopped, regovl0 = 01h (low-voltage stop mode), t a = 25 c 1.5 3.0 a subclock stopped, internal oscillator stopped, regovl0 = 01h (low-voltage stop mode), t a = 85 c 45 a i dd7 stop mode subclock operating, internal oscillator stopped, regovl0 = 01h (low-voltage stop mode) note 3 , csibn stopped note 5 , uarta0 stopped note 5 3.5 50 a supply current notes 4 i dd8 self programming mode f xx = 20 mhz (f x = 5 mhz) 14 24 ma lvi current i lvi 1.2 3 a wdt, internal oscillation current i wdt 5 a rtc back-up mode notes 4 i rtc rtc backup mode subclock operating t a = 70 c rv dd voltage, v dd = 0 v 1 a notes 1. typ. current is a value at v dd = ev dd = rv dd = 3.3 v, t a = 25 c. the typ. value is not a value guaranteed for each device. 2. max. current is a value at which the characterist ic in question is at the worst-case value at v dd = ev dd = rv dd = 3.6 v, t a = ? 40 to +85 c. 3. typ. value indicates the current value when "rtc " or "watch timer + tmm (count by watch timer interrupt)" operate as peripheral functions.max. val ue indicates the current value when all the functions operable in a range in which the pin status is not changed operate as peripheral functions. however, i lvi and i wdt are excluded. 4. total of v dd , ev dd and rv dd currents. currents i lvi and i wdt flowing through the output buffers, a/d converter, d/a converter, and on-chip pull-down resistor are not included. 5. csibn and uarta0 can be operated using sckbn and ascka0 respectively, but the target spec is the current value when csibn and uarta0 are stopped. remark for details about the operating voltage, see 33.3 operating conditions .
v850es/jg3-l chapter 33 el ectrical specifications ( pd70f3792, 70f3793) r01uh0165ej0700 rev.7.00 page 1003 of 1113 sep 22, 2011 33.6.3 data retention charact eristics (in stop mode) (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit data retention voltage v dddr stop mode (all functions stopped) 1.9 3.6 v data retention current i dddr subclock stopped, internal oscillator stopped t a = 85 c 45 a supply voltage rise time t rvd 200 s supply voltage fall time t fvd 200 s supply voltage retention time t hvd after stop mode setting 0 ms stop release signal input time t drel after v dd reaches the operating voltage min. (see 33.3 operating conditions ) 0 ms data retention input voltage, high v ihdr v dd = ev dd = v dddr 0.9v dddr v dddr v data retention input voltage, low v ildr v dd = ev dd = v dddr 0 0.1v dddr v caution shifting to stop mode and restoring from stop mode must be performed within the rated operating range. t drel t hvd t fvd t rvd stop release signal input stop mode setting v dddr v ihdr v ihdr v ildr v dd /ev dd reset (input) stop mode release interrupt (nmi, etc.) (released by falling edge) stop mode release interrupt (nmi, etc.) (released by rising edge) operating voltage lower limit
v850es/jg3-l chapter 33 el ectrical specifications ( pd70f3792, 70f3793) r01uh0165ej0700 rev.7.00 page 1004 of 1113 sep 22, 2011 33.7 ac characteristics 33.7.1 measurement conditions (1) ac test input measurement points v dd v ss v ih v il v ih v il measurement points (2) ac test output measurement points v oh v ol v oh v ol measurement points (3) load conditions dut (device under measurement) c l = 50 pf caution if the load capacitance exceeds 50 pf due to the circuit configuration, bring the load capacitance of the device to 50 pf or less by inserting a buffer or by some other means.
v850es/jg3-l chapter 33 el ectrical specifications ( pd70f3792, 70f3793) r01uh0165ej0700 rev.7.00 page 1005 of 1113 sep 22, 2011 33.7.2 clkout output timing (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.7 to 3.6 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit output cycle t cyk <1> 50 ns 31.25 s high-level width t wkh <2> t cyk /2 ? 10 ns low-level width t wkl <3> t cyk /2 ? 10 ns rise time t kr <4> 10 ns fall time t kf <5> 10 ns clkout (output) <1> <2> <3> <4> <5>
v850es/jg3-l chapter 33 el ectrical specifications ( pd70f3792, 70f3793) r01uh0165ej0700 rev.7.00 page 1006 of 1113 sep 22, 2011 33.7.3 bus timing the values for just the access method to be used (syn chronous with or asynchronous to clkout) must be satisfied. it is not necessary to satisfy the values for both methods. (1) in multiplexed bus mode (a) read/write cycle (a synchronous to clkout) (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.7 to 3.6 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit address setup time (to astb ) t sast <6> (0.5 + t asw )t ? 20 ns address hold time (from astb ) t hsta <7> (0.5 + t ahw )t ? 15 ns delay time from rd to address float t frda <8> 10 ns data input setup time from address t said <9> (2 + n + t asw + t ahw )t ? 35 ns data input setup time from rd t srid <10> (1 + n)t ? 25 ns delay time from astb to rd, wrm t dstrdwr <11> (0.5 + t ahw )t ? 15 ns data input hold time (from rd ) t hrdid <12> 0 ns address output time from rd t drda <13> (1 + i)t ? 15 ns delay time from rd, wrm to astb t drdwrst <14> 0.5t ? 15 ns delay time from rd to astb t drdst <15> (1.5 + i + t asw )t ? 15 ns rd, wrm low-level width t wrdwrl <16> (1 + n)t ? 15 ns astb high-level width t wsth <17> (1 + i + t asw )t ? 15 ns data output time from wrm t dwrod <18> 15 ns data output setup time (to wrm ) t sodwr <19> (1 + n)t ? 20 ns data output hold time (from wrm ) t hwrod <20> t ? 15 ns t sawt1 <21> n 1 (1.5 + t asw + t ahw )t ? 35 ns wait setup time (to address) t sawt2 <22> (1.5 + n + t asw + t ahw )t ? 35 ns t hawt1 <23> n 1 (0.5 + n + t asw + t ahw )t ns wait hold time (from address) t hawt2 <24> (1.5 + n + t asw + t ahw )t ns t sstwt1 <25> n 1 (1 + t ahw )t ? 25 ns wait setup time (to astb ) t sstwt2 <26> (1 + n + t ahw )t ? 25 ns t hstwt1 <27> n 1 (n + t ahw )t ns wait hold time (from astb ) t hstwt2 <28> (1 + n + t ahw )t ns address hold time from rd t hrda2 <29> (1 + i)t ? 15 ns address hold time from wrm t hwra2 <30> t ? 15 ns remarks 1. t asw : number of address setup wait clocks (0 or 1) t ahw : number of address hold wait clocks (0 or 1) 2. t = 1/f cpu (f cpu : cpu operating clock frequency) 3. n: number of wait clocks inserted in the bus cycle the sampling timing changes when a programmable wait is inserted. 4. m = 0, 1 5. i: number of idle states inserted after a read cycle (0 or 1) 6. the values in the above specifications are values for when clo cks with a 1:1 duty ratio are input from x1.
v850es/jg3-l chapter 33 el ectrical specifications ( pd70f3792, 70f3793) r01uh0165ej0700 rev.7.00 page 1007 of 1113 sep 22, 2011 read cycle (asynchronous to clkout): in mu ltiplexed bus mode clkout (output) a16 to a21 (output) ad0 to ad15 (i/o) astb (output) rd (output) wait (input) t1 t2 tw t3 data address hi-z <6> <7> <17> <9> <12> <14> <10> <11> <25> <27> <26> <28> <21> <23> <22> <24> <16> <8> <13> <29> <15> remark wr0 and wr1 are high level.
v850es/jg3-l chapter 33 el ectrical specifications ( pd70f3792, 70f3793) r01uh0165ej0700 rev.7.00 page 1008 of 1113 sep 22, 2011 write cycle (asynchronous to clko ut): in multiplexed bus mode clkout (output) ad0 to ad15 (i/o) astb (output) wr0, wr1 (output) wait (input) t1 t2 tw t3 data address <25> <27> <26> <28> <21> <23> <22> <24> <6> <17> <7> <14> <20> <30> <19> <16> <11> <18> a16 to a21 (output) remark rd is high level.
v850es/jg3-l chapter 33 el ectrical specifications ( pd70f3792, 70f3793) r01uh0165ej0700 rev.7.00 page 1009 of 1113 sep 22, 2011 (b) read/write cycle (synchronous with clkout): in multiplexed bus mode (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.7 to 3.6 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit delay time from clkout to address t dka <31> 0 25 ns delay time from clkout to address float t fka <32> 0 19 ns delay time from clkout to astb t dkst <33> ? 12 7 ns delay time from clkout to rd, wrm t dkrdwr <34> ? 5 14 ns data input setup time (to clkout ) t sidk <35> 15 ns data input hold time (from clkout ) t hkid <36> 5 ns data output delay time from clkout t dkod <37> 19 ns wait setup time (to clkout ) t swtk <38> 20 ns wait hold time (from clkout ) t hkwt <39> 5 ns address hold time from clkout t hka2 <40> 0 25 ns data output hold time from clkout t hkdw <41> 0 ns address hold time from clkout t hkaw <42> 0 ns remarks 1. m = 0, 1 2. the values in the above specifications are values for when cl ocks with a 1:1 duty ratio are input from x1. 3. for details about the clkout output timing, see 33.7.2 clkout output timing . read cycle (synchronous with clkout): in multiplexed bus mode clkout (output) a16 to a21 (output) ad0 to ad15 (i/o) astb (output) rd (output) wait (input) t1 t2 tw t3 ti t1 data address hi-z <31> <33> <34> <32> <31> <33> <40> <34> <38> <38> <39> <39> <35> <36> remark wr0 and wr1 are high level.
v850es/jg3-l chapter 33 el ectrical specifications ( pd70f3792, 70f3793) r01uh0165ej0700 rev.7.00 page 1010 of 1113 sep 22, 2011 write cycle (synchronous with clko ut): in multiplexed bus mode clkout (output) ad0 to ad15 (i/o) astb (output) wr0, wr1 (output) wait (input) t1 t2 tw t3 data address <31> <33> <34> <34> <39> <39> <38> <38> <33> <41> <42> <37> a16 to a21 (output) remark rd is high level.
v850es/jg3-l chapter 33 el ectrical specifications ( pd70f3792, 70f3793) r01uh0165ej0700 rev.7.00 page 1011 of 1113 sep 22, 2011 (2) in separate bus mode (a) read cycle (asynchronous to clkout): in separate bus mode (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.7 to 3.6 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit address setup time (to rd ) t sard <43> (0.5 + t asw )t ? 27 ns address hold time (from rd ) t hard <44> it ? 2 note ns rd low-level width t wrdl <45> (1.5 + n + t ahw )t ? 10 ns data setup time (to rd ) t sisd <46> 23 ns data hold time (from rd ) t hisd <47> ? 2 ns data setup time (to address) t said <48> (2 + n + t asw + t ahw )t ? 40 ns t srdwt1 <49> (0.5 + t ahw )t ? 25 ns wait setup time (to rd ) t srdwt2 <50> (0.5 + n + t ahw )t ? 25 ns t hrdwt1 <51> (n ? 0.5 + t ahw )t ns wait hold time (from rd ) t hrdwt2 <52> (n + 0.5 + t ahw )t ns t sawt1 <53> (1 + t asw + t ahw )t ? 45 ns wait setup time (to address) t sawt2 <54> (1 + n + t asw + t ahw )t ? 45 ns t hawt1 <55> (n + t asw + t ahw )t ns wait hold time (from address) t hawt2 <56> (1 + n + t asw + t ahw )t ns data output delay time from rd t drdod1 <57> (1 + i + t asw )t ? 15 ns note the address may be changed during the low-level period of the rd pin. to avoid the address change, insert an idle state. remarks 1. t asw : number of address setup wait clocks t ahw : number of address hold wait clocks 2. t = 1/f cpu (f cpu : cpu operating clock frequency) 3. n: number of wait clocks inserted in the bus cycle the sampling timing changes when a programmable wait is inserted. 4. i: number of idle states inserted after a read cycle (0 or 1) 5. the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1.
v850es/jg3-l chapter 33 el ectrical specifications ( pd70f3792, 70f3793) r01uh0165ej0700 rev.7.00 page 1012 of 1113 sep 22, 2011 read cycle (asynchronous to cl kout): in separate bus mode clkout (output) t1 <48> hi-z hi-z <43> <45> <52> <50> <51> <49> <53> <55> <54> <56> <47> <46> <57> <44> tw t2 rd (output) wr0, wr1 (output) a0 to a21 (output) ad0 to ad15 (i/o) wait (input) remark wr0 and wr1 are high level.
v850es/jg3-l chapter 33 el ectrical specifications ( pd70f3792, 70f3793) r01uh0165ej0700 rev.7.00 page 1013 of 1113 sep 22, 2011 (b) write cycle (asynchronous to clkout): in separate bus mode (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.7 to 3.6 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit address setup time (to wrm ) t sawr <58> (1 + t asw + t ahw )t ? 27 ns address hold time (from wrm ) t hawr <59> 0.5t ? 6 ns wrm low-level width t wwrl <60> (0.5 + n)t ? 10 ns data output time from wrm t dosdw <61> ? 5 ns data setup time (to wrm ) t sosdw <62> (0.5 + n)t ? 20 ns data hold time (from wrm ) t hosdw <63> 0.5t ? 7 ns data setup time (to address) t saod <64> (1 + t asw + t ahw )t ? 25 ns t swrwt1 <65> 22 ns wait setup time (to wrm ) t swrwt2 <66> nt ? 22 ns t hwrwt1 <67> 0 ns wait hold time (from wrm ) t hwrwt2 <68> nt ns t sawt1 <69> (1 + t asw + t ahw )t ? 45 ns wait setup time (to address) t sawt2 <70> (1 + n + t asw + t ahw )t ? 45 ns t hawt1 <71> (n + t asw + t ahw )t ns wait hold time (from address) t hawt2 <72> (1 + n + t asw + t ahw )t ns remarks 1. m = 0, 1 2. t asw : number of address setup wait clocks t ahw : number of address hold wait clocks 3. t = 1/f cpu (f cpu : cpu operating clock frequency) 4. n: number of wait clocks inserted in the bus cycle the sampling timing changes when a programmable wait is inserted. 5. the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1.
v850es/jg3-l chapter 33 el ectrical specifications ( pd70f3792, 70f3793) r01uh0165ej0700 rev.7.00 page 1014 of 1113 sep 22, 2011 write cycle (asynchronous to cl kout): in separate bus mode clkout (output) t1 <64> <58> <61> <60> <68> <66> <67> <65> <69> <71> <70> <72> <63> <62> <59> tw t2 wr0, wr1 (output) a0 to a21 (output) ad0 to ad15 (i/o) wait (input) hi-z hi-z remark rd is high level.
v850es/jg3-l chapter 33 el ectrical specifications ( pd70f3792, 70f3793) r01uh0165ej0700 rev.7.00 page 1015 of 1113 sep 22, 2011 (c) read cycle (synchronous with clkout): in separate bus mode (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.7 to 3.6 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit delay time from clkout to address t dksa <73> 0 27 ns data input setup time (to clkout ) t sisdk <74> 20 ns data input hold time (from clkout ) t hkisd <75> 0 ns delay time from clkout to rd t dksr <76> ? 2 12 ns wait setup time (to clkout ) t swtk <77> 20 ns wait hold time (from clkout ) t hkwt <78> 0 ns remarks 1. the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1. 2. for details about the clkout output timing, see 33.7.2 clkout output timing . read cycle (synchronous with clkout , 1 wait): in separate bus mode clkout (output) t1 <76> <77> <78> <77> <78> <73> <76> <74> <75> hi-z hi-z tw t2 rd (output) a0 to a21 (output) ad0 to ad15 (i/o) wait (input) <73> remark wr0 and wr1 are high level.
v850es/jg3-l chapter 33 el ectrical specifications ( pd70f3792, 70f3793) r01uh0165ej0700 rev.7.00 page 1016 of 1113 sep 22, 2011 (d) write cycle (synchronous with clkout): in separate bus mode (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.7 to 3.6 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit delay time from clkout to address t dksa <79> 0 27 ns delay time from clkout to data output t dksd <80> 0 18 ns delay time from clkout to wrm t dksw <81> ? 2 12 ns wait setup time (to clkout ) t swtk <82> 20 ns wait hold time (from clkout ) t hkwt <83> 0 ns remarks 1. m = 0, 1 2. the values in the above specifications are values for when cl ocks with a 1:1 duty ratio are input from x1. 3. for details about the clkout output timing, see 33.7.2 clkout output timing . write cycle (synchronous with cl kout): in separate bus mode clkout (output) t1 <80> <81> <83> <82> <81> tw t2 wr0, wr1 (output) a0 to a21 (output) ad0 to ad15 (i/o) wait (input) <79> <79> <83> <82> <80> hi-z hi-z remark rd is high level.
v850es/jg3-l chapter 33 el ectrical specifications ( pd70f3792, 70f3793) r01uh0165ej0700 rev.7.00 page 1017 of 1113 sep 22, 2011 (3) bus hold (a) asynchronous to clkout (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.7 to 3.6 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit hldrq high-level width t whqh <84> t + 10 ns hldak low-level width t whal <85> t ? 15 ns delay time from hldak to bus output t dhac <86> ? 3 ns delay time from hldrq to hldak t dhqha1 <87> (2n + 7.5)t + 26 ns delay time from hldrq to hldak t dhqha2 <88> 0.5t 1.5t + 26 ns remarks 1. t = 1/f cpu (f cpu : cpu operating clock frequency) 2. n: number of wait clocks inserted in the bus cycle the sampling timing changes when a programmable wait is inserted. 3. the values in the above specifications are values for when cl ocks with a 1:1 duty ratio are input from x1. bus hold (asynchronous to clkout) clkout (output) hldrq (input) hldak (output) address bus (output) data bus (i/o) th th th ti ti hi-z astb (output) rd (output), wr0, wr1 (output) hi-z hi-z <84> <88> <85> <86> <87>
v850es/jg3-l chapter 33 el ectrical specifications ( pd70f3792, 70f3793) r01uh0165ej0700 rev.7.00 page 1018 of 1113 sep 22, 2011 (b) synchronous with clkout (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.7 to 3.6 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit hldrq setup time (to clkout ) t shqk <89> 20 ns hldrq hold time (from clkout ) t hkhq <90> 5 ns delay time from clkout to bus float t dkf <91> 19 ns delay time from clkout to hldak t dkha <92> 19 ns remarks 1. the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1. 2. for details about the clkout output timing, see 33.7.2 clkout output timing . bus hold (synchronous with clkout) clkout (output) hldrq (input) hldak (output) address bus (output) data bus (i/o) th th th t2 t3 ti ti hi-z astb (output) rd (output), wr0, wr1 (output) hi-z hi-z <89> <89> <92> <92> <90> <91>
v850es/jg3-l chapter 33 el ectrical specifications ( pd70f3792, 70f3793) r01uh0165ej0700 rev.7.00 page 1019 of 1113 sep 22, 2011 33.7.4 power on/power off/reset timing (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.0 to 3.6 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit ev dd v dd t rel <93> 0 ns ev dd av ref0 , av ref1 t rea <94> 0 t rel ns v dd reset t rer <95> 500 + t reg note ns reset low-level width t wrsl <96> 500 ns reset v dd t fre <97> 500 ns v dd ev dd t fel <98> 0 ns av ref0 ev dd t fea <99> 0 t fel ns ev dd rv dd t ferv <100> 0 ns note see 33.5 regulator characteristics . remarks 1. the reset pin has an analog noise elimination function. 2. when apply rv dd , set rv dd level so that it meet s the specification of v dd positive slew rate (rv ddpsr ) in 33. 8. 10 rtc back-up mode characteristics . v dd ev dd rv dd v i v i v i v i av ref0 reset (input) <93> <95> <97> <96> <94> <98> <99> <100>
v850es/jg3-l chapter 33 el ectrical specifications ( pd70f3792, 70f3793) r01uh0165ej0700 rev.7.00 page 1020 of 1113 sep 22, 2011 33.8 peripheral function characteristics 33.8.1 interrupt timing (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.0 to 3.6 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit nmi high-level width t wnih 500 ns nmi low-level width t wnil 500 ns n = 0 to 7 (analog noise elimination) 500 ns intpn note high-level width t with n = 3 (digital noise elimination) 3t smp + 20 ns n = 0 to 7 (analog noise elimination) 500 ns intpn note low-level width t witl n = 3 (digital noise elimination) 3t smp + 20 ns note the characteristics of intpn is the same as the drst pin (p05/intp2/drst). remarks 1. t smp : noise elimination sampling clock cycle 2. the nmi and intpn pins have the analog no ise elimination function (n = 0 to 7). 33.8.2 key return timing (t a = ? 40 to +85 c, v dd = ev dd = av ref 0 = av ref1 = 2.0 to 3.6 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit krn high-level width t wkrh 500 ns krn low-level width t wkrl 500 ns remarks 1. n = 0 to 7 2. the krn pin has an analog noise elimination function. 33.8.3 timer timing (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.0 to 3.6 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit ti high-level width t tih 2t + 20 ns ti low-level width t til tip00, tip01, tip10, tip11, tip20, tip21, tip30, tip31, tip40, tip41, tip50, tip51, tiq00 to tiq03 2t + 20 ns remark t = 1/f xx
v850es/jg3-l chapter 33 el ectrical specifications ( pd70f3792, 70f3793) r01uh0165ej0700 rev.7.00 page 1021 of 1113 sep 22, 2011 33.8.4 uart timing (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit transmit rate v dd = 2.0 to 3.6 v 625 kbps v dd = 2.0 to 3.6 v 2.5 mhz v dd = 2.2 to 3.6 v 5 mhz asck0 frequency v dd = 2.7 to 3.6 v 10 mhz 33.8.5 csib timing (1) master mode (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit 2.7 v v dd 3.6 v 125 ns sckbn cycle time t kcy1 <101> 2.0 v v dd < 2.7 v 800 ns 2.7 v v dd 3.6 v t kcy1 /2 ? 8 ns sckbn high-level width t kh1 <102> 2.0 v v dd < 2.7 v t kcy1 /2 ? 80 ns 2.7 v v dd 3.6 v t kcy1 /2 ? 8 ns sckbn low-level width t kl1 <103> 2.0 v v dd < 2.7 v t kcy1 /2 ? 80 ns 2.7 v v dd 3.6 v 27 ns sibn setup time (to sckbn ) t sik1 <104> 2.0 v v dd < 2.7 v 100 ns 2.7 v v dd 3.6 v 27 ns sibn hold time (from sckbn ) t ksi1 <105> 2.0 v v dd < 2.7 v 100 ns 2.7 v v dd 3.6 v 27 ns delay time from sckbn to sobn output t kso1 <106> 2.0 v v dd < 2.7 v 95 ns remark n = 0 to 4
v850es/jg3-l chapter 33 el ectrical specifications ( pd70f3792, 70f3793) r01uh0165ej0700 rev.7.00 page 1022 of 1113 sep 22, 2011 (2) slave mode (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit 2.7 v v dd 3.6 v 125 ns sckbn cycle time t kcy2 <101> 2.0 v v dd < 2.7 v 800 ns sckbn high-level width t kh2 <102> 2.0 v v dd 3.6 v 54.5 ns sckbn low-level width t kl2 <103> 2.0 v v dd 3.6 v 54.5 ns 2.7 v v dd 3.6 v 27 ns sibn setup time (to sckbn ) t sik2 <104> 2.0 v v dd < 2.7 v 100 ns 2.7 v v dd 3.6 v 27 ns sibn hold time (from sckbn ) t ksi2 <105> 2.0 v v dd < 2.7 v 100 ns 2.7 v v dd 3.6 v 27 ns delay time from sckbn to sobn output t kso2 <106> 2.0 v v dd < 2.7 v 95 ns remark n = 0 to 4 sobn (output) input data output data sibn (input) sckbn (i/o) <101> <102> <103> <104> <105> <106> remark n = 0 to 4
v850es/jg3-l chapter 33 el ectrical specifications ( pd70f3792, 70f3793) r01uh0165ej0700 rev.7.00 page 1023 of 1113 sep 22, 2011 33.8.6 i 2 c bus mode (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.0 to 3.6 v, v ss = ev ss = av ss = 0 v) normal mode high-speed mode parameter symbol min. max. min. max. unit scl0n clock frequency f clk 0 100 0 400 khz bus free time (between start and stop conditions) t buf <107> 4.7 ? 1.3 ? s hold time note 1 t hd:sta <108> 4.0 ? 0.6 ? s scl0n clock low-level width t low <109> 4.7 ? 1.3 ? s scl0n clock high-level width t high <110> 4.0 ? 0.6 ? s setup time for start/restart conditions t su:sta <111> 4.7 ? 0.6 ? s cbus compatible master 5.0 ? ? ? s data hold time i 2 c mode t hd:dat <112> 0 note 2 ? 0 note 2 0.9 note 3 s data setup time t su:dat <113> 250 ? 100 note 4 ? ns sda0n and scl0n signal rise time t r <114> ? 1000 20 + 0.1cb note 5 300 ns sda0n and scl0n signal fall time t f <115> ? 300 20 + 0.1cb note 5 300 ns stop condition setup time t su:sto <116> 4.0 ? 0.6 ? s pulse width of spike suppressed by input filter t sp <117> ? ? 0 50 ns capacitance load of each bus line cb ? 400 ? 400 pf notes 1. at the start condition, the first clock pulse is generated after the hold time. 2. the system requires a minimum of 300 ns hold time internally for the sda0n signal (at v ihmin. of scl0n signal) in order to occupy the undefined area at the falling edge of scl0n. 3. if the system does not extend the scl0n signal low hold time (t low ), only the maximum data hold time (t hd : dat ) needs to be satisfied. 4. the high-speed mode i 2 c bus can be used in the normal-mode i 2 c bus system. in this case, set the high-speed mode i 2 c bus so that it meets the following conditions. ? if the system does not extend the scl0n signal?s low state hold time: t su : dat 250 ns ? if the system extends the scl0n signal?s low state hold time: transmit the following data bit to the sda0n line prior to the scl0n line release (t rmax. + t su:dat = 1,000 + 250 = 1,250 ns: normal mode i 2 c bus specification). 5. cb: total capacitance of one bus line (unit: pf) remark n = 0 to 2
v850es/jg3-l chapter 33 el ectrical specifications ( pd70f3792, 70f3793) r01uh0165ej0700 rev.7.00 page 1024 of 1113 sep 22, 2011 i 2 c bus timing stop condition start condition restart condition stop condition scl0n (i/o) sda0n (i/o) <109> <115> <115> <114> <114> <112> <113> <111> <108> <107> <108> <117> <116> <110> remark n = 0 to 2 33.8.7 a/d converter (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , 2.7 v av ref0 = av ref1 3.6 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit resolution 10 bit overall error note 2.7 v av ref0 3.6 v 0.6 %fsr 3.0 v av ref0 3.6 v 2.6 24 s a/d conversion time t conv 2.7 v av ref0 3.0 v 3.9 24 s zero scale error 0.5 %fsr full scale error 0.5 %fsr non-linearity error 4.0 lsb differential linearity error 4.0 lsb analog input voltage v ian av ss av ref0 v reference voltage av ref0 2.7 3.6 v normal conversion mode 3 6.5 ma high-speed conversion mode 4 10 ma av ref0 current ai ref0 when a/d converter unused 5 a note excluding quantization error ( 0.05 %fsr). caution do not set (read/write) alternate-function ports during a/d conversion; otherwise the conversion resolution may be degraded. remark lsb: least significant bit fsr: full scale range
v850es/jg3-l chapter 33 el ectrical specifications ( pd70f3792, 70f3793) r01uh0165ej0700 rev.7.00 page 1025 of 1113 sep 22, 2011 33.8.8 d/a converter (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 8 bit overall error r = 2 m 1.2 %fsr settling time c = 20 pf 3 s output resistor r o output data 55h 6.42 k reference voltage av ref1 2.7 3.6 v d/a conversion operating 1 2.5 ma av ref1 current note ai ref1 d/a conversion stopped 5 a note value of 1 channel of d/a converter remark r is the output pin load resistance and c is the output pin load capacitance. 33.8.9 lvi circuit characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.0 to 3.6 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit v lvi0 2.7 2.8 2.9 v v lvi1 2.2 2.3 2.4 v detection voltage v lvi2 2.0 2.1 2.2 v response time note t ld at rising edge: after v dd reaches v lvi0 /v lvi1 /v lvi2 (max.) at falling edge: after v dd has dropped to v lvi0 /v lvi1 /v lvi2 (min.) 0.2 2.0 ms minimum pulse width t lw v dd = v lvi0 /v lvi1 (min.) 0.2 ms reference voltage stabilization wait time t lwait after v dd reaches v lvi0 /v lvi1 /v lvi2 (max.) 0.1 0.2 ms note time required to detect the detection volta ge and output an interrupt or reset signal. supply voltage (v dd ) time detection voltage (min.) operating voltage (min.) detection voltage (max.) t lwait t lw t ld t ld lvion bit = 0 1
v850es/jg3-l chapter 33 el ectrical specifications ( pd70f3792, 70f3793) r01uh0165ej0700 rev.7.00 page 1026 of 1113 sep 22, 2011 33.8.10 rtc back-up mode characteristics (1) v dd power-down timing (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.0 v to 3.6 v, rv dd = 1.8 v to 3.6 v, v ss = ev ss = av ss = 0v, c l = 50 pf) parameter symbol conditions min. typ. max. unit v ddnsr1 when using rtc backup mode, and setting the lvi detection level to 2.80 0.10 v 0.2 v/ms v dd negative slew rate v ddnsr2 when using rtc backup mode, and setting the lvi detection level to 2.30 0.10 v 0.07 v/ms (2) rv dd power-up timing (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.0 v to 3.6 v, rv dd = 1.8 v to 3.6 v, v ss = ev ss = av ss = 0v, c l = 50 pf) parameter symbol conditions min. typ. max. unit rv dd positive slew rate rv ddpsr 3.0 v/s (3) regulator output voltage for rtc backup area (vch) (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.0 v to 3.6 v, rv dd = 1.8 v to 3.6 v, v ss = ev ss = av ss = 0v, c l = 50 pf) parameter symbol conditions min. typ. max. unit regulator output voltage for rtc backup area (vch) vch 0.8 1.8 v (4) vch setup time (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.0 v to 3.6 v, rv dd = 2.0 v to 3.6 v, v ss = ev ss = av ss = 0v, c l = 50 pf) parameter symbol conditions min. typ. max. unit vch setup time t spor the time from when rv dd reaches the maximum amplitude (v dd = 2.0 to 3.6 v) until vch is stable 4.5 ms
v850es/jg3-l chapter 33 el ectrical specifications ( pd70f3792, 70f3793) r01uh0165ej0700 rev.7.00 page 1027 of 1113 sep 22, 2011 33.9 flash memory programming characteristics (1) basic characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.7 to 3.6 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit operating frequency f cpu 2.5 20 mhz supply voltage v dd 2.5 mhz f xx 20 mhz 2.7 3.6 v used for updating programs when using flash memory programmer and renesas electronics self programming library retained for 15 years 1,000 times number of rewrites c wrt used for updating data when using renesas electronics eeprom emulation library (usable rom size: 12 kb of 3 consecutive blocks) retained for 5 years 10,000 times programming temperature t prg ? 40 +85 c (2) serial write operation characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.7 to 3.6 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit flmd0, flmd1 setup time t mdset 2 3000 ms flmd0 count start time from reset t rfcf f x = 2.5 to 10 mhz 800 s flmd0 counter high-level width/ low-level width t ch /t cl 10 100 s flmd0 counter rise time/fall time t r /t f 1 s flash write mode setup timing v dd flmd1 0 v v dd reset (input) 0 v v dd flmd0 0 v t rfcf t cl t f t r t ch t mdset
v850es/jg3-l chapter 33 el ectrical specifications ( pd70f3792, 70f3793) r01uh0165ej0700 rev.7.00 page 1028 of 1113 sep 22, 2011 (3) programming characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.7 to 3.6 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit chip erase time f xx = 20 mhz (when the chip erase command is executed) 105 ms write time per 256 bytes f xx = 20 mhz 2.0 ms block internal verify time f xx = 20 mhz 10 ms block blank check time f xx = 20 mhz 0.5 ms flash memory information setting time f xx = 20 mhz 30 ms remark block size = 4 kb
v850es/jg3-l chapter 34 el ectrical specifications ( pd70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 1029 of 1113 sep 22, 2011 chapter 34 electrical specifications ( pd70f3841, 70f3842) 34.1 absolute maximum ratings absolute maximum ratings (t a = 25 c) (1/2) parameter symbol conditions ratings unit v dd v dd = ev dd = av ref0 = av ref1 ? 0.5 to +4.6 v ev dd v dd = ev dd = av ref0 = av ref1 ? 0.5 to +4.6 v rv dd v dd = ev dd = av ref0 = av ref1 ? 0.5 to +4.6 v av ref0 v dd = ev dd = av ref0 = av ref1 ? 0.5 to +4.6 v av ref1 v dd = ev dd = av ref0 = av ref1 ? 0.5 to +4.6 v v ss v ss = ev ss = av ss ? 0.5 to +0.5 v av ss v ss = ev ss = av ss ? 0.5 to +0.5 v supply voltage ev ss v ss = ev ss = av ss ? 0.5 to +0.5 v v i1 p97 to p915, pdh0 to pdh4, pcm0 to pcm3, pct0, pct1, pct4, pct6, pdl0 to pdl15, reset, flmd0 ? 0.5 to ev dd + 0.5 note 1 v v i2 p10, p11 ? 0.5 to av ref1 + 0.5 note 1 v x1 ? 0.5 to v dd + 0.5 note 1 v v i3 x2 ? 0.5 to v ro note 2 + 0.5 note 1 v i4 p02 to p06, p30 to p39, p40 to p42, p50 to p55, p90 to p96 ? 0.5 to +6.0 v input voltage v i5 xt1, xt2 ? 0.5 to v ro note 2 + 0.5 v analog input voltage v ian p70 to p711 ? 0.5 to av ref0 + 0.5 note 1 v notes 1. be sure not to exceed the absolute maximum ratings (max. value) of each supply voltage. 2. on-chip regulator output voltage cautions 1. do not directly connect the output (or i/o) pins of ic products to each other, or to v dd , v cc , and gnd. open-drain pins or open-collector pins, however, can be directly connected to each other. direct connection of the output pins between an ic product and an external circuit is possible, if the output pins can be set to th e high-impedance state a nd the output timing of the external circuit is designed to avoid output conflict. 2. product quality may suffer if the absolute maximum rati ng is exceeded even momentarily for any parameter. that is, the absolute m aximum ratings are rate d values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum rati ngs are not exceeded. the ratings and conditions indicated fo r dc characteristics, ac characteristics, and operating conditions represent the quality assurance range duri ng normal operation. remark unless specified otherwise, the ratings of alternate-fu nction pins are the same as those of port pins.
v850es/jg3-l chapter 34 el ectrical specifications ( pd70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 1030 of 1113 sep 22, 2011 absolute maximum ratings (t a = 25 c) (2/2) parameter symbol conditions ratings unit per pin 4 ma p02 to p06, p30 to p39, p40 to p42, p50 to p55, p90 to p915, pdh4 total of all pins 50 ma per pin 4 ma pcm0 to pcm3, pct0, pct1, pct4, pct6, pdh0 to pdh3, pdl0 to pdl15 total of all pins 50 ma per pin 4 ma p10, p11 total of all pins 8 ma per pin 4 ma output current, low i ol p70 to p711 total of all pins 20 ma per pin ? 4 ma p02 to p06, p30 to p39, p40 to p42, p50 to p55, p90 to p915, pdh4 total of all pins ? 50 ma per pin ? 4 ma pcm0 to pcm3, pct0, pct1, pct4, pct6, pdh0 to pdh3, pdl0 to pdl15 total of all pins ? 50 ma per pin ? 4 ma p10, p11 total of all pins ? 8 ma per pin ? 4 ma output current, high i oh p70 to p711 total of all pins ? 20 ma normal operation mode ? 40 to +85 c operating ambient temperature t a flash memory programming mode ? 40 to +85 c storage temperature t stg ? 40 to +125 c cautions 1. do not directly connect the output (or i/o) pins of ic products to each other, or to v dd , v cc , and gnd. open-drain pins or open-collector pins, however, can be directly connected to each other. direct connection of the output pins between an ic product and an external circuit is possible, if the output pins can be set to th e high-impedance state a nd the output timing of the external circuit is designed to avoid output conflict. 2. product quality may suffer if the absolute maximum rati ng is exceeded even momentarily for any parameter. that is, the absolute m aximum ratings are rate d values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum rati ngs are not exceeded. the ratings and conditions indicated fo r dc characteristics, ac characteristics, and operating conditions represent the quality assurance range duri ng normal operation. remark unless specified otherwise, the ratings of alternate-fu nction pins are the same as those of port pins.
v850es/jg3-l chapter 34 el ectrical specifications ( pd70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 1031 of 1113 sep 22, 2011 34.2 capacitance capacitance (t a = 25 c, v dd = ev dd = av ref0 = av ref1 = rv dd = v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit i/o capacitance c io f x = 1 mhz unmeasured pins returned to 0 v 10 pf 34.3 operating conditions (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v) supply voltage operating clock conditions v dd ev dd rv dd note1 av ref0 , av ref1 unit f xx = 10 to 20 mhz (main clock) regc = 4.7 f, a/d converter operating, d/a converter operating pll mode v f xx = 2.5 to 10 mhz (main clock) regc = 4.7 f, a/d converter operating, d/a converter operating clock-through mode 2.7 to 3.6 2.7 to 3.6 2.7 to 3.6 2.7 to 3.6 v f xx = 2.5 to 5 mhz (main clock) regc = 4.7 f, a/d converter stopped, d/a converter stopped clock-through mode 2.2 to 3.6 2.2 to 3.6 2.2 to 3.6 2.2 to 3.6 v f xx = 1.25 to 2.5 mhz note2 (main clock) regc = 4.7 f, a/d converter stopped, d/a converter stopped clock-through mode 2.0 to 3.6 2.0 to 3.6 2.0 to 3.6 2.0 to 3.6 v f xt = 32.768 khz (subclock) regc = 4.7 f, a/d converter stopped, d/a converter stopped 2.0 to 3.6 2.0 to 3.6 2.0 to 3.6 2.0 to 3.6 v f xt = 32.768 khz (subclock) regc = 4.7 f, a/d converter stopped, d/a converter stopped, rtc backup mode 0 to 3.6 0 to 3.6 1.8 to 3.6 0 to 3.6 v notes1. rv dd can be used as a separate potential without any need to set it to the same potential as other power supply voltages. unless otherwise specified, use rv dd in this way under the above operating condition. 2. an operating clock of 1.25 mhz can only be specifi ed when the ckthsel register is set to 1 (which specifies the clock-through frequency divided by 2). caution the operating conditions will not be satisfied if rv dd falls below 1.8 v. in this case, therefore, be sure to initialize the rtc (by clearing the rc1cc0.rc1pwr bit (0)) once rv dd is restored (to 1.8 v or higher) after having fallen below 1.8 v during operation. note that the rtc will be initialized if power is applied with rv dd = 0.
v850es/jg3-l chapter 34 el ectrical specifications ( pd70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 1032 of 1113 sep 22, 2011 34.4 oscillator characteristics 34.4.1 main clock osc illator characteristics (1) main clock oscilla tor characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v) resonator circuit example paramete r conditions min. typ. max. unit v dd = 2.0 to 3.6 v 2.5 2.5 mhz v dd = 2.2 to 3.6 v 2.5 5 mhz clock through mode v dd = 2.7 to 3.6 v 2.5 10 mhz oscillation frequency (f x ) note 1 v dd = 2.7 to 3.6 v in pll mode 2.5 5 mhz v dd = 2.0 to 3.6 v immediately after reset ends note 3 note 4 s v dd = 2.0 to 3.6 v in clock through mode 400 note 5 note 6 s after stop mode is released v dd = 2.7 to 3.6 v in pll mode 400 note 7 note 6 s v dd = 2.0 to 3.6 v in clock through mode 200 note 5 note 6 s ceramic resonator/ crystal resonator x2 x1 oscillation stabilization time note 2 after idle2 mode is released v dd = 2.7 to 3.6 v in pll mode 400 note 7 note 6 s notes 1. the oscillation frequency shown above indicates only os cillator characteristics. use the v850es/jg3-l so that the internal operating condit ions do not exceed the ratings shown in ac characteristics , dc characteristics , and operating conditions . 2. the wait time required from when the resonator starts oscillating until oscillation stabilizes. 3. the oscillation stabilization time after reset release is restricted in accordance with the set value of the option byte. for details, see chapter 29 option byte . 4. the oscillation stabilization time differs depending on the set value of the option byte. for details, see chapter 29 option byte . 5. time required to set up the regulator and flash memory . secure the setup time using the osts register. 6. the value varies depending on the setting of the osts register. 7. time required to set up the regulator, flash memory, and pll. secure the setup time using the osts register. caution 1. when using the main clock oscillator, wire as follows in the ar ea enclosed by th e broken lines in the above figure to avo id an adverse effect from wiring capacitance. ? keep the wiring lengt h as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line th rough which a high fluctuating current flows. ? always make the ground point of the o scillator capacitor the same potential as v ss . ? do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. caution 2. when the main clock is stopped and th e device is operating on the subclock, wait until the oscillation stabilization time has been secured by the program before switching back to the main clock.
v850es/jg3-l chapter 34 el ectrical specifications ( pd70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 1033 of 1113 sep 22, 2011 (a) kyocera kinseki corporation: crystal resonator (t a = ? 10 to +70 c) note1 recommended circuit constant oscillation voltage range oscillation stabilizatio n time note2 type circuit example part number oscillation frequency f x (mhz) load capacitan ce (pf) c1 (pf) c2 (pf) rd ( ) min. (v) max. (v) max. (ms) cx49gfnb, cx1255gb, cx8045gb 4.000 8 10 10 0 2.0 3.6 2.26 cx49gfnb, cx1255gb, cx8045gb 5.000 8 10 10 0 2.0 3.6 1.61 cx49gfnb, cx1255gb, cx8045gb 6.000 8 10 10 0 2.0 3.6 1.02 cx49gfnb, cx1255gb, cx8045gb 8.000 8 10 10 0 2.0 3.6 0.87 surface mounting cx49gfnb, cx1255gb, cx8045gb 10.000 8 10 10 0 2.0 3.6 0.57 hc49sfnb 4.000 8 10 10 0 2.0 3.6 2.26 hc49sfnb 5.000 8 10 10 0 2.0 3.6 1.61 hc49sfnb 6.000 8 10 10 0 2.0 3.6 1.02 hc49sfnb 8.000 8 10 10 0 2.0 3.6 0.87 lead x2 x1 c1 c2 rd hc49sfnb 10.000 8 10 10 0 2.0 3.6 0.57 notes1. contact the resonator manufacturer regarding use at a temperature outside this range. 2. the oscillation stabilization time is slightly longer when using the cx8045gb. contact the resonator manufacturer for details. caution this oscillator constant is a reference value based on evalua tion under a specific environment by the resonator manufacturer. if optimization of oscillator characteristics is necessary in the actual application, apply to the resonator manufacturer for evaluation on the implementation circuit. the oscillation voltage and osc illation frequency indicate only osc illator characteris tics. use the v850es/jg3-l so that the internal operating condit ions are within the specifications of the ac characteristics, dc characterist ics, and operating conditions.
v850es/jg3-l chapter 34 el ectrical specifications ( pd70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 1034 of 1113 sep 22, 2011 (b) murata mfg. co. lt d.: ceramic resonator (t a = ? 20 to +80 c) note recommended circuit constant oscillation voltage range oscillation stabilization time type circuit example part number oscillation frequency f x (mhz) c1 (pf) c2 (pf) rd ( ) min. (v) max. (v) max. (ms) cstcc2m50g56-r0 2.500 (47) (47) 2200 2.0 3.6 0.02 cstcr4m00g55-r0 4.000 (39) (39) 680 2.0 3.6 0.02 cstcr5m00g55-r0 5.000 (39) (39) 680 2.0 3.6 0.02 cstcr6m00g55-r0 6.000 (39) (39) 470 2.0 3.6 0.02 cstce8m00g55-r0 8.000 (33) (33) 0 2.0 3.6 0.03 surface mounting cstce10m0g55-r0 10.000 (33) (33) 0 2.0 3.6 0.03 cstls4m00g56-b0 4.000 (47) (47) 680 2.0 3.6 0.02 cstls5m00g56-b0 5.000 (47) (47) 680 2.0 3.6 0.02 cstls6m00g56-b0 6.000 (47) (47) 470 2.0 3.6 0.02 cstls8m00g56-b0 8.000 (47) (47) 0 2.0 3.6 0.03 lead x2 x1 c1 c2 rd cstls10m0g56-b0 10.000 (47) (47) 0 2.1 3.6 0.03 note contact the resonator ma nufacturer regarding use at a temperature outside this range. caution this oscillator constant is a reference value based on evaluati on under a specific environment by the resonator manufacturer. if optimization of oscillator characteristics is necessary in the actual app lication, apply to the resonator manufacturer for evaluation on the implementation circuit. the oscillation voltage and osc illation frequency indicate only osc illator characteris tics. use the v850es/jg3-l so that the intern al operating conditions are withi n the specifications of the ac characteristics, dc characterist ics, and operating conditions. remark figures in parentheses in columns c1 and c2 indi cate the capacitance incorporated in the resonator. (2) external clock (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.7 to 3.6 v, v ss = ev ss = av ss = 0 v) resonator circuit example paramete r conditions min. typ. max. unit clock through mode 2.5 5 mhz input frequency (f x ) note pll mode 2.5 5 mhz v ih x1 2.3 v dd v external clock open external clock cmos inverter x2 x1 v il x1 v ss 0.4 v note keep the duty factor of the input waveform to within 45% to 55%. cautions 1. be sure to disconnect the internal feedback resistor after reset (set pcc.mfrc = 1). 2. leave the x2 pin open. 3. make sure that the cmos inverter is as close to the x1 pin as possible.
v850es/jg3-l chapter 34 el ectrical specifications ( pd70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 1035 of 1113 sep 22, 2011 34.4.2 subclock oscilla tor characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.0 to 3.6 v, v ss = ev ss = av ss = 0 v) resonator circuit example parameter conditions min. typ. max. unit oscillation frequency (f xt ) note 1 32 32.768 35 khz crystal resonator xt2 xt1 oscillation stabilization time note 2 10 s notes 1. the oscillation frequency shown above indicates only os cillator characteristics. use the v850es/jg3-l so that the internal operation condit ions do not exceed the ratings shown in ac characteristics , dc characteristics , and operating conditions. 2. time required from when rv dd reaches the oscillation voltage range (2.0 v (min.)) to when the crystal resonator stabilizes. cautions 1. when using the subclock oscillator, wire as follows in the area enclosed by th e broken lines in the above figures to avo id an adverse effect fr om wiring capacitance. ? keep the wiring le ngth as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the oscillator capacitor the same potential as v ss . ? do not ground the capacitor to a groun d pattern through which a high current flows. ? do not fetch signals from the oscillator. 2. the subclock oscillator is designed as a low-amplitude circuit for reducing power consumption, and is mo re prone to malfunction due to noi se than the main clock oscillator. particular care is theref ore required with the wiring met hod when the subclock is used. 3. for the resonator selection and oscillator constant, custom ers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
v850es/jg3-l chapter 34 el ectrical specifications ( pd70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 1036 of 1113 sep 22, 2011 (a) seiko instruments inc.: crystal resonator (t a = ? 40 to +85 c) oscillation frequency: f xt = 32.768 khz recommended circuit constant oscillation voltage range type circuit example part number load capacitance of crystal resonator (pf) c1 (pf) c2 (pf) rd ( ) min. (v) max. (v) lead xt2 xt1 c1 c2 rd vt-200-f 12.5 22 22 220 1.8 3.6 caution this oscillator constant is a reference value based on evalua tion under a specific environment by the resonator manufacturer. if optimization of oscillator characteristics is necessary in the actual application, apply to the resonator manufacturer for evaluation on the implementation circuit. the oscillation voltage and osc illation frequency indicate only osc illator characteris tics. use the v850es/jg3-l so that the internal operating condit ions are within the specifications of the ac characteristics, dc characterist ics, and operating conditions. (b) citizen miyota co., ltd.: crystal resonator (t a = ? 40 to +85 c) oscillation frequency: f xt = 32.768 khz recommended circuit constant oscillation voltage range type circuit example part number load capacitance of crystal resonator (pf) c1 (pf) c2 (pf) rd ( ) min. (v) max. (v) surface mounting xt2 xt1 c1 c2 rd cmr200t 9 15 18 100 1.8 3.6 caution this oscillator constant is a reference value based on evalua tion under a specific environment by the resonator manufacturer. if optimization of oscillator characteristics is necessary in the actual application, apply to the resonator manufacturer for evaluation on the implementation circuit. the oscillation voltage and osc illation frequency indicate only osc illator characteris tics. use the v850es/jg3-l so that the internal operating condit ions are within the specifications of the ac characteristics, dc characterist ics, and operating conditions.
v850es/jg3-l chapter 34 el ectrical specifications ( pd70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 1037 of 1113 sep 22, 2011 34.4.3 pll characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit input frequency f x 2.5 5 mhz output frequency f xx 10 20 mhz lock time t pll after v dd reaches 2.7 v (min.) 400 s 34.4.4 internal oscillat or characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit output frequency f r 100 220 400 khz
v850es/jg3-l chapter 34 el ectrical specifications ( pd70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 1038 of 1113 sep 22, 2011 34.5 regulator characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit f xx = 20 mhz (max.) 2.7 3.6 v f xx = 5 mhz (max.) 2.2 3.6 v f xx = 2.5 mhz (max.) 2.0 3.6 v input voltage v dd data retained (stop mode) 1.9 3.6 v output voltage v ro v dd = 2.7 to 3.6 v 2.5 v after v dd reaches 2.7 v (min.), stabilization capacitance c = 4.7 f (recommended value) connected to regc pin 1 ms after v dd reaches 2.2 v (min.), stabilization capacitance c = 4.7 f (recommended value) connected to regc pin 3.5 ms regulator output stabilization time t reg after v dd reaches 2.0 v (min.), stabilization capacitance c = 4.7 f (recommended value) connected to regc pin 4.5 ms external capacitance regc permissible error of external capacitance to be connected to regc pin 3.76 4.70 5.64 f v dd v ro t reg reset
v850es/jg3-l chapter 34 el ectrical specifications ( pd70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 1039 of 1113 sep 22, 2011 34.6 dc characteristics 34.6.1 pin characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.0 to 3.6 v, v ss = ev ss = av ss = 0 v) (1/2) parameter symbol conditions min. typ. max. unit v ih1 reset, flmd0, p97 to p915 0.8ev dd ev dd v v ih2 p02 to p06, p30 to p37, p42, p50 to p55, p92 to p96 0.8ev dd 5.5 v v ih3 p38, p39, p40, p41, p90, p91 0.7ev dd 5.5 v v ih4 pcm0 to pcm3, pct0, pct1, pct4, pct6, pdh0 to pdh4, pdl0 to pdl15 0.7ev dd ev dd v v ih5 p70 to p711 0.7av ref0 av ref0 v input voltage, high v ih6 p10, p11 0.7av ref1 av ref1 v v il1 reset, flmd0, p97 to p915 ev ss 0.2ev dd v v il2 p02 to p06, p30 to p37, p42, p50 to p55, p92 to p96 ev ss 0.2ev dd v v il3 p38, p39, p40, p41, p90, p91 ev ss 0.3ev dd v v il4 pcm0 to pcm3, pct0, pct1, pct4, pct6, pdh0 to pdh4, pdl0 to pdl15 ev ss 0.3ev dd v v il5 p70 to p711 av ss 0.3av ref0 v input voltage, low v il6 p10, p11 av ss 0.3av ref1 v input leakage current, high i lih v i = v dd = ev dd = av ref0 = av ref1 5 a input leakage current, low i lil v i = 0 v ? 5 a output leakage current, high i loh v o = v dd = ev dd = av ref0 = av ref1 5 a output leakage current, low i lol v o = 0 v ? 5 a remark unless specified otherwise, the characteristics of alte rnate-function pins are t he same as those of port pins.
v850es/jg3-l chapter 34 el ectrical specifications ( pd70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 1040 of 1113 sep 22, 2011 (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.0 to 3.6 v, v ss = ev ss = av ss = 0 v) (2/2) parameter symbol conditions min. typ. max. unit per pin i oh = ? 1.0 ma total of all pins ? 20 ma ev dd ? 1.0 ev dd v v oh1 p02 to p06, p30 to p39, p40 to p42, p50 to p55, p90 to p915, pdh4 per pin i oh = ? 100 a total of all pins ? 4.1 ma ev dd ? 0.5 ev dd v per pin i oh = ? 1.0 ma total of all pins ? 20 ma ev dd ? 1.0 ev dd v v oh2 pcm0 to pcm3, pct0, pct1, pct4, pct6, pdh0 to pdh3, pdl0 to pdl15 per pin i oh = ? 100 a total of all pins ? 2.8 ma ev dd ? 0.5 ev dd v per pin i oh = ? 0.4 ma total of all pins ? 4.8 ma av ref0 ? 1.0 av ref0 v v oh3 p70 to p711 per pin i oh = ? 100 a total of all pins ? 1.2 ma av ref0 ? 0.5 av ref0 v per pin i oh = ? 0.4 ma total of all pins ? 0.8 ma av ref1 ? 1.0 av ref1 v output voltage, high v oh4 p10, p11 per pin i oh = ? 100 a total of all pins ? 0.2 ma av ref1 ? 0.5 av ref1 v v ol1 p02 to p06, p30 to p37, p42, p50 to p55, p92 to p915, pdh4 per pin i ol = 1.0 ma 0 0.4 v v ol2 p38, p39, p40, p41, p90, p91 per pin i ol = 3.0 ma total of all pins 20 ma 0 0.4 v v ol3 pcm0 to pcm3, pct0, pct1, pct4, pct6, pdh0 to pdh3, pdl0 to pdl15 per pin i ol = 1.0 ma total of all pins 20 ma 0 0.4 v output voltage, low v ol4 p10, p11, p70 to p711 per pin i ol = 0.4 ma total of all pins 5.6 ma 0 0.4 v software pull-down resistor note r 1 p05 v i = v dd 10 20 100 k note drst pin only (controlled by ocdm register) remarks 1. unless specified otherwise, the charac teristics of alternate-function pins are the same as those of port pins. 2. when the i oh and i ol conditions are not satisfied for a pin but t he total value of all pins is satisfied, only that pin does not satisf y the dc characteristics.
v850es/jg3-l chapter 34 el ectrical specifications ( pd70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 1041 of 1113 sep 22, 2011 34.6.2 supply current characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. note 1 max. note 2 unit f xx = 20 mhz (f x = 5 mhz) note 3 15 27 ma i dd1 normal operation f xx = 10 mhz (f x = 10 mhz), pll off note 3 9 14 ma i dd2 halt mode f xx = 20 mhz (f x = 5 mhz) note 3 8 16 ma i dd3 idle1 mode f xx = 5 mhz (f x = 5 mhz), pll off note 3 0.9 1.5 ma i dd4 idle2 mode f xx = 5 mhz (f x = 5 mhz), pll off note 3 0.28 0.5 ma i dd5 subclock operation mode f xt = 32.768 khz, main clock stopped, internal oscillator stopped, pll off note 3 regovl0 = 02h (low-voltage subclock operation mode), csibn stopped note 5 , uarta0 stopped note 5 18 a i dd6 sub-idle mode f xt = 32.768 khz, main clock stopped, internal oscillator stopped, pll off note 3 regovl0 = 02h (low-voltage sub-idle mode), csibn stopped note 5 , uarta0 stopped note 5 3.5 50 a subclock stopped, internal oscillator stopped, regovl0 = 01h (low-voltage stop mode), t a = 25 c 1.5 3.0 a subclock stopped, internal oscillator stopped, regovl0 = 01h (low-voltage stop mode), t a = 85 c 45 a i dd7 stop mode subclock operating, internal oscillator stopped, regovl0 = 01h (low-voltage stop mode) note 3 , csibn stopped note 5 , uarta0 stopped note 5 3.5 50 a supply current note 4 i dd8 self programming mode f xx = 20 mhz (f x = 5 mhz) 14 24 ma lvi current i lvi 1.2 3 a wdt, internal oscillation current i wdt 5 a rtc back-up mode note 4 i rtc rtc backup mode subclock operating t a = 70 c rv dd voltage, v dd = 0 v 1 a notes 1. typ. current is a value at v dd = ev dd = rv dd = 3.3 v, t a = 25 c. the typ. value is not a value guaranteed for each device. 2. max. current is a value at which the characterist ic in question is at the worst-case value at v dd = ev dd = rv dd = 3.6 v, t a = ? 40 to +85 c. 3. typ. value indicates the current value when "rtc " or "watch timer + tmm (count by watch timer interrupt)" operate as peripheral functions.max. val ue indicates the current value when all the functions operable in a range in which the pin status is not changed operate as peripheral functions. however, i lvi and i wdt are excluded. 4. total of v dd , ev dd and rv dd currents. currents i lvi and i wdt flowing through the output buffers, a/d converter, d/a converter, and on-chip pull-down resistor are not included. 5. csibn and uarta0 can be operated using sckbn and ascka0 respectively, but the target spec is the current value when csibn and uarta0 are stopped. remark for details about the operating voltage, see 34.3 operating conditions .
v850es/jg3-l chapter 34 el ectrical specifications ( pd70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 1042 of 1113 sep 22, 2011 34.6.3 data retention charact eristics (in stop mode) (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit data retention voltage v dddr stop mode (all functions stopped) 1.9 3.6 v data retention current i dddr subclock stopped, internal oscillator stopped t a = 85 c 45 a supply voltage rise time t rvd 200 s supply voltage fall time t fvd 200 s supply voltage retention time t hvd after stop mode setting 0 ms stop release signal input time t drel after v dd reaches the operating voltage min. (see 34.3 operating conditions ) 0 ms data retention input voltage, high v ihdr v dd = ev dd = v dddr 0.9v dddr v dddr v data retention input voltage, low v ildr v dd = ev dd = v dddr 0 0.1v dddr v caution shifting to stop mode and restoring from stop mode must be performed within the rated operating range. t drel t hvd t fvd t rvd stop release signal input stop mode setting v dddr v ihdr v ihdr v ildr v dd /ev dd reset (input) stop mode release interrupt (nmi, etc.) (released by falling edge) stop mode release interrupt (nmi, etc.) (released by rising edge) operating voltage lower limit
v850es/jg3-l chapter 34 el ectrical specifications ( pd70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 1043 of 1113 sep 22, 2011 34.7 ac characteristics 34.7.1 measurement conditions (1) ac test input measurement points v dd v ss v ih v il v ih v il measurement points (2) ac test output measurement points v oh v ol v oh v ol measurement points (3) load conditions dut (device under measurement) c l = 50 pf caution if the load capacitance exceeds 50 pf due to the circuit configuration, bring the load capacitance of the device to 50 pf or less by inserting a buffer or by some other means.
v850es/jg3-l chapter 34 el ectrical specifications ( pd70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 1044 of 1113 sep 22, 2011 34.7.2 clkout output timing (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.7 to 3.6 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit output cycle t cyk <1> 50 ns 31.25 s high-level width t wkh <2> t cyk /2 ? 10 ns low-level width t wkl <3> t cyk /2 ? 10 ns rise time t kr <4> 10 ns fall time t kf <5> 10 ns clkout (output) <1> <2> <3> <4> <5>
v850es/jg3-l chapter 34 el ectrical specifications ( pd70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 1045 of 1113 sep 22, 2011 34.7.3 bus timing the values for just the access method to be used (syn chronous with or asynchronous to clkout) must be satisfied. it is not necessary to satisfy the values fo r both methods. when using a separate bus, refer to the specification of multiplexed bus mode. (1) in multiplexed bus mode (a) read/write cycle (a synchronous to clkout) (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.7 to 3.6 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit address setup time (to astb ) t sast <6> (0.5 + t asw )t ? 20 ns address hold time (from astb ) t hsta <7> (0.5 + t ahw )t ? 15 ns delay time from rd to address float t frda <8> 0 ns data input setup time from address t said <9> (2 + n + t asw + t ahw )t ? 35 ns data input setup time from rd t srid <10> (1 + n)t ? 25 ns delay time from astb to rd, wrm t dstrdwr <11> (0.5 + t ahw )t ? 15 ns data input hold time (from rd ) t hrdid <12> 0 ns address output time from rd t drda <13> (1 + i)t ? 15 ns delay time from rd, wrm to astb t drdwrst <14> 0.5t ? 15 ns delay time from rd to astb t drdst <15> (1.5 + i + t asw )t ? 15 ns rd, wrm low-level width t wrdwrl <16> (1 + n)t ? 15 ns astb high-level width t wsth <17> (1 + i + t asw )t ? 15 ns data output time from wrm t dwrod <18> 15 ns data output setup time (to wrm ) t sodwr <19> (1 + n)t ? 20 ns data output hold time (from wrm ) t hwrod <20> t ? 15 ns t sawt1 <21> n 1 (1.5 + t asw + t ahw )t ? 35 ns wait setup time (to address) t sawt2 <22> (1.5 + n + t asw + t ahw )t ? 35 ns t hawt1 <23> n 1 (0.5 + n + t asw + t ahw )t ns wait hold time (from address) t hawt2 <24> (1.5 + n + t asw + t ahw )t ns t sstwt1 <25> n 1 (1 + t ahw )t ? 25 ns wait setup time (to astb ) t sstwt2 <26> (1 + n + t ahw )t ? 25 ns t hstwt1 <27> n 1 (n + t ahw )t ns wait hold time (from astb ) t hstwt2 <28> (1 + n + t ahw )t ns address hold time from rd t hrda2 <29> (1 + i)t ? 15 ns address hold time from wrm t hwra2 <30> t ? 15 ns remarks 1. t asw : number of address setup wait clocks (0 or 1) t ahw : number of address hold wait clocks (0 or 1) 2. t = 1/f cpu (f cpu : cpu operating clock frequency) 3. n: number of wait clocks inserted in the bus cycle the sampling timing changes when a programmable wait is inserted. 4. m = 0, 1 5. i: number of idle states inserted after a read cycle (0 or 1) 6. the values in the above specifications are values for when clo cks with a 1:1 duty ratio are input from x1.
v850es/jg3-l chapter 34 el ectrical specifications ( pd70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 1046 of 1113 sep 22, 2011 read cycle (asynchronous to clkout): in mu ltiplexed bus mode clkout (output) a16 to a21 note (output) ad0 to ad15 (i/o) astb (output) rd (output) wait (input) t1 t2 tw t3 data address hi-z <6> <7> <17> <9> <12> <14> <10> <11> <25> <27> <26> <28> <21> <23> <22> <24> <16> <8> <13> <29> <15> note when use a separate bus, a0 to a21. remark wr0 and wr1 are high level.
v850es/jg3-l chapter 34 el ectrical specifications ( pd70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 1047 of 1113 sep 22, 2011 write cycle (asynchronous to clko ut): in multiplexed bus mode clkout (output) ad0 to ad15 (i/o) astb (output) wr0, wr1 (output) wait (input) t1 t2 tw t3 data address <25> <27> <26> <28> <21> <23> <22> <24> <6> <17> <7> <14> <20> <30> <19> <16> <11> <18> a16 to a21 note (output) note when use a separate bus, a0 to a21. remark rd is high level.
v850es/jg3-l chapter 34 el ectrical specifications ( pd70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 1048 of 1113 sep 22, 2011 (b) read/write cycle (synchronous with clkout): in multiplexed bus mode (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.7 to 3.6 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit delay time from clkout to address t dka <31> 0 25 ns delay time from clkout to address float t fka <32> 0 19 ns delay time from clkout to astb t dkst <33> ? 12 7 ns delay time from clkout to rd, wrm t dkrdwr <34> ? 5 14 ns data input setup time (to clkout ) t sidk <35> 15 ns data input hold time (from clkout ) t hkid <36> 5 ns data output delay time from clkout t dkod <37> 19 ns wait setup time (to clkout ) t swtk <38> 20 ns wait hold time (from clkout ) t hkwt <39> 5 ns address hold time from clkout t hka2 <40> 0 25 ns data output hold time from clkout t hkdw <41> 0 ns address hold time from clkout t hkaw <42> 0 ns remarks 1. m = 0, 1 2. the values in the above specifications are values for when cl ocks with a 1:1 duty ratio are input from x1. 3. for details about the clkout output timing, see 34.7.2 clkout output timing . read cycle (synchronous with clkout): in multiplexed bus mode clkout (output) a16 to a21 note (output) ad0 to ad15 (i/o) astb (output) rd (output) wait (input) t1 t2 tw t3 ti t1 data address hi-z <31> <33> <34> <32> <31> <33> <40> <34> <38> <38> <39> <39> <35> <36> note when use a separate bus, a0 to a21. remark wr0 and wr1 are high level.
v850es/jg3-l chapter 34 el ectrical specifications ( pd70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 1049 of 1113 sep 22, 2011 write cycle (synchronous with clko ut): in multiplexed bus mode clkout (output) ad0 to ad15 (i/o) astb (output) wr0, wr1 (output) wait (input) t1 t2 tw t3 data address <31> <33> <34> <34> <39> <39> <38> <38> <33> <41> <42> <37> a16 to a21 note (output) note when use a separate bus, a0 to a21. remark rd is high level.
v850es/jg3-l chapter 34 el ectrical specifications ( pd70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 1050 of 1113 sep 22, 2011 (2) bus hold (a) asynchronous to clkout (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.7 to 3.6 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit hldrq high-level width t whqh <84> t + 10 ns hldak low-level width t whal <85> t ? 15 ns delay time from hldak to bus output t dhac <86> ? 3 ns delay time from hldrq to hldak t dhqha1 <87> (2n + 7.5)t + 26 ns delay time from hldrq to hldak t dhqha2 <88> 0.5t 1.5t + 26 ns remarks 1. t = 1/f cpu (f cpu : cpu operating clock frequency) 2. n: number of wait clocks inserted in the bus cycle the sampling timing changes when a programmable wait is inserted. 3. the values in the above specifications are values for when cl ocks with a 1:1 duty ratio are input from x1. bus hold (asynchronous to clkout) clkout (output) hldrq (input) hldak (output) address bus (output) data bus (i/o) th th th ti ti hi-z astb (output) rd (output), wr0, wr1 (output) hi-z hi-z <84> <88> <85> <86> <87>
v850es/jg3-l chapter 34 el ectrical specifications ( pd70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 1051 of 1113 sep 22, 2011 (b) synchronous with clkout (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.7 to 3.6 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit hldrq setup time (to clkout ) t shqk <89> 20 ns hldrq hold time (from clkout ) t hkhq <90> 5 ns delay time from clkout to bus float t dkf <91> 19 ns delay time from clkout to hldak t dkha <92> 19 ns remarks 1. the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1. 2. for details about the clkout output timing, see 34.7.2 clkout output timing . bus hold (synchronous with clkout) clkout (output) hldrq (input) hldak (output) address bus (output) data bus (i/o) th th th t2 t3 ti ti hi-z astb (output) rd (output), wr0, wr1 (output) hi-z hi-z <89> <89> <92> <92> <90> <91>
v850es/jg3-l chapter 34 el ectrical specifications ( pd70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 1052 of 1113 sep 22, 2011 34.7.4 power on/power off/reset timing (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.0 to 3.6 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit ev dd v dd t rel <93> 0 ns ev dd av ref0 , av ref1 t rea <94> 0 t rel ns v dd reset t rer <95> 500 + t reg note ns reset low-level width t wrsl <96> 500 ns reset v dd t fre <97> 500 ns v dd ev dd t fel <98> 0 ns av ref0 ev dd t fea <99> 0 t fel ns ev dd rv dd t ferv <100> 0 ns note see 34.5 regulator characteristics . remarks 1. the reset pin has an analog noise elimination function. 2. when apply rv dd , set rv dd level so that it meet s the specification of v dd positive slew rate (rv ddpsr ) in 34. 8. 10 rtc back-up mode characteristics . v dd ev dd rv dd v i v i v i v i av ref0 reset (input) <93> <95> <97> <96> <94> <98> <99> <100>
v850es/jg3-l chapter 34 el ectrical specifications ( pd70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 1053 of 1113 sep 22, 2011 34.8 peripheral function characteristics 34.8.1 interrupt timing (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.0 to 3.6 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit nmi high-level width t wnih 500 ns nmi low-level width t wnil 500 ns n = 0 to 7 (analog noise elimination) 500 ns intpn note high-level width t with n = 3 (digital noise elimination) 3t smp + 20 ns n = 0 to 7 (analog noise elimination) 500 ns intpn note low-level width t witl n = 3 (digital noise elimination) 3t smp + 20 ns note the characteristics of intpn is the same as the drst pin (p05/intp2/drst). remarks 1. t smp : noise elimination sampling clock cycle 2. the nmi and intpn pins have the analog no ise elimination function (n = 0 to 7). 34.8.2 key return timing (t a = ? 40 to +85 c, v dd = ev dd = av ref 0 = av ref1 = 2.0 to 3.6 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit krn high-level width t wkrh 500 ns krn low-level width t wkrl 500 ns remarks 1. n = 0 to 7 2. the krn pin has an analog noise elimination function. 34.8.3 timer timing (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.0 to 3.6 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit ti high-level width t tih 2t + 20 ns ti low-level width t til tip00, tip01, tip10, tip11, tip20, tip21, tip30, tip31, tip40, tip41, tip50, tip51, tiq00 to tiq03 2t + 20 ns remark t = 1/f xx
v850es/jg3-l chapter 34 el ectrical specifications ( pd70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 1054 of 1113 sep 22, 2011 34.8.4 uart timing (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit transmit rate v dd = 2.0 to 3.6 v 625 kbps v dd = 2.0 to 3.6 v 2.5 mhz v dd = 2.2 to 3.6 v 5 mhz asck0 frequency v dd = 2.7 to 3.6 v 10 mhz 34.8.5 csib timing (1) master mode (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit 2.7 v v dd 3.6 v 125 ns sckbn cycle time t kcy1 <101> 2.0 v v dd < 2.7 v 800 ns 2.7 v v dd 3.6 v t kcy1 /2 ? 8 ns sckbn high-level width t kh1 <102> 2.0 v v dd < 2.7 v t kcy1 /2 ? 80 ns 2.7 v v dd 3.6 v t kcy1 /2 ? 8 ns sckbn low-level width t kl1 <103> 2.0 v v dd < 2.7 v t kcy1 /2 ? 80 ns 2.7 v v dd 3.6 v 27 ns sibn setup time (to sckbn ) t sik1 <104> 2.0 v v dd < 2.7 v 100 ns 2.7 v v dd 3.6 v 27 ns sibn hold time (from sckbn ) t ksi1 <105> 2.0 v v dd < 2.7 v 100 ns 2.7 v v dd 3.6 v 27 ns delay time from sckbn to sobn output t kso1 <106> 2.0 v v dd < 2.7 v 95 ns remark n = 0 to 4
v850es/jg3-l chapter 34 el ectrical specifications ( pd70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 1055 of 1113 sep 22, 2011 (2) slave mode (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit 2.7 v v dd 3.6 v 125 ns sckbn cycle time t kcy2 <101> 2.0 v v dd < 2.7 v 800 ns sckbn high-level width t kh2 <102> 2.0 v v dd 3.6 v 54.5 ns sckbn low-level width t kl2 <103> 2.0 v v dd 3.6 v 54.5 ns 2.7 v v dd 3.6 v 27 ns sibn setup time (to sckbn ) t sik2 <104> 2.0 v v dd < 2.7 v 100 ns 2.7 v v dd 3.6 v 27 ns sibn hold time (from sckbn ) t ksi2 <105> 2.0 v v dd < 2.7 v 100 ns 2.7 v v dd 3.6 v 27 ns delay time from sckbn to sobn output t kso2 <106> 2.0 v v dd < 2.7 v 95 ns remark n = 0 to 4 sobn (output) input data output data sibn (input) sckbn (i/o) <101> <102> <103> <104> <105> <106> remark n = 0 to 4
v850es/jg3-l chapter 34 el ectrical specifications ( pd70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 1056 of 1113 sep 22, 2011 34.8.6 i 2 c bus mode (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.0 to 3.6 v, v ss = ev ss = av ss = 0 v) normal mode high-speed mode parameter symbol min. max. min. max. unit scl0n clock frequency f clk 0 100 0 400 khz bus free time (between start and stop conditions) t buf <107> 4.7 ? 1.3 ? s hold time note 1 t hd:sta <108> 4.0 ? 0.6 ? s scl0n clock low-level width t low <109> 4.7 ? 1.3 ? s scl0n clock high-level width t high <110> 4.0 ? 0.6 ? s setup time for start/restart conditions t su:sta <111> 4.7 ? 0.6 ? s cbus compatible master 5.0 ? ? ? s data hold time i 2 c mode t hd:dat <112> 0 note 2 ? 0 note 2 0.9 note 3 s data setup time t su:dat <113> 250 ? 100 note 4 ? ns sda0n and scl0n signal rise time t r <114> ? 1000 20 + 0.1cb note 5 300 ns sda0n and scl0n signal fall time t f <115> ? 300 20 + 0.1cb note 5 300 ns stop condition setup time t su:sto <116> 4.0 ? 0.6 ? s pulse width of spike suppressed by input filter t sp <117> ? ? 0 50 ns capacitance load of each bus line cb ? 400 ? 400 pf notes 1. at the start condition, the first clock pulse is generated after the hold time. 2. the system requires a minimum of 300 ns hold time internally for the sda0n signal (at v ihmin. of scl0n signal) in order to occupy the undefined area at the falling edge of scl0n. 3. if the system does not extend the scl0n signal low hold time (t low ), only the maximum data hold time (t hd : dat ) needs to be satisfied. 4. the high-speed mode i 2 c bus can be used in the normal-mode i 2 c bus system. in this case, set the high-speed mode i 2 c bus so that it meets the following conditions. ? if the system does not extend the scl0n signal?s low state hold time: t su : dat 250 ns ? if the system extends the scl0n signal?s low state hold time: transmit the following data bit to the sda0n line prior to the scl0n line release (t rmax. + t su:dat = 1,000 + 250 = 1,250 ns: normal mode i 2 c bus specification). 5. cb: total capacitance of one bus line (unit: pf) remark n = 0 to 2
v850es/jg3-l chapter 34 el ectrical specifications ( pd70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 1057 of 1113 sep 22, 2011 i 2 c bus timing stop condition start condition restart condition stop condition scl0n (i/o) sda0n (i/o) <109> <115> <115> <114> <114> <112> <113> <111> <108> <107> <108> <117> <116> <110> remark n = 0 to 2 34.8.7 a/d converter (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , 2.7 v av ref0 = av ref1 3.6 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit resolution 10 bit overall error note 2.7 v av ref0 3.6 v 0.6 %fsr 3.0 v av ref0 3.6 v 2.6 24 s a/d conversion time t conv 2.7 v av ref0 3.0 v 3.9 24 s zero scale error 0.5 %fsr full scale error 0.5 %fsr non-linearity error 4.0 lsb differential linearity error 4.0 lsb analog input voltage v ian av ss av ref0 v reference voltage av ref0 2.7 3.6 v normal conversion mode 3 6.5 ma high-speed conversion mode 4 10 ma av ref0 current ai ref0 when a/d converter unused 5 a note excluding quantization error ( 0.05 %fsr). caution do not set (read/write) alternate-function ports during a/d conversion; otherwise the conversion resolution may be degraded. remark lsb: least significant bit fsr: full scale range
v850es/jg3-l chapter 34 el ectrical specifications ( pd70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 1058 of 1113 sep 22, 2011 34.8.8 d/a converter (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 8 bit overall error r = 2 m 1.2 %fsr settling time c = 20 pf 3 s output resistor r o output data 55h 6.42 k reference voltage av ref1 2.7 3.6 v d/a conversion operating 1 2.5 ma av ref1 current note ai ref1 d/a conversion stopped 5 a note value of 1 channel of d/a converter remark r is the output pin load resistance and c is the output pin load capacitance. 34.8.9 lvi circuit characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.0 to 3.6 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit v lvi0 2.7 2.8 2.9 v v lvi1 2.2 2.3 2.4 v detection voltage v lvi2 2.0 2.1 2.2 v response time note t ld at rising edge: after v dd reaches v lvi0 /v lvi1 /v lvi2 (max.) at falling edge: after v dd has dropped to v lvi0 /v lvi1 /v lvi2 (min.) 0.2 2.0 ms minimum pulse width t lw v dd = v lvi0 /v lvi1 (min.) 0.2 ms reference voltage stabilization wait time t lwait after v dd reaches v lvi0 /v lvi1 /v lvi2 (max.) 0.1 0.2 ms note time required to detect the detection volta ge and output an interrupt or reset signal. supply voltage (v dd ) time detection voltage (min.) operating voltage (min.) detection voltage (max.) t lwait t lw t ld t ld lvion bit = 0 1
v850es/jg3-l chapter 34 el ectrical specifications ( pd70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 1059 of 1113 sep 22, 2011 34.8.10 rtc back-up mode characteristics (1) v dd power-down timing (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.0 v to 3.6 v, rv dd = 1.8 v to 3.6 v, v ss = ev ss = av ss = 0v, c l = 50 pf) parameter symbol conditions min. typ. max. unit v ddnsr1 when using rtc backup mode, and setting the lvi detection level to 2.80 0.10 v 0.2 v/ms v dd negative slew rate v ddnsr2 when using rtc backup mode, and setting the lvi detection level to 2.30 0.10 v 0.07 v/ms (2) rv dd power-up timing (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.0 v to 3.6 v, rv dd = 1.8 v to 3.6 v, v ss = ev ss = av ss = 0v, c l = 50 pf) parameter symbol conditions min. typ. max. unit rv dd positive slew rate rv ddpsr 3.0 v/s (3) regulator output voltage for rtc backup area (vch) (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.0 v to 3.6 v, rv dd = 1.8 v to 3.6 v, v ss = ev ss = av ss = 0v, c l = 50 pf) parameter symbol conditions min. typ. max. unit regulator output voltage for rtc backup area (vch) vch 0.8 1.8 v (4) vch setup time (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.0 v to 3.6 v, rv dd = 2.0 v to 3.6 v, v ss = ev ss = av ss = 0v, c l = 50 pf) parameter symbol conditions min. typ. max. unit vch setup time t spor the time from when rv dd reaches the maximum amplitude (v dd = 2.0 to 3.6 v) until vch is stable 4.5 ms
v850es/jg3-l chapter 34 el ectrical specifications ( pd70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 1060 of 1113 sep 22, 2011 34.9 flash memory programming characteristics (1) basic characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.7 to 3.6 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit operating frequency f cpu 2.5 20 mhz supply voltage v dd 2.5 mhz f xx 20 mhz 2.7 3.6 v used for updating programs when using flash memory programmer and renesas electronics self programming library retained for 15 years 1,000 times number of rewrites c wrt used for updating data when using renesas electronics eeprom emulation library (usable rom size: 12 kb of 3 consecutive blocks) retained for 5 years 10,000 times programming temperature t prg ? 40 +85 c (2) serial write operation characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.7 to 3.6 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit flmd0, flmd1 setup time t mdset 2 3000 ms flmd0 count start time from reset t rfcf f x = 2.5 to 10 mhz 800 s flmd0 counter high-level width/ low-level width t ch /t cl 10 100 s flmd0 counter rise time/fall time t r /t f 1 s flash write mode setup timing v dd flmd1 0 v v dd reset (input) 0 v v dd flmd0 0 v t rfcf t cl t f t r t ch t mdset
v850es/jg3-l chapter 34 el ectrical specifications ( pd70f3841, 70f3842) r01uh0165ej0700 rev.7.00 page 1061 of 1113 sep 22, 2011 (3) programming characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = 2.7 to 3.6 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit chip erase time f xx = 20 mhz (when the chip erase command is executed) 105 ms write time per 256 bytes f xx = 20 mhz 2.0 ms block internal verify time f xx = 20 mhz 10 ms block blank check time f xx = 20 mhz 0.5 ms flash memory information setting time f xx = 20 mhz 30 ms remark block size = 4 kb
v850es/jg3-l chapter 35 package drawings r01uh0165ej0700 rev.7.00 page 1062 of 1113 sep 22, 2011 chapter 35 package drawings s y e s x b m l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.125 (unit:mm) item dimensions d e hd he a a1 a2 a3 20.00 0.20 14.00 0.20 22.00 0.20 16.00 0.20 1.60 max. 0.10 0.05 1.40 0.05 0.04 0.08 0.075 0.025 0.25 c e x y zd ze 0.65 0.13 0.10 0.575 0.825 l lp l1 0.50 0.60 0.15 5 3 1.00 0.20 p100gf-65-gas 3 note each lead centerline is located within 0.13 mm of its true position at maximum material condition. detail of lead end 0.30 b + + + 30 50 1 100 31 51 81 80 100-pin plastic lqfp (14x20) ( pd70f3737, 70f3738 only)
v850es/jg3-l chapter 35 package drawings r01uh0165ej0700 rev.7.00 page 1063 of 1113 sep 22, 2011 100-pin plastic lqfp (fine pitch) (14x14) s y e s x b m l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.125 (unit:mm) item dimensions d e hd he a a1 a2 a3 14.00 0.20 14.00 0.20 16.00 0.20 16.00 0.20 1.60 max. 0.10 0.05 1.40 + + + 0.05 0.25 c e x y zd ze 0.50 0.08 0.08 1.00 1.00 l lp l1 0.50 0.60 0.15 1.00 0.20 p100gc-50-ueu-1 3 3 5 detail of lead end 0.20 0.07 0.075 0.025 0.03 b 25 50 1 100 26 51 75 76
v850es/jg3-l chapter 35 package drawings r01uh0165ej0700 rev.7.00 page 1064 of 1113 sep 22, 2011 121-pin plastic fbga (8x8) item dimensions d e w a a1 a2 e 8.00 0.10 8.00 0.10 0.20 0.30 0.05 0.05 0.08 1.21 0.10 0.91 0.65 (unit:mm) 0.10 0.20 0.75 0.75 p121f1-65-cah s e y1 s a a1 a2 s y s x bab m s wb s wa zd ze index mark b a 1 2 3 4 5 6 7 8 9 10 11 a b c d e f g h j k l d e x y y1 zd ze b 0.40 index mark
v850es/jg3-l chapter 36 recommended soldering conditions r01uh0165ej0700 rev.7.00 page 1065 of 1113 sep 22, 2011 chapter 36 recommended soldering conditions the v850es/jg3-l should be soldered and mounted under the following recommended conditions. for technical information, see the following website. semiconductor device mount manual (h ttp://www.renesas.com/prod/package/manual/) table 36-1. surface mounting type soldering conditions (1/2) (1) pd70f3737gc-ueu-ax: 100-pin plast ic lqfp (fine pitch) (14 14) pd70f3738gc-ueu-ax: 100-pin plast ic lqfp (fine pitch) (14 14) pd70f3792gc-ueu-ax: 100-pin plast ic lqfp (fine pitch) (14 14) pd70f3793gc-ueu-ax: 100-pin plast ic lqfp (fine pitch) (14 14) pd70f3841gc-ueu-ax: 100-pin plast ic lqfp (fine pitch) (14 14) pd70f3842gc-ueu-ax: 100-pin plast ic lqfp (fine pitch) (14 14) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 260c, time: 60 seconds max. (at 220c or higher), count: three times or less, exposure limit: 7 days note (after that, prebake at 125c for 20 to 72 hours) ir60-207-3 partial heating pin temperature: 350c max ., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25c or le ss and 65% rh or less for the allowable storage period. caution do not use different soldering met hods together (except for partial heating). remarks 1. the v850es/jg3-l is a lead-free product. 2. for soldering methods and conditions other t han those recommended above, please contact a renesas electronics sales representative. 3. the pd70f3737gf-gas-az and pd70f3738gf-gas-ax are under development. recommended soldering conditions for them are ther efore undefined.
v850es/jg3-l chapter 36 recommended soldering conditions r01uh0165ej0700 rev.7.00 page 1066 of 1113 sep 22, 2011 table 36-1. surface mounting type soldering conditions (2/2) (2) pd70f3737f1-cah-a: 121-pin plastic fbga (8 8) pd70f3738f1-cah-a: 121-pin plastic fbga (8 8) pd70f3792f1-cah-a: 121-pin plastic fbga (8 8) pd70f3793f1-cah-a: 121-pin plastic fbga (8 8) pd70f3841f1-cah-a: 121-pin plastic fbga (8 8) pd70f3842f1-cah-a: 121-pin plastic fbga (8 8) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 260c, time: 60 seconds max. (at 220c or higher), count: three times or less, exposure limit: 7 days note (after that, prebake at 125c for 10 to 72 hours) ir60-107-3 note after opening the dry pack, store it at 25c or le ss and 65% rh or less for the allowable storage period. caution do not use different soldering methods together. remarks 1. the v850es/jg3-l is a lead-free product. 2. for soldering methods and conditions other t han those recommended above, please contact a renesas electronics sales representative.
v850es/jg3-l appendix a development tools r01uh0165ej0700 rev.7.00 page 1067 of 1113 sep 22, 2011 appendix a development tools the following development tool s are available for the dev elopment of systems that em ploy the v850es/jg3-l. figure a-1 shows the developm ent tool configuration. ? support for pc98-nx series unless otherwise specified, pr oducts supported by ibm pc/at tm compatibles are compatible with pc98-nx series computers. when using pc98-nx series co mputers, refer to the explanation for ibm pc/at compatibles. ? windows ? unless otherwise specified, ?windows? means the following oss. ? windows 98, 2000 ? windows me ? windows xp ? windows nt ? ver. 4.0
v850es/jg3-l appendix a development tools r01uh0165ej0700 rev.7.00 page 1068 of 1113 sep 22, 2011 figure a-1. development tool configuration flash memory write environment debugging software ? integrated debugger ? system simulator host machine (pc or ews) interface adapter note 2 in-circuit emulator (qb-v850essx2, qb-v850esjx3l) note 5 ? project manager (windows only) note 1 software package conversion socket or conversion adapter target system control software embedded software ? real-time os ? network library ? file system on-chip debug emulator (qb-v850mini) note 3 (qb-mini2) note 4 flash memory write adapter flash memory programmer flash memory language processing software ? c compiler package ? device file notes 1. project manager pm+ is included in the c compiler package. pm+ is only used in windows. 2. the qb-v850mini, qb-mini2, qb-v850essx2 and qb-v850esjx3l (under development) support the usb interface only. 3. the qb-v850mini is supplied with the id850qb, usb interface cable, ocd cable, self-check board, kel adapter, and kel connector. all other products are optional. 4. the qb-mini2 is supplied with usb interface cabl e, 16-pin target cable, 10-pin target cable, and 78k0-ocd board (integrated debugger is not s upplied.) all other products are optional. 5. the qb-v850essx2 (qb-v850ssx2support the pd70f3737, 70f3738 only) and qb-v850esjx3l (under development) are supplied with the id850qb, flash memory programmer (minicube2), power supply unit, and usb interfac e adapter. all other products are optional.
v850es/jg3-l appendix a development tools r01uh0165ej0700 rev.7.00 page 1069 of 1113 sep 22, 2011 a.1 software package development tools (software) commonly used with v850 microcontrollers are included this package. sp850 software package for v850 microcontrollers part number: s sp850 remark in the part number differs depending on the host machine and os used. s sp850 host machine os supply medium ab17 windows (japanese version) bb17 pc-9800 series, ibm pc/at compatibles windows (english version) cd-rom a.2 language processing software this compiler converts programs written in c into object codes executable with a microcontroller. this compiler is started from project manager pm+. ca850 c compiler package part number: s ca703000 df703738 device file this file contains informat ion peculiar to the device. this device file should be used in combi nation with a tool (ca850 or id850qb). the corresponding os and host machine di ffer depending on the tool to be used. remark in the part number differs depending on the host machine and os used. s ca703000 host machine os supply medium ab17 windows (japanese version) bb17 pc-9800 series, ibm pc/at compatibles windows (english version) 3k17 sparcstation tm sunos tm (rel. 4.1.4), solaris tm (rel. 2.5.1) cd-rom a.3 control software pm+ project manager this is control software designed to enable e fficient user program development in the windows environment. all operations used in development of a user program, such as starting the editor, building, and starting the debugger, can be performed from pm+. pm+ is included in c compiler package ca850. it can only be used in windows.
v850es/jg3-l appendix a development tools r01uh0165ej0700 rev.7.00 page 1070 of 1113 sep 22, 2011 a.4 debugging tools (hardware) a.4.1 when using iecube ? qb-v850essx2, qb-v850esjx3l the system configuration when connec ting the qb-v850esjx3l to the host machine (pc-9821 series, pc/at compatible) is shown below. even if optional pr oducts are not prepared, connection is possible. figure a-2. system configuration (whe n using qb-v850essx2, qb-v850esjx3l) (1/2) <12> mount adapter for device mounting <13> target connector for mounting on target system <8> exchange adapter exchanges pins among different microcontroller types <9> check pin adapter (s type only) enables signal monitoring <10> space adapter each adapter can adjust height by 5.6 mm. <14> target system <7> extension probe probe can be connected (s and t types) <12> mount adapter for device mounting <13> target connector for mounting on target system <11> yq connector connector for connecting to emulator <8> exchange adapter exchanges pins among different microcontroller types <10> space adapter each adapter can adjust height by 3.2 mm. <6> check pin adapter (under development) enables signal monitoring (s and t types) <5> iecube <1> s-type socket configuration optional required <4> power supply <2> cd-rom <3> usb cable simple flash memory programmer <14> target system t-type socket configuration system configuration accessories remark qb-v850essx2 support the pd70f3737, 70f3738 only.
v850es/jg3-l appendix a development tools r01uh0165ej0700 rev.7.00 page 1071 of 1113 sep 22, 2011 figure a-2. system configuration (whe n using qb-v850essx2, qb-v850esjx3l) (2/2) <1> host machine (pc-9821 series, ibm-pc/at compatibles) <2> debugger, usb driver, manuals, etc. (id850qb disk, accessory disk note 1 ) <3> usb interface cable <4> ac adapter <5> in-circuit emulator (qb-v850essx2, qb-v850esjx3l) <6> check pin adapter (s and t types) (qb-144-ca-01 note 2 ) (optional) <7> extension probe (s and t ty pes) (qb-144-ep-01s) (optional) <8> exchange adapter note 3 (s type: qb-100gc-ea-01s (gc package), qb-100gf-ea-01s (gf package), t type: qb-100gc-ea-01t (gc package ), qb-100gf-ea-01t (gf package)) <9> check pin adapter note 4 (s type only) (qb-100-ca-01s) (optional) <10> space adapter note 4 (s type: qb-100-sa-01s (gc/gf packages), t type: qb-100gc-ys-01t (gf package), qb-100gf-ys-01t (gf package) (optional) <11> yq connector note 3 (t type only) (qb-100gc-yq-01t) (gc pa ckage), qb-100gf-yq-01t (gf package) <12> mount adapter (s type: qb-100gc-ma-01s (g c package), qb-100gf-ma-01s (gf package), t type: qb-100gf-hq-01t (gc package), qb-100g f-hq-01t (gf package)) (optional) <13> target connector note 3 (s type: qb-100gc-tc-01s (gc pack age), qb-100gf-tc-01s (gf package), t type: qb-100gc-nq-01t (gc package ), qb-100gf-nq-01t (gf package)) <14> target system notes 1. download the device file from t he renesas electronics website. http://www2.renesas.com /micro/en/ods/index.html 2. under development 3. supplied with the device depending on the ordering number. ? when qb-v850essx2-zzz and qb-v850esjx3l-zzz are ordered the exchange adapter and the target connector are not supplied. ? when qb-v850essx2-s100gc, qb-v850esjx3l-s100gc are ordered the qb-100gc-ea-01s and qb -100gc-tc-01s are supplied. ? when qb-v850essx2-s100gf is ordered the qb-100gf-ea-01s and qb -100gf-tc-01s are supplied. ? when qb-v850essx2-t100gc, qb-v850esjx3l-t100gc are ordered the qb-100gc-ea-01t, qb-100gc-yq- 01t, and qb-100gc-nq-01t are supplied. ? when qb-v850essx2-t100gf is ordered the qb-100gf-ea-01t, qb-100gf-yq-0 1t, and qb-100gf-nq-01t are supplied. 4. when using both <9> and <10>, the order between <9> and <10> is not cared. remark qb-v850essx2 support the pd70f3737, 70f3738 only.
v850es/jg3-l appendix a development tools r01uh0165ej0700 rev.7.00 page 1072 of 1113 sep 22, 2011 <5> qb-v850essx2 note qb-v850esjx3l note in-circuit emulator the in-circuit emulator serves to d ebug hardware and software when developing application systems using the v850es/jg3-l. it supports the integrated debugger id850qb. this emulator should be used in combination with a power supply unit and emulation probe. use the usb interface c able to connect this emulator to the host machine. <3> usb interface cable cable to connect the host machine and the qb-v850essx2, qb-v850esjx3l note2 . <4> ac adapter 100 to 240 v can be supported by replacing the ac plug. <8> qb-100gc-ea-01s qb-100gf-ea-01s qb-100gc-ea-01t qb-100gf-ea-01t exchange adapter adapter to perform pin conversion. ? qb-100gc-ea-01s: 100-pin pl astic lqfp (gc-ueu type) ? qb-100gf-ea-01s: 100-pin pl astic lqfp (gf-gas type) ? qb-100gc-ea-01t: 100-pin pl astic lqfp (gc-ueu type) ? qb-100gf-ea-01t: 100-pin plastic lqfp (gc-gas type) <9> qb-100-ca-01s (s type only) check pin adapter adapter used in waveform monitoring using the oscilloscope, etc. ? qb-100-ca-01s: gc-ueu/gf-gas type <10> qb-100-sa-01s qb-100gc-ys-01t qb-100gf-ys-01t space adapter adapter to adjust the height. ? qb-100gf-sa-01s: gc-ueu/gf-gas type ? qb-100gc-ys-01t: 100-pin plastic lqfp (gc-ueu type) ? qb-100gf-ys-01t: 100-pin plastic lqfp (gf-gas type) <11> qb-100gc-yq-01t qb-100gf-yq-01t (t type only) yq connector conversion adapter to connect tar get connector and exchange adapter ? qb-100gc-yq-01t: 100-pin plastic lqfp (gc-ueu type) ? qb-100gf-yq-01t: 100-pin plastic lqfp (gf-gas type) <12> qb-100gc-ma-01s qb-100gf-ma-01s qb-100gc-hq-01t qb-100gf-hq-01t mount adapter adapter to mount the v850es/jg3-l with socket. ? qb-100gc-ma-01s: 100-pin pl astic lqfp (gc-ueu type) ? qb-100gf-ma-01s: 100-pin pl astic lqfp (gf-gas type) ? qb-100gc-hq-01t: 100-pin plastic lqfp (gc-ueu type) ? qb-100gf-hq-01t: 100-pin plastic lqfp (gf-gas type) <13> qb-100gc-tc-01s qb-100gf-tc-01s qb-100gc-nq-01t qb-100gf-nq-01t target connector connector to solder on the target system. ? qb-100gc-tc-01s: 100-pin plastic lqfp (gc-ueu type) ? qb-100gf-tc-01s: 100-pin pl astic lqfp (gf-gas type) ? qb-100gc-nq-01t: 100-pin plastic lqfp (gc-ueu type) ? qb-100gf-nq-01t: 100-pin plastic lqfp (gf-gas type) note the qb-v850essx2 and qb-v850esjx3l note2 are supplied with a power supply unit, usb interface cable, and flash memory programmer (minicube2). it is also supplied with integrated debugger id850qb as control software. remark the numbers in the angle brackets correspond to the numbers in figure a-2.
v850es/jg3-l appendix a development tools r01uh0165ej0700 rev.7.00 page 1073 of 1113 sep 22, 2011 a.4.2 when using minicube qb-v850mini (1) on-chip emulat ion using minicube the system configuration when connecting mi nicube to the host machine (pc-9821 series, pc/at compatible) is shown below. figure a-3. on-chip emulation system configuration <7> <6> target system v850es/jg3-l <1> <4> <3> <5> <2> s t a t u s t a r g e t p o w e r <1> host machine pc with usb ports <2> cd-rom note 1 contents such as integrated debugger id850qb, n-wire checker, device driver, and documents are included in cd-rom. it is supplied with minicube. <3> usb interface cable usb cable to connect the host machine and minicube. it is supplied with minicube. the cable length is approximately 2 m. <4> minicube on-chip debug emulator this on-chip debug emulator serves to debug hardware and software when developing application systems using the v 850es/jg3-l. it supports integrated debugger id850qb. <5> ocd cable cable to connect minicube and the target system. it is supplied with minicube. the cable length is approximately 20 cm. <6> connector conversion board kel adapter this conversion board is supplied with minicube. <7> minicube connector kel connector note 2 8830e-026-170s (supplied with minicube) 8830e-026-170l (sold separately) notes 1. download the device file from t he renesas electronics website. http://www2.renesas.com /micro/en/ods/index.html 2. product of kel corporation remark the numbers in the angular brackets co rrespond to the numbers in figure a-3.
v850es/jg3-l appendix a development tools r01uh0165ej0700 rev.7.00 page 1074 of 1113 sep 22, 2011 a.4.3 when using minicube2 qb-mini2 the system configuration when connec ting minicube2 to the host machine (pc-9821 series, pc/at compatible) is shown below. figure a-4. system configuration of on-chip emulation system <6> <5> target system v850es/jg3-l <1> <2> software <4> <3> m in ic u b e 2 <1> host machine pc with usb ports <2> software the integrated debugger id850qb, device file, etc. download the device file from the renesas electronics website. http://www2.renesas.com/micro/en/ods/index.html <3> usb interface cable usb cable to connect the host machine and minicube. it is supplied with minicube. the cable length is approximately 2 m. <4> minicube2 on-chip debug emulator this on-chip debug emulator serves to debug hardware and software when developing application systems using the v 850es/jg3-l. it supports integrated debugger id850qb. <5> 16-pin target cable cable to connect minicube2 and the target system. it is supplied with minicube. the cable length is approximately 15 cm. <6> target connector (sold separately) use a 16- pin general-purpose connector with 2.54 mm pitch. remark the numbers in the angular brackets co rrespond to the numbers in figure a-4.
v850es/jg3-l appendix a development tools r01uh0165ej0700 rev.7.00 page 1075 of 1113 sep 22, 2011 a.5 debugging tools (software) this debugger supports the in-circuit emul ators for v850 microcontrollers. the id850qb is windows-based software. it has improved c-compatible debugging func tions and can display the results of tracing with the source program using an int egrating window function that associates the source program, disassemble display, and memory display with the trace result. it should be used in combinat ion with the device file. id850qb integrated debugger part number: s id703000-qb (id850qb) remark in the part number differs depending on the host machine and os used. s id703000-qb host machine os supply medium ab17 windows (japanese version) bb17 pc-9800 series, ibm pc/at compatibles windows (english version) cd-rom
v850es/jg3-l appendix a development tools r01uh0165ej0700 rev.7.00 page 1076 of 1113 sep 22, 2011 a.6 embedded software the rx850 and rx850 pro are real-time oss conforming to itron 3.0 specifications. a tool (configurator) for generating multip le information tables is supplied. rx850 pro has more functions than the rx850. rx850, rx850 pro real-time os part number: s rx703000- ??? (rx850) s rx703100- ??? (rx850 pro) applilet ? (under development) this is a driver configurator that automatically generates sample programs for the v850es/jg3-l. rx-fs850 (file system) this is a fat file system function. it is a file system that supports the cd-rom file system function. this file system is used with the real-time os rx850 pro. caution to purchase the rx850 or rx850 pro, first fill in the purchase application form and sign the license agreement. remark and ??? in the part number differ depending on the host machine and os used. s rx703000- ??? s rx703100- ??? ??? product outline maximum number for use in mass production 001 evaluation object do not use for mass-produced product. 100k 0.1 million units 001m 1 million units 010m mass-production object 10 million units s01 source program object source program for mass production host machine os supply medium ab17 windows (japanese version) bb17 pc-9800 series, ibm pc/at compatibles windows (english version) 3k17 sparcstation solaris (rel. 2.5.1) cd-rom
v850es/jg3-l appendix a development tools r01uh0165ej0700 rev.7.00 page 1077 of 1113 sep 22, 2011 a.7 flash memory writing tools flashpro iv (part number: pg-fp4) flashpro v (part number: pg-fp5) flash memory programmer flash memory programmer dedicated to mi crocontrollers with internal flash memory. qb-mini2 (minicube2) on-chip debug em ulator with programming function. fa-100gc-ueu-b fa-100gf-gas-b flash memory writing adapter flash memory writing adapter used connec ted to the flashpro iv, flashpro v, etc. (not wired). ? fa-100gc-ueu-b: 100-pin plastic lqfp (gc-ueu type) ? fa-100gf-gas-b: 100-pin plastic lqfp (gf-gas type) fa-70f3738gc-ueu-rx fa-70f3738gf-gas-rx fa-70f3738f1-cah-rx fa-70f3793f1-cah-rx fa-70f3793gc-ueu-rx flash memory writing adapter flash memory writing adapter used connec ted to the flashpro iv, flashpro v, etc. (already wired). ? fa-70f3738gc-ueu-rx: 100-pin plastic lqfp (gc-ueu type) ? fa-70f3738gf-gas-rx: 100-pin plastic lqfp (gf-gas type) ? fa-70f3738f1-cah-rx: 121-pin plastic fbga (f1-cah type of pd70f3737, 70f3738) ? fa-70f3793f1-cah-rx: 121-pin plastic fbga (f1-cah type of pd70f3792, 70f3793, 70f3841, 70f3842) ? fa-70f3793gc-ueu-rx: 100-pin plastic lqfp (gc-ueu type of pd70f3792, 70f3793, 70f3841, 70f3842) remark fa-100gc-ueu-b, fa-100gf-gas-b, fa- 70f3738gc-ueu-rx, fa-70f3738gf-gas-rx, fa-70f3738f1-cah-rx, fa-70f3793f1- cah-rx and fa-70f3793gc-ueu-rx are products of naito densei machida mfg. co., ltd. tel: +81-42-750-4172
v850es/jg3-l appendix b major differences bet ween products r01uh0165ej0700 rev.7.00 page 1078 of 1113 sep 22, 2011 appendix b major diffe rences between products table b-1. major differences be tween v850es/jg3-l and v850es/jg2 v850es/jg3-l major differences pd70f3841 pd70f3842 pd70f3792 pd70f3793 pd70f3737 pd70f3738 v850es/jg2 bv dd , bv ss pins changed to ev dd , ev ss provided pin port (5 v tolerant) 83 (31) 84 (31) 84 (40) internal flash memory 768 k/1 mb 384/512 kb 128/256 kb 128/256/384/5 12/640 kb memory internal ram 80 kb note 32/40 kb 8/16 kb 12/24/32/40/4 8 kb 2.2 to 3.6 v @5 mhz 2.7 to 3.6 v @20 mhz v dd , ev dd 2.0 to 3.6 v @2.5 mhz - 2.85 to 3.6 v @20 mhz supply voltage a/d, d/a operating voltage 2.7 to 3.6 v 3.0 to 3.6 v lv i 3 levels: 2.8 v (typ.), 2.3 v (typ.) , 2.1 v (typ.) selectable by software 2 levels: 2.8 v (typ.), 2.3 v (typ.) selectable by software 1 level: 3.0 v (typ.) interrupt condition at low-voltage detection when supply voltage drops or ri ses across the detection voltage when supply voltage drops below the detection voltage low-volt age detector (lvi) ramf none provided low-voltage stop/ low-voltage subclock operation/ low-voltage sub-idle mode provided none standby function rtc backup mode provided none none crc circuit provided none boot area 64 kb 32 kb 56 kb flash memory block configuration block 0 to last block: 4 kb each block 0 to last block: 2 kb each blocks 0 to 3: 28 kb each blocks 4 to 7: 4 kb each block 8 to last block: 64 kb each note including 24 kb of expanded internal ram.
v850es/jg3-l appendix b major differences bet ween products r01uh0165ej0700 rev.7.00 page 1079 of 1113 sep 22, 2011 table b-3. major differenc es between v850es/jg3-l products major difference pd70f3841 pd70f3842 pd70f3792 pd70f3793 pd70f3737 pd70f3738 flash memory 1 mb 768 kb 384 kb 512 kb 128 kb 256 kb internal memory ram 80 kb note 80 kb note 32 kb 40 kb 8 kb 16 kb port number 83 84 interrupt number 64 (external interrupt : 9) 57 (external interrupt : 9) intrtc0 available none intrct1 available none rtc intrtc2 available none inttua3r available none uarta3 inttua3t available none inttua4r available none uarta4 inttua4t available none inttua5r available none uarta5 inttua5t available none inttuc1r available none interrupt request signal uartc1 inttuc1t available none rtc available none rtc backup mode available none uarta 6 channels 3 channels uartc available none intrtc1 available none intua3r available none intua3t available none intua4r available none intua4t available none intua5r available none dma start factors intua5t available none lvi detection level 3 levels 2 levels package 100-pinqfp (14x20) none available operation power supply voltage 2.0 to 3.6 v@2.5 mhz available none note including 24 kb of expanded internal ram.
v850es/jg3-l appendix b major differences bet ween products r01uh0165ej0700 rev.7.00 page 1080 of 1113 sep 22, 2011 table b-3. pin layout in lqfp package pin number pd70f3792gc-ueu-ax pd70f3793gc-ueu-ax pd70f3841gc-ueu-ax pd70f3842gc-ueu-ax pd70f3737gc-ueu-ax pd70f3738gc-ueu-ax 7 pin p02/nmi/a21 pdh5/a21 17 pin rv dd p02/nmi 18 pin p03/intp0/adtrg/rtc1hz p03/intp0/adtrg 19 pin p04/intp1/rtcdiv/rtccl p04/intp1 31 pin p36/txda3 p36 32 pin p37/rxda3 p37 45 pin p92/a2/tip41/top41/txda4 p92/a2/tip41/top41 46 pin p93/a3/tip40/top40/rxda4 p93/a3/tip40/top40 47 pin p94/a4/tip31/top31/txda5 p94/a4/tip31/top31 48 pin p95/a5/tip30/top30/rxda5 p95/a5/tip30/top30 49 pin p96/a6/txdc0/tip21/top21 p96/a6/tip21/top21 50 pin p97/a7/sib1/rxdc0/tip20/top20 p97/a7/sib1/tip20/top20 table b-4. pin layout in fbga package pin number pd70f3792f1-cah-a pd70f3793f1-cah-a pd70f3841f1-cah-a pd70f3842f1-cah-a pd70f3737f1-cah-a pd70f3738f1-cah-a d2 pin rv dd v dd g3 pin p03/intp0/adtrg/rtc1hz p03/intp0/adtrg g4 pin p02/nmi/a21 pdh5/a21 h4 pin p04/intp1/rtcdiv/rtccl p04/intp1 h5 pin p36/txda3 p36 j2 pin p02/nmi/a21 p02/nmi j6 pin p37/rxda3 p37 j9 pin p93/a3/tip40/top40/rxda4 p93/a3/tip40/top40 j11 pin p97/a7/sib1/rxdc0/tip20/top20 p97/a7/sib1/tip20/top20 k9 pin p92/a2/tip41/top41/txda4 p92/a2/tip41/top41 k10 pin p95/a5/tip30/top30/rxda5 p95/a5/tip30/top30 k11 pin p96/a6/txdc0/tip21/top21 p96/a6/tip21/top21 l10 pin p94/a4/tip31/top31/txda5 p94/a4/tip31/top31
v850es/jg3-l appendix c register index r01uh0165ej0700 rev.7.00 page 1081 of 1113 sep 22, 2011 appendix c register index (1/11) symbol name unit page ada0cr0 a/d conversion result register 0 adc 515 ada0cr0h a/d conversion result register 0h adc 515 ada0cr1 a/d conversion result register 1 adc 515 ada0cr1h a/d conversion result register 1h adc 515 ada0cr2 a/d conversion result register 2 adc 515 ada0cr2h a/d conversion result register 2h adc 515 ada0cr3 a/d conversion result register 3 adc 515 ada0cr3h a/d conversion result register 3h adc 515 ada0cr4 a/d conversion result register 4 adc 515 ada0cr4h a/d conversion result register 4h adc 515 ada0cr5 a/d conversion result register 5 adc 515 ada0cr5h a/d conversion result register 5h adc 515 ada0cr6 a/d conversion result register 6 adc 515 ada0cr6h a/d conversion result register 6h adc 515 ada0cr7 a/d conversion result register 7 adc 515 ada0cr7h a/d conversion result register 7h adc 515 ada0cr8 a/d conversion result register 8 adc 515 ada0cr8h a/d conversion result register 8h adc 515 ada0cr9 a/d conversion result register 9 adc 515 ada0cr9h a/d conversion result register 9h adc 515 ada0cr10 a/d conversion result register 10 adc 515 ada0cr10h a/d conversion result register 10h adc 515 ada0cr11 a/d conversion result register 11 adc 515 ada0cr11h a/d conversion result register 11h adc 515 ada0m0 a/d converter mode register 0 adc 508 ada0m1 a/d converter mode register 1 adc 510 ada0m2 a/d converter mode register 2 adc 513 ada0pfm power fail compare mode register adc 517 ada0pft power fail compare threshold value register adc 518 ada0s analog input channel specification register adc 514 adic interrupt control register intc 802 awc address wait control register bcu 203 bcc bus cycle control register bcu 204 bsc bus size configuration register bcu 192 cb0ctl0 csib0 control register 0 csib 636 cb0ctl1 csib0 control register 1 csib 639 cb0ctl2 csib0 control register 2 csib 640 cb0ric interrupt control register intc 802 cb0rx csib0 receive data register csib 634 cb0rxl csib0 receive data register l csib 634 cb0str csib0 status register csib 642 cb0tic interrupt control register intc 802
v850es/jg3-l appendix c register index r01uh0165ej0700 rev.7.00 page 1082 of 1113 sep 22, 2011 (2/11) symbol name unit page cb0tx csib0 transmit data register csi 635 cb0txl csib0 transmit data register l csi 635 cb1ctl0 csib1 control register 0 csi 636 cb1ctl1 csib1 control register 1 csi 639 cb1ctl2 csib1 control register 2 csi 640 cb1ric interrupt control register intc 802 cb1rx csib1 receive data register csi 634 cb1rxl csib1 receive data register l csi 634 cb1str csib1 status register csi 642 cb1tic interrupt control register intc 802 cb1tx csib1 transmit data register csi 635 cb1txl csib1 transmit data register l csi 635 cb2ctl0 csib2 control register 0 csi 636 cb2ctl1 csib2 control register 1 csi 639 cb2ctl2 csib2 control register 2 csi 640 cb2ric interrupt control register intc 802 cb2rx csib2 receive data register csi 634 cb2rxl csib2 receive data register l csi 634 cb2str csib2 status register csi 642 cb2tic interrupt control register intc 802 cb2tx csib2 transmit data register csi 635 cb2txl csib2 transmit data register l csi 635 cb3ctl0 csib3 control register 0 csi 636 cb3ctl1 csib3 control register 1 csi 639 cb3ctl2 csib3 control register 2 csi 640 cb3ric interrupt control register intc 802 cb3rx csib3 receive data register csi 634 cb3rxl csib3 receive data register l csi 634 cb3str csib3 status register csi 642 cb3tic interrupt control register intc 802 cb3tx csib3 transmit data register csi 635 cb3txl csib3 transmit data register l csi 635 cb4ctl0 csib4 control register 0 csi 636 cb4ctl1 csib4 control register 1 csi 639 cb4ctl2 csib4 control register 2 csi 640 cb4ric interrupt control register intc 802 cb4rx csib4 receive data register csi 634 cb4rxl csib4 receive data register l csi 634 cb4str csib4 status register csi 642 cb4tic interrupt control register intc 802 cb4tx csib4 transmit data register csi 635 cb4txl csib4 transmit data register l csi 635 ccls cpu operation clock status register cg 223 ckc clock control register cg 227 ckthsel clock-through select register cg 224
v850es/jg3-l appendix c register index r01uh0165ej0700 rev.7.00 page 1083 of 1113 sep 22, 2011 (3/11) symbol name unit page clm clock monitor mode register clm 884 crcd crc data register crc 894 crcin crc input register crc 894 ctbp callt base pointer cpu 59 ctpc callt execution status saving register cpu 58 ctpsw callt execution status saving register cpu 58 da0cs0 d/a conversion value setting register 0 dac 548 da0cs1 d/a conversion value setting register 1 dac 548 da0m d/a converter mode register dac 547 dadc0 dma addressing control register 0 dmac 766 dadc1 dma addressing control register 1 dmac 766 dadc2 dma addressing control register 2 dmac 766 dadc3 dma addressing control register 3 dmac 766 dbc0 dma transfer count register 0 dmac 765 dbc1 dma transfer count register 1 dmac 765 dbc2 dma transfer count register 2 dmac 765 dbc3 dma transfer count register 3 dmac 765 dbpc exception/debug trap status saving register cpu 59 dbpsw exception/debug trap status saving register cpu 59 dchc0 dma channel control register 0 dmac 767 dchc1 dma channel control register 1 dmac 767 dchc2 dma channel control register 2 dmac 767 dchc3 dma channel control register 3 dmac 767 dda0h dma destination address register 0h dmac 764 dda0l dma destination address register 0l dmac 764 dda1h dma destination address register 1h dmac 764 dda1l dma destination address register 1l dmac 764 dda2h dma destination address register 2h dmac 764 dda2l dma destination address register 2l dmac 764 dda3h dma destination address register 3h dmac 764 dda3l dma destination address register 3l dmac 764 dmaic0 interrupt control register intc 802 dmaic1 interrupt control register intc 802 dmaic2 interrupt control register intc 802 dmaic3 interrupt control register intc 802 dsa0h dma source address register 0h dmac 763 dsa0l dma source address register 0l dmac 763 dsa1h dma source address register 1h dmac 763 dsa1l dma source address register 1l dmac 763 dsa2h dma source address register 2h dmac 763 dsa2l dma source address register 2l dmac 763 dsa3h dma source address register 3h dmac 763 dsa3l dma source address register 3l dmac 763 dtfr0 dma trigger factor register 0 dmac 768 dtfr1 dma trigger factor register 1 dmac 768
v850es/jg3-l appendix c register index r01uh0165ej0700 rev.7.00 page 1084 of 1113 sep 22, 2011 (4/11) symbol name unit page dtfr2 dma trigger factor register 2 dmac 768 dtfr3 dma trigger factor register 3 dmac 768 dwc0 data wait control register 0 bcu 200 ecr interrupt source register cpu 56 eipc interrupt status saving register cpu 55 eipsw interrupt status saving register cpu 55 eximc external bus interface mode control register bcu 190 fepc nmi status saving register cpu 56 fepsw nmi status saving register cpu 56 iic0 iic shift register 0 i2c 703 iic1 iic shift register 1 i2c 703 iic2 iic shift register 2 i2c 703 iicc0 iic control register 0 i2c 689 iicc1 iic control register 1 i2c 689 iicc2 iic control register 2 i2c 689 iiccl0 iic clock select register 0 i2c 699 iiccl1 iic clock select register 1 i2c 699 iiccl2 iic clock select register 2 i2c 699 iicf0 iic flag register 0 i2c 697 iicf1 iic flag register 1 i2c 697 iicf2 iic flag register 2 i2c 697 iicic0 interrupt control register intc 802 iicic1 interrupt control register intc 802 iicic2 interrupt control register intc 802 iics0 iic status register 0 i2c 694 iics1 iic status register 1 i2c 694 iics2 iic status register 2 i2c 694 iicx0 iic function expansion register 0 i2c 700 iicx1 iic function expansion register 1 i2c 700 iicx2 iic function expansion register 2 i2c 700 imr0 interrupt mask register 0 intc 804 imr0h interrupt mask register 0h intc 804 imr0l interrupt mask register 0l intc 804 imr1 interrupt mask register 1 intc 804 imr1h interrupt mask register 1h intc 804 imr1l interrupt mask register 1l intc 804 imr2 interrupt mask register 2 intc 804 imr2h interrupt mask register 2h intc 804 imr2l interrupt mask register 2l intc 804 imr3 interrupt mask register 3 intc 804 imr3h interrupt mask register 3h intc 804 imr3l interrupt mask register 3l intc 804 intf0 external interrupt falling edge specification register 0 intc 818 intf3 external interrupt falling edge specification register 3 intc 819 intf9h external interrupt falling edge specification register 9h intc 820
v850es/jg3-l appendix c register index r01uh0165ej0700 rev.7.00 page 1085 of 1113 sep 22, 2011 (5/11) symbol name unit page intr0 external interrupt rising edge specification register 0 intc 818 intr3 external interrupt rising edge specification register 3 intc 819 intr9h external interrupt rising edge specification register 9h intc 820 ispr in-service priority register intc 807 kric interrupt control register intc 802 krm key return mode register kr 826 lockr lock register cg 228 lviic interrupt control register intc 802 lvim low voltage detection register lvi 889 lvis low voltage detection level select register lvi 890 nfc noise elimination control register intc 821 ocdm on-chip debug mode register dcu 937 ocks0 iic division clock select register 0 i2c 703 ocks1 iic division clock select register 1 i2c 703 osts oscillation stabilization time select register standby 832 p0 port 0 register port 103 p1 port 1 register port 107 p3 port 3 register port 110 p3h port 3 register h port 110 p3l port 3 register l port 110 p4 port 4 register port 115 p5 port 5 register port 117 p7h port 7 register h port 123 p7l port 7 register l port 123 p9 port 9 register port 125 p9h port 9 register h port 125 p9l port 9 register l port 125 pc program counter cpu 53 pcc processor clock control register cg 219 pcm port cm register port 132 pct port ct register port 134 pdh port dh register port 136 pdl port dl register port 139 pdlh port dl register h port 139 pdll port dl register l port 139 pf0 port 0 function register port 106 pf3 port 3 function register port 114 pf3h port 3 function register h port 114 pf3l port 3 function register l port 114 pf4 port 4 function register port 116 pf5 port 5 function register port 121 pf9 port 9 function register port 131 pf9h port 9 function register h port 131 pf9l port 9 function register l port 131 pfc0 port 0 function control register port 105
v850es/jg3-l appendix c register index r01uh0165ej0700 rev.7.00 page 1086 of 1113 sep 22, 2011 (6/11) symbol name unit page pfc3 port 3 function control register port 112 pfc3h port 3 function control register h port 112 pfc3l port 3 function control register l port 112 pfc4 port 4 function control register port 116 pfc5 port 5 function control register port 119 pfc9 port 9 function control register port 128 pfc9h port 9 function control register h port 128 pfc9l port 9 function control register l port 128 pfce0 port 0 function control extension register port 105 pfce3l port 3 function control extension register l port 112 pfce5 port 5 function control extension register port 119 pfce9 port 9 function control extension register port 128 pfce9h port 9 function control extension register h port 128 pfce9l port 9 function control extension register l port 128 pic0 interrupt control register intc 802 pic1 interrupt control register intc 802 pic2 interrupt control register intc 802 pic3 interrupt control register intc 802 pic4 interrupt control register intc 802 pic5 interrupt control register intc 802 pic6 interrupt control register intc 802 pic7 interrupt control register intc 802 pllctl pll control register cg 227 plls pll lockup time specification register cg 229 pm0 port 0 mode register port 104 pm1 port 1 mode register port 108 pm3 port 3 mode register port 110 pm3h port 3 mode register h port 110 pm3l port 3 mode register l port 110 pm4 port 4 mode register port 115 pm5 port 5 mode register port 118 pm7h port 7 mode register h port 123 pm7l port 7 mode register l port 123 pm9 port 9 mode register port 125 pm9h port 9 mode register h port 125 pm9l port 9 mode register l port 125 pmc0 port 0 mode control register port 104 pmc3 port 3 mode control register port 111 pmc3h port 3 mode control register h port 111 pmc3l port 3 mode control register l port 111 pmc4 port 4 mode control register port 116 pmc5 port 5 mode control register port 118 pmc9 port 9 mode control register port 125 pmc9h port 9 mode control register h port 125 pmc9l port 9 mode control register l port 125
v850es/jg3-l appendix c register index r01uh0165ej0700 rev.7.00 page 1087 of 1113 sep 22, 2011 (7/11) symbol name unit page pmccm port cm mode control register port 133 pmcct port ct mode control register port 135 pmcdh port dh mode control register port 137 pmcdl port dl mode control register port 140 pmcdlh port dl mode control register h port 140 pmcdll port dl mode control register l port 140 pmcm port cm mode register port 132 pmct port ct mode register port 134 pmdh port dh mode register port 137 pmdl port dl mode register port 139 pmdlh port dl mode register h port 139 pmdll port dl mode register l port 139 prcmd command register cpu 91 prscm0 prescaler compare register 0 rtc 454, 478 prscm1 prescaler compare register 1 brg 679 prscm2 prescaler compare register 2 brg 679 prscm3 prescaler compare register 3 brg 679 prsm0 prescaler mode register 0 rtc 453, 479 prsm1 prescaler mode register 1 brg 678 prsm2 prescaler mode register 2 brg 678 prsm3 prescaler mode register 3 brg 678 psc power save control register cg 830 psmr power save mode register cg 831 psw program status word cpu 57 r0 to r31 general-purpose registers cpu 53 rc1alh alarm minute set register rtc 476 rc1alm alarm time set register rtc 476 rc1alw alarm week set register rtc 477 rc1cc0 rtc control register 0 rtc 465 rc1cc1 rtc control register 1 rtc 465 rc1cc2 rtc control register 2 rtc 467 rc1cc3 rtc control register 3 rtc 468 rc1day day count register rtc 472 rc1hour hour count register rtc 470 rc1min minute count register rtc 470 rc1month month count register rtc 474 rc1sec second count register rtc 469 rc1subc sub-count register rtc 469 rc1subu time error correction register rtc 475 rc1week week count register rtc 473 rc1year year count register rtc 474 rcm internal oscillation mode register cg 223 regovl0 regulator output voltage level control register 0 regc 834 regpr regulator protection register regc 833 resf reset source flag register reset 872
v850es/jg3-l appendix c register index r01uh0165ej0700 rev.7.00 page 1088 of 1113 sep 22, 2011 (8/11) symbol name unit page rtbh0 real-time output buffer register 0h rtp 499 rtbl0 real-time output buffer register 0l rtp 499 rtc0ic interrupt control register intc 802 rtc1ic interrupt control register intc 802 rtc2ic interrupt control register intc 802 rtcbumctl0 rtc backup control register 0 rtc 861 rtpc0 real-time output port control register 0 rtp 501 rtpm0 real-time output port mode register 0 rtp 500 selcnt0 selector operation control register 0 timer 328 soscamctl subclock low-power operation control register standby 862 sva0 slave address register 0 i2c 704 sva1 slave address register 1 i2c 704 sva2 slave address register 2 i2c 704 sys system status register cpu 92 tm0cmp0 tmm0 compare register 0 timer 444 tm0ctl0 tmm0 control register 0 timer 443 tm0eqic0 interrupt control register intc 802 tp0ccic0 interrupt control register intc 802 tp0ccic1 interrupt control register intc 802 tp0ccr0 tmp0 capture/compare register 0 timer 246 tp0ccr1 tmp0 capture/compare register 1 timer 248 tp0cnt tmp0 counter read buffer register timer 250 tp0ctl0 tmp0 control register 0 timer 240 tp0ctl1 tmp0 control register 1 timer 241 tp0ioc0 tmp0 i/o control register 0 timer 242 tp0ioc1 tmp0 i/o control register 1 timer 243 tp0ioc2 tmp0 i/o control register 2 timer 244 tp0opt0 tmp0 option register 0 timer 245 tp0ovic interrupt control register intc 802 tp1ccic0 interrupt control register intc 802 tp1ccic1 interrupt control register intc 802 tp1ccr0 tmp1 capture/compare register 0 timer 246 tp1ccr1 tmp1 capture/compare register 1 timer 248 tp1cnt tmp1 counter read buffer register timer 250 tp1ctl0 tmp1 control register 0 timer 240 tp1ctl1 tmp1 control register 1 timer 241 tp1ioc0 tmp1 i/o control register 0 timer 242 tp1ioc1 tmp1 i/o control register 1 timer 243 tp1ioc2 tmp1 i/o control register 2 timer 244 tp1opt0 tmp1 option register 0 timer 245 tp1ovic interrupt control register intc 802 tp2ccic0 interrupt control register intc 802 tp2ccic1 interrupt control register intc 802 tp2ccr0 tmp2 capture/compare register 0 timer 246 tp2ccr1 tmp2 capture/compare register 1 timer 248
v850es/jg3-l appendix c register index r01uh0165ej0700 rev.7.00 page 1089 of 1113 sep 22, 2011 (9/11) symbol name unit page tp2cnt tmp2 counter read buffer register timer 250 tp2ctl0 tmp2 control register 0 timer 240 tp2ctl1 tmp2 control register 1 timer 241 tp2ioc0 tmp2 i/o control register 0 timer 242 tp2ioc1 tmp2 i/o control register 1 timer 243 tp2ioc2 tmp2 i/o control register 2 timer 244 tp2opt0 tmp2 option register 0 timer 245 tp2ovic interrupt control register intc 802 tp3ccic0 interrupt control register intc 802 tp3ccic1 interrupt control register intc 802 tp3ccr0 tmp3 capture/compare register 0 timer 246 tp3ccr1 tmp3 capture/compare register 1 timer 248 tp3cnt tmp3 counter read buffer register timer 250 tp3ctl0 tmp3 control register 0 timer 240 tp3ctl1 tmp3 control register 1 timer 241 tp3ioc0 tmp3 i/o control register 0 timer 242 tp3ioc1 tmp3 i/o control register 1 timer 243 tp3ioc2 tmp3 i/o control register 2 timer 244 tp3opt0 tmp3 option register 0 timer 245 tp3ovic interrupt control register intc 802 tp4ccic0 interrupt control register intc 802 tp4ccic1 interrupt control register intc 802 tp4ccr0 tmp4 capture/compare register 0 timer 246 tp4ccr1 tmp4 capture/compare register 1 timer 248 tp4cnt tmp4 counter read buffer register timer 250 tp4ctl0 tmp4 control register 0 timer 240 tp4ctl1 tmp4 control register 1 timer 241 tp4ioc0 tmp4 i/o control register 0 timer 242 tp4ioc1 tmp4 i/o control register 1 timer 243 tp4ioc2 tmp4 i/o control register 2 timer 244 tp4opt0 tmp4 option register 0 timer 245 tp4ovic interrupt control register intc 802 tp5ccic0 interrupt control register intc 802 tp5ccic1 interrupt control register intc 802 tp5ccr0 tmp5 capture/compare register 0 timer 246 tp5ccr1 tmp5 capture/compare register 1 timer 248 tp5cnt tmp5 counter read buffer register timer 250 tp5ctl0 tmp5 control register 0 timer 240 tp5ctl1 tmp5 control register 1 timer 241 tp5ioc0 tmp5 i/o control register 0 timer 242 tp5ioc1 tmp5 i/o control register 1 timer 243 tp5ioc2 tmp5 i/o control register 2 timer 244 tp5opt0 tmp5 option register 0 timer 245 tp5ovic interrupt control register intc 802 tq0ccic0 interrupt control register intc 802
v850es/jg3-l appendix c register index r01uh0165ej0700 rev.7.00 page 1090 of 1113 sep 22, 2011 (10/11) symbol name unit page tq0ccic1 interrupt control register intc 802 tq0ccic2 interrupt control register intc 802 tq0ccic3 interrupt control register intc 802 tq0ccr0 tmq0 capture/compare register 0 timer 341 tq0ccr1 tmq0 capture/compare register 1 timer 343 tq0ccr2 tmq0 capture/compare register 2 timer 345 tq0ccr3 tmq0 capture/compare register 3 timer 347 tq0cnt tmq0 counter read buffer register timer 348 tq0ctl0 tmq0 control register 0 timer 335 tq0ctl1 tmq0 control register 1 timer 336 tq0ioc0 tmq0 i/o control register 0 timer 337 tq0ioc1 tmq0 i/o control register 1 timer 338 tq0ioc2 tmq0 i/o control register 2 timer 339 tq0opt0 tmq0 option register 0 timer 340 tq0ovic interrupt control register intc 802 ua0ctl0 uarta0 control register 0 uarta 558 ua0ctl1 uarta0 control register 1 uarta 582 ua0ctl2 uarta0 control register 2 uarta 583 ua0opt0 uarta0 option control register 0 uarta 560 ua0ric interrupt control register intc 802 ua0rx uarta0 receive data register uarta 563 ua0str uarta0 status register uarta 561 ua0tic interrupt control register intc 802 ua0tx uarta0 transmit data register uarta 564 ua1ctl0 uarta1 control register 0 uarta 558 ua1ctl1 uarta1 control register 1 uarta 582 ua1ctl2 uarta1 control register 2 uarta 583 ua1opt0 uarta1 option control register 0 uarta 560 ua1ric interrupt control register intc 802 ua1rx uarta1 receive data register uarta 563 ua1str uarta1 status register uarta 561 ua1tic interrupt control register intc 802 ua1tx uarta1 transmit data register uarta 564 ua2ctl0 uarta2 control register 0 uarta 558 ua2ctl1 uarta2 control register 1 uarta 582 ua2ctl2 uarta2 control register 2 uarta 583 ua2opt0 uarta2 option control register 0 uarta 560 ua2ric interrupt control register intc 802 ua2rx uarta2 receive data register uarta 563 ua2str uarta2 status register uarta 561 ua2tic interrupt control register intc 802 ua2tx uarta2 transmit data register uarta 564 ua3ctl0 uarta3 control register 0 uarta 558 ua3ctl1 uarta3 control register 1 uarta 582 ua3ctl2 uarta3 control register 2 uarta 583
v850es/jg3-l appendix c register index r01uh0165ej0700 rev.7.00 page 1091 of 1113 sep 22, 2011 (11/11) symbol name unit page ua3opt0 uarta3 option control register 0 uarta 560 ua3ric interrupt control register intc 802 ua3rx uarta3 receive data register uarta 563 ua3str uarta3 status register uarta 561 ua3tic interrupt control register intc 802 ua3tx uarta3 transmit data register uarta 564 ua4ctl0 uarta4 control register 0 uarta 558 ua4ctl1 uarta4 control register 1 uarta 582 ua4ctl2 uarta4 control register 2 uarta 583 ua4opt0 uarta4 option control register 0 uarta 560 ua4ric interrupt control register intc 802 ua4rx uarta4 receive data register uarta 563 ua4str uarta4 status register uarta 561 ua4tic interrupt control register intc 802 ua4tx uarta4 transmit data register uarta 564 ua5ctl0 uarta5 control register 0 uarta 558 ua5ctl1 uarta5 control register 1 uarta 582 ua5ctl2 uarta5 control register 2 uarta 583 ua5opt0 uarta5 option control register 0 uarta 560 ua5ric interrupt control register intc 802 ua5rx uarta5 receive data register uarta 563 ua5str uarta5 status register uarta 561 ua5tic interrupt control register intc 802 ua5tx uarta5 transmit data register uarta 564 uc0ctl0 uartc0 control register 0 uartc 595 uc0ctl1 uartc0 control register 1 uartc 621 uc0ctl2 uartc0 control register 2 uartc 622 uc0opt0 uartc0 option control register 0 uartc 597 uc0opt1 uartc0 option control register 1 uartc 599 uc0ric interrupt control register intc 802 uc0rx uartc0 receive data register uartc 602 uc0rxl uartc0 receive data register l uartc 602 uc0str uartc0 status register uartc 600 uc0tic interrupt control register intc 802 uc0tx uartc0 transmit data register uartc 603 uc0txl uartc0 transmit data register l uartc 603 vswc system wait control register cpu 93 wdte watchdog timer enable register wdt 496 wdtm2 watchdog timer mode register 2 wdt 494 wtic interrupt control register intc 802 wtiic interrupt control register intc 802 wtm watch timer operation mode register wt 455
v850es/jg3-l appendix d instruction set list r01uh0165ej0700 rev.7.00 page 1092 of 1113 sep 22, 2011 appendix d instruction set list d.1 conventions (1) register symbols u sed to describe operands register symbol explanation reg1 general-purpose registers: used as source registers. reg2 general-purpose registers: used main ly as destination registers. also used as source register in some instructions. reg3 general-purpose registers: used mainly to store the remainders of division result s and the higher 32 bits of multiplication results. bit#3 3-bit data for specifying the bit number immx x bit immediate data dispx x bit displacement data regid system register number vector 5-bit data that specifies the trap vector (00h to 1fh) cccc 4-bit data that shows the conditions code sp stack pointer (r3) ep element pointer (r30) listx x item register list (2) register symbols used to describe opcodes register symbol explanation r 1-bit data of a code that specifies reg1 or regid r 1-bit data of the code that specifies reg2 w 1-bit data of the code that specifies reg3 d 1-bit displacement data i 1-bit immediate data (indicates th e higher bits of immediate data) i 1-bit immediate data cccc 4-bit data that shows the condition codes cccc 4-bit data that shows the condition codes of bcond instruction bbb 3-bit data for specifying the bit number l 1-bit data that specifies a program register in the register list
v850es/jg3-l appendix d instruction set list r01uh0165ej0700 rev.7.00 page 1093 of 1113 sep 22, 2011 (3) register symbols used in operations register symbol explanation input for gr [ ] general-purpose register sr [ ] system register zero-extend (n) expand n with zeros until word length. sign-extend (n) expand n with signs until word length. load-memory (a, b) read size b data from address a. store-memory (a, b, c) write data b into address a in size c. load-memory-bit (a, b) read bit b of address a. store-memory-bit (a, b, c) write c to bit b of address a. saturated (n) execute saturated processing of n (n is a 2?s complement). if, as a result of calculations, n 7fffffffh, let it be 7fffffffh. n 80000000h, let it be 80000000h. result reflects the results in a flag. byte byte (8 bits) halfword half word (16 bits) word word (32 bits) + addition ? subtraction ll bit concatenation multiplication division % remainder from division results and logical product or logical sum xor exclusive or not logical negation logically shift left by logical shift left logically shift right by logical shift right arithmetically shift right by arithmetic shift right (4) register symbols u sed in execution clock register symbol explanation i if executing another instruction immediately a fter executing the first instruction (issue). r if repeating execution of the same instruction immedi ately after executing the first instruction (repeat). l if using the results of instruction execution in the instruction immediately afte r the execution (latency).
v850es/jg3-l appendix d instruction set list r01uh0165ej0700 rev.7.00 page 1094 of 1113 sep 22, 2011 (5) register symbols used in flag operations identifier explanation (blank) no change 0 clear to 0 x set or cleared in accordance with the results. r previously saved values are restored. (6) condition codes condition code (cccc) condition formula explanation 0 0 0 0 ov = 1 overflow 1 0 0 0 ov = 0 no overflow 0 0 0 1 cy = 1 carry lower (less than) 1 0 0 1 cy = 0 no carry not lower (greater than or equal) 0 0 1 0 z = 1 zero 1 0 1 0 z = 0 not zero 0 0 1 1 (cy or z) = 1 not higher (less than or equal) 1 0 1 1 (cy or z) = 0 higher (greater than) 0 1 0 0 s = 1 negative 1 1 0 0 s = 0 positive 0 1 0 1 ? always (unconditional) 1 1 0 1 sat = 1 saturated 0 1 1 0 (s xor ov) = 1 less than signed 1 1 1 0 (s xor ov) = 0 greater than or equal signed 0 1 1 1 ((s xor ov) or z) = 1 less than or equal signed 1 1 1 1 ((s xor ov) or z) = 0 greater than signed
v850es/jg3-l appendix d instruction set list r01uh0165ej0700 rev.7.00 page 1095 of 1113 sep 22, 2011 d.2 instruction set (in alphabetical order) (1/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat reg1,reg2 r r rr r0 01 11 0 rrrrr gr[reg2] gr[reg2]+gr[reg1] 1 1 1 add imm5,reg2 r r r r r 0 1 0 010iiiii gr[reg2] gr[reg2]+sign-extend(imm5) 1 1 1 addi imm16,reg1,reg2 r r rr r1 10 00 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]+sign-extend(imm16) 1 1 1 and reg1,reg2 r r rr r0 01 01 0 rrrrr gr[reg2] gr[reg2]and gr[reg1] 1 1 1 0 andi imm16,reg1,reg2 r r rr r1 10 11 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]and zero-extend(imm16) 1 1 1 0 when conditions are satisfied 2 note 2 2 note 2 2 note 2 bcond disp9 ddddd1011dddcccc note 1 if conditions are satisfied then pc pc+sign-extend(disp9) when conditions are not satisfied 1 1 1 bsh reg2,reg3 r r r r r 1 1 1 1 1 1 0 0 0 0 0 wwwww01101000010 gr[reg3] gr[reg2] (23 : 16) ll gr[reg2] (31 : 24) ll gr[reg2] (7 : 0) ll gr[reg2] (15 : 8) 1 1 1 0 bsw reg2,reg3 r r r r r 1 1 1 1 1 1 0 0 0 0 0 wwwww01101000000 gr[reg3] gr[reg2] (7 : 0) ll gr[reg2] (15 : 8) ll gr [reg2] (23 : 16) ll gr[reg2] (31 : 24) 1 1 1 0 callt imm6 0000001000iiiiii ctpc pc+2(return pc) ctpsw psw adr ctbp+zero-extend(imm6 logically shift left by 1) pc ctbp+zero-extend(load-memory(adr,halfword)) 4 4 4 bit#3,disp16[reg1] 10bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not(load-memory-bit(adr,bit#3)) store-memory-bit(adr,bit#3,0) 3 note 3 3 note 3 3 note 3 clr1 reg2,[reg1] r r rr r1 11 11 1 rrrrr 0000000011100100 adr gr[reg1] z flag not(load-memory-bit(adr,reg2)) store-memory-bit(adr,reg2,0) 3 note 3 3 note 3 3 note 3 cccc,imm5,reg2,reg3 r r r r r 1 1 1 111iiiii wwwww011000cccc0 if conditions are satisfied then gr[reg3] sign-extended(imm5) else gr[reg3] gr[reg2] 1 1 1 cmov cccc,reg1,reg2,reg3 r r r r r 1 1 1 1 1 1 r r r r wwwww011001cccc0 if conditions are satisfied then gr[reg3] gr[reg1] else gr[reg3] gr[reg2] 1 1 1 reg1,reg2 r r rr r0 01 11 1 rrrrr result gr[reg2]?gr[reg1] 1 1 1 cmp imm5,reg2 r r r r r 0 1 0 011iiiii result gr[reg2]?sign-extend(imm5) 1 1 1 ctret 0000011111100000 0000000101000100 pc ctpc psw ctpsw 3 3 3 r r r r r dbret 0000011111100000 0000000101000110 pc dbpc psw dbpsw 3 3 3 r r r r r
v850es/jg3-l appendix d instruction set list r01uh0165ej0700 rev.7.00 page 1096 of 1113 sep 22, 2011 (2/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat dbtrap 1111100001000000 dbpc pc+2 (restored pc) dbpsw psw psw.np 1 psw.ep 1 psw.id 1 pc 00000060h 3 3 3 di 0000011111100000 0000000101100000 psw.id 1 1 1 1 imm5,list12 0000011001iiiiil lllllllllll00000 sp sp+zero-extend(imm5 logically shift left by 2) gr[reg in list12] load-memory(sp,word) sp sp+4 repeat 2 steps above until all regs in list12 is loaded n+1 note 4 n+1 note 4 n+1 note 4 dispose imm5,list12,[reg1] 0 0 0 0 0 1 1 0 0 1 i i i i i l lllllllllllrrrrr note 5 sp sp+zero-extend(imm5 logically shift left by 2) gr[reg in list12] load-memory(sp,word) sp sp+4 repeat 2 steps above until all regs in list12 is loaded pc gr[reg1] n+3 note 4 n+3 note 4 n+3 note 4 div reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01011000000 gr[reg2] gr[reg2]gr[reg1] gr[reg3] gr[reg2]%gr[reg1] 35 35 35 reg1,reg2 r r rr r0 00 01 0 rrrrr gr[reg2] gr[reg2]gr[reg1] note 6 35 35 35 divh reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01010000000 gr[reg2] gr[reg2]gr[reg1] note 6 gr[reg3] gr[reg2]%gr[reg1] 35 35 35 divhu reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01010000010 gr[reg2] gr[reg2]gr[reg1] note 6 gr[reg3] gr[reg2]%gr[reg1] 34 34 34 divu reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01011000010 gr[reg2] gr[reg2]gr[reg1] gr[reg3] gr[reg2]%gr[reg1] 34 34 34 ei 1000011111100000 0000000101100000 psw.id 0 1 1 1 halt 0000011111100000 0000000100100000 stop 1 1 1 hsw reg2,reg3 r r r r r 1 1 1 1 1 1 0 0 0 0 0 wwwww01101000100 gr[reg3] gr[reg2](15 : 0) ll gr[reg2] (31 : 16) 1 1 1 0 jarl disp22,reg2 r r r r r 1 1 1 1 0 d d d d d d ddddddddddddddd0 note 7 gr[reg2] pc+4 pc pc+sign-extend(disp22) 2 2 2 jmp [reg1] 00000000011rrrrr pc gr[reg1] 3 3 3 jr disp22 0000011110dddddd ddddddddddddddd0 note 7 pc pc+sign-extend(disp22) 2 2 2 ld.b disp16[reg1],reg2 r r rr r1 11 00 0 rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) gr[reg2] sign-extend(load-memory(adr,byte)) 1 1 note 11 ld.bu disp16[reg1],reg2 r r rr r1 11 10 b rrrrr dddddddddddddd1 notes 8, 10 adr gr[reg1]+sign-extend(disp16) gr[reg2] zero-extend(load-memory(adr,byte)) 1 1 note 11
v850es/jg3-l appendix d instruction set list r01uh0165ej0700 rev.7.00 page 1097 of 1113 sep 22, 2011 (3/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat ld.h disp16[reg1],reg2 rrrrr111001rrrrr ddddddddddddddd0 note 8 adr gr[reg1]+sign-extend(disp16) gr[reg2] sign-extend(load-memory(adr,halfword)) 1 1 note 11 other than regid = psw 1 1 1 ldsr reg2,regid rrrrr111111rrrrr 0000000000100000 note 12 sr[regid] gr[reg2] regid = psw 1 1 1 ld.hu disp16[reg1],reg2 r r rr r1 11 11 1 rrrrr ddddddddddddddd1 note 8 adr gr[reg1]+sign-extend(disp16) gr[reg2] zero-extend(load-memory(adr,halfword) 1 1 note 11 ld.w disp16[reg1],reg2 r r rr r1 11 00 1 rrrrr ddddddddddddddd1 note 8 adr gr[reg1]+sign-extend(disp16) gr[reg2] load-memory(adr,word) 1 1 note 11 reg1,reg2 r r rr r0 00 00 0 rrrrr gr[reg2] gr[reg1] 1 1 1 imm5,reg2 r r r r r 0 1 0 000iiiii gr[reg2] sign-extend(imm5) 1 1 1 mov imm32,reg1 00000110001rrrrr iiiiiiiiiiiiiiii iiiiiiiiiiiiiiii gr[reg1] imm32 2 2 2 movea imm16,reg1,reg2 r r rr r1 10 00 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]+sign-extend(imm16) 1 1 1 movhi imm16,reg1,reg2 r r rr r1 10 01 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]+(imm16 ll 0 16 ) 1 1 1 reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01000100000 gr[reg3] ll gr[reg2] gr[reg2]xgr[reg1] note 14 1 4 5 mul imm9,reg2,reg3 rrrrr111111iiiii wwwww01001iiii00 note 13 gr[reg3] ll gr[reg2] gr[reg2]xsign-extend(imm9) 1 4 5 reg1,reg2 r r rr r0 00 11 1 rrrrr gr[reg2] gr[reg2] note 6 xgr[reg1] note 6 1 1 2 mulh imm5,reg2 r r r r r 0 1 0 111iiiii gr[reg2] gr[reg2] note 6 xsign-extend(imm5) 1 1 2 mulhi imm16,reg1,reg2 r r rr r1 10 11 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1] note 6 ximm16 1 1 2 reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01000100010 gr[reg3] ll gr[reg2] gr[reg2]xgr[reg1] note 14 1 4 5 mulu imm9,reg2,reg3 rrrrr111111iiiii wwwww01001iiii10 note 13 gr[reg3] ll gr[reg2] gr[reg2]xzero-extend(imm9) 1 4 5 nop 0000000000000000 pass at least one clock cycle doing nothing. 1 1 1 not reg1,reg2 r r rr r0 00 00 1 rrrrr gr[reg2] not(gr[reg1]) 1 1 1 0 bit#3,disp16[reg1] 01bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not(load-memory-bit(adr,bit#3)) store-memory-bit(adr,bit#3,z flag) 3 note 3 3 note 3 3 note 3 not1 reg2,[reg1] r r rr r1 11 11 1 rrrrr 0000000011100010 adr gr[reg1] z flag not(load-memory-bit(adr,reg2)) store-memory-bit(adr,reg2,z flag) 3 note 3 3 note 3 3 note 3
v850es/jg3-l appendix d instruction set list r01uh0165ej0700 rev.7.00 page 1098 of 1113 sep 22, 2011 (4/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat or reg1,reg2 r r rr r0 01 00 0 rrrrr gr[reg2] gr[reg2]or gr[reg1] 1 1 1 0 ori imm16,reg1,reg2 r r rr r1 10 10 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]or zero-extend(imm16) 1 1 1 0 list12,imm5 0000011110iiiiil lllllllllll00001 store-memory(sp?4,gr[reg in list12],word) sp sp?4 repeat 1 step above until all regs in list12 is stored sp sp-zero-extend(imm5) n+1 note 4 n+1 note 4 n+1 note 4 prepare list12,imm5, sp/imm note 15 0000011110iiiiil lllllllllllff011 imm16/imm32 note 16 store-memory(sp?4,gr[reg in list12],word) sp sp+4 repeat 1 step above until all regs in list12 is stored sp sp-zero-extend (imm5) ep sp/imm n+2 note 4 note 17 n+2 note 4 note 17 n+2 note 4 note 17 reti 0000011111100000 0000000101000000 if psw.ep=1 then pc eipc psw eipsw else if psw.np=1 then pc fepc psw fepsw else pc eipc psw eipsw 3 3 3 r r r r r reg1,reg2 r r rr r1 11 11 1 rrrrr 0000000010100000 gr[reg2] gr[reg2]arithmetically shift right by gr[reg1] 1 1 1 0 sar imm5,reg2 rrrrr010101iiiii gr[reg2] gr[reg2]arithmetically shift right by zero-extend (imm5) 1 1 1 0 sasf cccc,reg2 rrrrr1111110cccc 0000001000000000 if conditions are satisfied then gr[reg2] (gr[reg2]logically shift left by 1) or 00000001h else gr[reg2] (gr[reg2]logically shift left by 1) or 00000000h 1 1 1 reg1,reg2 r r rr r0 00 11 0 rrrrr gr[reg2] saturated(gr[reg2]+gr[reg1]) 1 1 1 satadd imm5,reg2 rrrrr010001iiiii gr[reg2] saturated(gr[reg2]+sign-extend(imm5) 1 1 1 satsub reg1,reg2 r r rr r0 00 10 1 rrrrr gr[reg2] saturated(gr[reg2]?gr[reg1]) 1 1 1 satsubi imm16,reg1,reg2 r r rr r1 10 01 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] saturated(gr[reg1]?sign-extend(imm16) 1 1 1 satsubr reg1,reg2 r r rr r0 00 10 0 rrrrr gr[reg2] saturated(gr[reg1]?gr[reg2]) 1 1 1 setf cccc,reg2 rrrrr1111110cccc 0000000000000000 if conditions are satisfied then gr[reg2] 00000001h else gr[reg2] 00000000h 1 1 1
v850es/jg3-l appendix d instruction set list r01uh0165ej0700 rev.7.00 page 1099 of 1113 sep 22, 2011 (5/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat bit#3,disp16[reg1] 00bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not (load-memory-bit(adr,bit#3)) store-memory-bit(adr,bit#3,1) 3 note 3 3 note 3 3 note 3 set1 reg2,[reg1] r r rr r1 11 11 1 rrrrr 0000000011100000 adr gr[reg1] z flag not(load-memory-bit(adr,reg2)) store-memory-bit(adr,reg2,1) 3 note 3 3 note 3 3 note 3 reg1,reg2 r r rr r1 11 11 1 rrrrr 0000000011000000 gr[reg2] gr[reg2] logically shift left by gr[reg1] 1 1 1 0 shl imm5,reg2 rrrrr010110iiiii gr[reg2] gr[reg2] logically shift left by zero-extend(imm5) 1 1 1 0 reg1,reg2 r r rr r1 11 11 1 rrrrr 0000000010000000 gr[reg2] gr[reg2] logically shift right by gr[reg1] 1 1 1 0 shr imm5,reg2 rrrrr010100iiiii gr[reg2] gr[reg2] logically shift right by zero-extend(imm5) 1 1 1 0 sld.b disp7[ep],reg2 r r r r r 0 1 1 0 d d d d d d d adr ep+zero-extend(disp7) gr[reg2] sign-extend(load-memory(adr,byte)) 1 1 note 9 sld.bu disp4[ep],reg2 rrrrr0000110dddd note 18 adr ep+zero-extend(disp4) gr[reg2] zero-extend(load-memory(adr,byte)) 1 1 note 9 sld.h disp8[ep],reg2 r r r r r 1 0 0 0 d d d d d d d note 19 adr ep+zero-extend(disp8) gr[reg2] sign-extend(load-memory(adr,halfword)) 1 1 note 9 sld.hu disp5[ep],reg2 rrrrr0000111dddd notes 18, 20 adr ep+zero-extend(disp5) gr[reg2] zero-extend(load-memory(adr,halfword)) 1 1 note 9 sld.w disp8[ep],reg2 rrrrr1010dddddd0 note 21 adr ep+zero-extend(disp8) gr[reg2] load-memory(adr,word) 1 1 note 9 sst.b reg2,disp7[ep] r r r r r 0 1 1 1 d d d d d d d adr ep+zero-extend(disp7) store-memory(adr,gr[reg2],byte) 1 1 1 sst.h reg2,disp8[ep] r r r r r 1 0 0 1 d d d d d d d note 19 adr ep+zero-extend(disp8) store-memory(adr,gr[reg2],halfword) 1 1 1 sst.w reg2,disp8[ep] rrrrr1010dddddd1 note 21 adr ep+zero-extend(disp8) store-memory(adr,gr[reg2],word) 1 1 1 st.b reg2,disp16[reg1] r r rr r1 11 01 0 rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) store-memory(adr,gr[reg2],byte) 1 1 1 st.h reg2,disp16[reg1] r r rr r1 11 01 1 rrrrr ddddddddddddddd0 note 8 adr gr[reg1]+sign-extend(disp16) store-memory (adr,gr[reg2], halfword) 1 1 1 st.w reg2,disp16[reg1] rrrrr111011rrrrr ddddddddddddddd1 note 8 adr gr[reg1]+sign-extend(disp16) store-memory (adr,gr[reg2], word) 1 1 1 stsr regid,reg2 r r rr r1 11 11 1 rrrrr 0000000001000000 gr[reg2] sr[regid] 1 1 1
v850es/jg3-l appendix d instruction set list r01uh0165ej0700 rev.7.00 page 1100 of 1113 sep 22, 2011 (6/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat sub reg1,reg2 r r rr r0 01 10 1 rrrrr gr[reg2] gr[reg2]?gr[reg1] 1 1 1 subr reg1,reg2 r r rr r0 01 10 0 rrrrr gr[reg2] gr[reg1]?gr[reg2] 1 1 1 switch reg1 00000000010rrrrr adr (pc+2) + (gr [reg1] logically shift left by 1) pc (pc+2) + (sign-extend (load-memory (adr,halfword)) logically shift left by 1 5 5 5 sxb reg1 00000000101rrrrr gr[reg1] sign-extend (gr[reg1] (7 : 0)) 1 1 1 sxh reg1 00000000111rrrrr gr[reg1] sign-extend (gr[reg1] (15 : 0)) 1 1 1 trap vector 00000111111iiiii 0000000100000000 eipc pc+4 (restored pc) eipsw psw ecr.eicc interrupt code psw.ep 1 psw.id 1 pc 00000040h (when vector is 00h to 0fh) 00000050h (when vector is 10h to 1fh) 3 3 3 tst reg1,reg2 r r rr r0 01 01 1 rrrrr result gr[reg2] and gr[reg1] 1 1 1 0 bit#3,disp16[reg1] 11bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not (load-memory-bit (adr,bit#3)) 3 note 3 3 note 3 3 note 3 tst1 reg2, [reg1] r r rr r1 11 11 1 rrrrr 0000000011100110 adr gr[reg1] z flag not (load-memory-bit (adr,reg2)) 3 note 3 3 note 3 3 note 3 xor reg1,reg2 r r rr r0 01 00 1 rrrrr gr[reg2] gr[reg2] xor gr[reg1] 1 1 1 0 xori imm16,reg1,reg2 r r rr r1 10 10 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1] xor zero-extend (imm16) 1 1 1 0 zxb reg1 00000000100rrrrr gr[reg1] zero-extend (gr[reg1] (7 : 0)) 1 1 1 zxh reg1 00000000110rrrrr gr[reg1] zero-extend (gr[reg1] (15 : 0)) 1 1 1 notes 1. dddddddd: higher 8 bits of disp9. 2. 3 if there is an instruction that rewrites the contents of the psw immediately before. 3. if there is no wait state (3 + the number of read access wait states). 4. n is the total number of list12 load registers. (according to the number of wait states. also, if there are no wait states, n is the total num ber of list12 registers. if n = 0, same operation as when n = 1) 5. rrrrr: other than 00000. 6. the lower halfword data only are valid. 7. ddddddddddddddddddddd: the higher 21 bits of disp22. 8. ddddddddddddddd: the higher 15 bits of disp16. 9. according to the number of wait stat es (1 if there are no wait states). 10. b: bit 0 of disp16. 11. according to the number of wait stat es (2 if there are no wait states).
v850es/jg3-l appendix d instruction set list r01uh0165ej0700 rev.7.00 page 1101 of 1113 sep 22, 2011 notes 12. in this instruction, for convenience of mnemonic de scription, the source register is made reg2, but the reg1 field is used in the opcode. t herefore, the meaning of register specification in the mnemonic description and in the opcode differs from other instructions. rrrrr = regid specification rrrrr = reg2 specification 13. iiiii: lower 5 bits of imm9. iiii: higher 4 bits of imm9. 14. do not specify the same register fo r general-purpose registers reg1 and reg3. 15. sp/imm: specified by bits 19 and 20 of the sub-opcode. 16. ff = 00: load sp in ep. 01: load sign expanded 16-bit immediate data (bits 47 to 32) in ep. 10: load 16-bit logically left shifted 16-bit immediate data (bits 47 to 32) in ep. 11: load 32-bit immediate data (bits 63 to 32) in ep. 17. if imm = imm32, n + 3 clocks. 18. rrrrr: other t han 00000. 19. ddddddd: higher 7 bits of disp8. 20. dddd: higher 4 bits of disp5. 21. dddddd: higher 6 bits of disp8.
v850es/jg3-l appendix e revision history r01uh0165ej0700 rev.7.00 page 1102 of 1113 sep 22, 2011 appendix e revision history e.1 major revisions in this edition (1/2) page description p. 94 modification of caution to 3. 4. 9 (1) accessing special on-chip peripheral i/o registers p. 866 addition of note 1 to figure 23-2. rtc backup mode status transition p. 992 addition of caution to 33.3 operating conditions p. 1031 addition of caution to 34.3 operating conditions pp. 1065. 1066 modification of table 36-1. surface mounting type soldering conditions
v850es/jg3-l appendix e revision history r01uh0165ej0700 rev.7.00 page 1103 of 1113 sep 22, 2011 e.2 revision history of previous editions a history of the revisions up to this edition is shown below. ?applied to:? indicates the chapters to which the revision was applied. (1/8) edition description applied to: ? under development mass production pd70f3737gc-ueu-ax, 70f3738gc-ueu-ax throughout modification of 1.4 ordering information modification of 1.5 pin configuration (top view) chapter 1 introduction modification of 16.2 features modification of note in 16.4 (2) csibn control register 1 (cbnctl1) modification of 16.8.1 baud rate generation chapter 16 3-wire variable-length serial i/o (csib) modification of table 28-2 basic functions modification of table 28- 3 security functions modification of table 28-4 security setting modification of table 28-7 flash memory control commands chapter 28 flash memory modification of main clock oscillator characteristics in chapter 30 electrical specifications modification of subclock oscillator characteristics in chapter 30 electrical specifications modification of dc characteristics in chapter 30 electrical specifications modification of bus timing (1) (b) read/write cycle (clkout synchronous): in multiplexed bus mode in chapter 30 electrical specifications modification of bus timing (2) (a) read cycle (clkout asynchronous): in separate bus mode in chapter 30 electrical specifications modification of uart timing of bu s timing in chapter 30 electrical specifications modification of csib timing of bus timing in chapter 30 electrical specifications chapter 30 electrical specifications addition of chapter 32 recommended soldering conditions chapter 32 recommended soldering conditions 2nd addition of appendix e revision history appendix e revision history
v850es/jg3-l appendix e revision history r01uh0165ej0700 rev.7.00 page 1104 of 1113 sep 22, 2011 (2/8) edition description applied to: ? addition of products pd70f3737f1-gc-cah-a, 70f3738f1-cah-a throughout modification of table 1-1. v850es/jx3-l product list chapter 1 introduction addition of figure 3-10 si gn extension in data space chapter 3 cpu function modification of table 5-3 pin statuses when internal rom, internal ram, or on-chip peripheral i/o is accessed addition of 5.11 sram connection examples chapter 5 bus control function addition of 6.4.3 exte rnal clock signal input addition of 6.6 how to connect a resonator chapter 6 clock generator addition of 7.2.1 pins used by tmpn addition of 7.2.2 interrupts addition of 7.4 (1) basic counter operation addition of 7.4 (2) anytime write and batch write addition of 7.4.1 (3) operation of interval timer based on input of external event count modification of figure 7-28 r egister settings in external trigger pulse output mode modification of figure 7-40 register se ttings in one-shot pulse output mode chapter 7 16-bit timer/event counter p (tmp) addition of 8.2.1 pins used by tmq0 addition of 8.2.2 interrupts addition of 8.4 (1) basic counter operation addition of 8.4 (2) anytime write and batch write addition of 8.4.1 (3) operation of interval timer based on input of external event count modification of figure 8-28 r egister settings in external trigger pulse output mode modification of figure 8-40 register se ttings in one-shot pulse output mode chapter 8 16-bit timer/event counter q (tmq) modification of figure 13-4 example of timi ng in continuous select mode (ada0s register = 01h) modification of figure 13-5 example of timing in continuous scan mode (ada0s register = 03h) modification of figure 13-6 exam ple of timing in one-shot se lect mode (ada0s register = 01h) modification of figure 13-7 example of timi ng in one-shot scan mode (ada0s register = 03h) modification of figure 13-8 example of timing in continuous select mode (when power-fail comparison is made: ada0pf m.ada0pfc bit = 0, ada0s register = 01h) modification of figure 13-9 exampl e of timing in continuous scan mode (when power-fail comparison is made: ada0pf m.ada0pfc bit = 0, ada0s register = 03h) modification of figure 13-10 example of timing in one-shot select mode (when power-fail comparison is made: ada0pf m.ada0pfc bit = 1, ada0s register = 01h) 3rd modification of figure 13-11 exampl e of timing in one-shot scan mode (when power-fail comparison is made: ada0pf m.ada0pfc bit = 0, ada0s register = 03h) chapter 13 a/d converter
v850es/jg3-l appendix e revision history r01uh0165ej0700 rev.7.00 page 1105 of 1113 sep 22, 2011 (3/8) edition description applied to: modification of figure 14-1 block diagram of d/a converter chapter 14 d/a converter addition of 15.2.1 pin functions of each channel addition of a note for figure 15-7 continuous transmission processing chapter 15 asynchronous serial interface a (uarta) modification of 16.1 features addition of 16.2.1 pin functions of each channel addition of note to figure 16-11 singl e transfer mode operation (slave mode, transmission mode) addition of note to figure 16-13 single tr ansfer mode operation (slave mode, reception mode) addition of note to figure 16-15 singl e transfer mode operation (slave mode, transmission/reception mode) modification of figure 16-19 continuous tran sfer mode operation (master mode, reception mode) modification of figure 16-21 continuous transfer mode operation (master mode, transmission/reception mode) addition of note to figure 16-23 conti nuous transfer mode operation (slave mode, transmission mode) modification of figure 16-25 continuous tran sfer mode operation (slave mode, reception mode) modification of figure 16-27 continuous transfer mode operation (slave mode, transmission/reception mode) chapter 16 clocked serial interface b (csib) modification of 18.13 (4) (a) temporarily stop transfer of all dma channels chapter 18 dma function (dma controller) addition of 20.2 pin functions chapter 20 key interrupt function modification of caution 2 in 21.4.1 setting and operation status modification of caution 2 in 21.5.1 setting and operation status modification of caution 2 in 21.6.1 setting and operation status modification of caution 2 in 21.8.1 setting and operation status chapter 21 standby function modification of figure 22-7 reset fu nction operation flow chapter 22 reset function modification of figure 23-1 block diagr am of clock monitor chapter 23 clock monitor modification of figure 24-2 operation timing of low-voltage detector (lvimd bit = 1, low-voltage detection level: 2.80 v) modification of figure 24-3 operation timing of low-voltage detector (lvimd bit = 0, low-voltage detection level: 2.80 v) chapter 24 low-voltage detector (lvi) modification of note 3 in figure 29 -4 circuit connection example when uarta0/csib0/csib3 is used for communication interface chapter 29 on-chip debug function 3rd addition of 121-pin plastic fbga (8 8) to chapter 31 package drawings chapter 31 package drawings
v850es/jg3-l appendix e revision history r01uh0165ej0700 rev.7.00 page 1106 of 1113 sep 22, 2011 (4/8) edition description applied to: addition of pd70f3737f1-gc-cah-a and 70f3738f1-cah-a to chapter 32 recommended soldering conditions chapter 32 recommended soldering conditions 3rd addition of appendix e revision history appendix e revision history ? addition of products pd70f3792gc-ueu-ax pd70f3793gc-ueu-ax pd70f3792f1-cah-a pd70f3793f1-cah-a throughout modification of table 1-1. v850es/jx3-l product list modification of 1.2 features modification of 1.4 ordering information addition of products 100-pin plastic lqfp (fine pitch) (14 14) pd70f3792gc-ueu-ax, pd70f3793gc-ueu-ax addition of products 121-pin plastic fbga (8 8) pd70f3792f1-cah-a, pd70f3793f1-cah-a modification of pin functions modification of 1.6.1 internal block diagram addition of 1.6.2 (10) real-time counter (for watch) ( pd70f3792, 70f3793 only) addition of note to table 1-2. port functions chapter 1 introduction modification of 2.1 (1) port functions modification of 2.1 (2) non-port functions modification of 2.2 table 2-2. pin operation states in various modes modification of 2.3 pin i/o ci rcuit types, i/o buffer power supplies, and connection of unused pins chapter 2 pin functions addition of note to 3.1 features addition of 3.4.3 areas (1) (c) internal rom area addition of 3.4.3 areas (1) (d) internal rom area addition of 3.4.3 areas (2) (c) internal ram area addition of 3.4.3 areas (2) (d) internal ram area addition of 3.4.5 (1) program space modification of 3.4.6 pe ripheral i/o registers addition of 3.4.7 special registers chapter 3 cpu function addition of 4.1 features modification of figure 4- 1. port configuration addition of table 4-2. port configuration modification of 4.3.1 port 0 (3) modification of 4.3.1 port 0 (4) addition of 4.3.1 port 0 (5) modification of table 4-6. port 3 alternate-function pins modification of 4.3.3 port 3 (3) modification of table 4-10. port 9 alternate-function pins 4th modification of 4.3.7 port 9 (3) chapter 4 port functions
v850es/jg3-l appendix e revision history r01uh0165ej0700 rev.7.00 page 1107 of 1113 sep 22, 2011 (5/8) edition description applied to: modification of 4.3.7 port 9 (6) addition of figure 4-32. bl ock diagram of type u-16 chapter 4 port functions addition of note to table 5-1. bus contro l signals (when multiplexed bus is selected) addition of note to table 5-2. bus cont rol signals (when separate bus is selected) modification of figure 5-16. connecting sram wi th 8-bit data bus to v850es/jg3-l via 8-bit bus modification of figure 5-17. connecting two sram s with 8-bit data bus to v850es/jg3-l via 16-bit bus modification of figure 5-18. connecting sram with 16-bit data bus to v850es/jg3-l via 16-bit bus chapter 5 bus control function addition of 6.1 overview modification of figure 6-1. clock generator modification of 6.2 configuration (1) addition of 6.2 configuration (2) addition of 6.2 configuration (8) addition of caution to 6.3 registers (2) modification of table 6-1. oper ation status of each clock addition of 6.5.2 registers (5) chapter 6 clock generator modification of table 7-2. pins used by tmpn chapter 7 16-bit timer/event counter p (tmp) addition of chapter 11 real-time counter ( pd70f3792, 70f3793) chapter 11 real-time counter addition of remark to 16.1 features addition of remark to figure 16 -1. block diagram of uartan modification of table 16-2. pins used by uarta modification of 16.4 registers (1) modification of 16.4 registers (4) modification of 16.4 registers (5) modification of 16.4 registers (6) modification of 16.4 registers (7) modification of 16.7 dedicated baud rate generator (2) modification of 16.7 dedicated baud rate generator (3) chapter 16 asynchronous serial interface a (uarta) addition of chapter 17 asynchronous serial interface c (uartc) ( 0 3 9 ,0 3 9 3 ) ? 0 3 9 ,0 3 9 3 ) p 0 3 9 ,0 3 9 3 ) d 0 3 9 ,0 3 9 3 ) 7 0 3 9 ,0 3 9 3 ) 0 3 9 ,0 3 9 3 ) f 3 9 ,0 3 9 3 ) 3 9 ,0 3 9 3 ) 7 9 ,0 3 9 3 ) 9 ,0 3 9 3 ) 2 ,0 3 9 3 ) , 0 3 9 3 ) 0 3 9 3 ) 7 0 3 9 3 ) 0 3 9 3 ) f 3 9 3 ) 3 9 3 ) 7 9 3 ) 9 3 ) 3 ) ) chapter 17 asynchronous serial interface c (uartc) modification of table 18-2. pins used by csib chapter 18 clocked serial interface b (csib) 4th modification of table 20-2. dma st art factors chapter 20 dma function (dma controller)
v850es/jg3-l appendix e revision history r01uh0165ej0700 rev.7.00 page 1108 of 1113 sep 22, 2011 (6/8) edition description applied to: modification of 21.1 features modification of table 21-1. interrupt source list modification of table 21-3. inte rrupt control registers (xxicn) modification of 21.3.5 interrupt mask registers 0 to 3 (imr0 to imr3) chapter 21 interrupt servicing/excepti on processing function modification of table 23-1. standby modes modification of figure 23-1. status transition modification of table 23-3. operating status in halt mode modification of table 23-5. operating status in idle1 mode modification of table 23-7. operating status in idle2 mode modification of table 23-8. operating status in stop mode modification of table 23-9. operating status in low-voltage stop mode modification of table 23-11. operating status in subclock operation mode modification of table 23-12. operating stat us in low-voltage subclock operation mode modification of table 23-13. operat ing status in sub-idle mode modification of table 23-14. operating status in low-voltage sub-idle mode addition of 23.9 rtc backup mode ( pd70f3792, 70f3793 only) chapter 23 standby function modification of figure 26-1. block diagram of low-voltage detector modification of 26.3 registers (2) chapter 26 low-voltage detector (lvi) addition of figure 28-2. regulator ( pd70f3792, 70f3793) chapter 28 regulator modification of chapter 29 option byte chapter 29 option byte modification of chapter 30 flash memory modification of 30.1 features addition of figure 30-1. fl ash memory mapping (2/2) modification of 30.4 rewriting by dedicated flash memory programmer chapter 30 flash memory modification of figure 31-5. memory spaces where d ebug monitor programs are allocated chapter 31 on-chip debug function modification of 32.9 flash memory pr ogramming characteristics (1) chapter 32 electrical specifications addition of chapter 33 electrical specificat ions (target) (pd70f3792, 70f3793) chapter 33 electrical specifications (target) modification of a.4.1 when using iecube qb-v850essx2, qb-v850esjx3l modification of a.7 flash memory writing tools appendix a development tools 4th modification of appendix b major differences between products appendix b major differences between products
v850es/jg3-l appendix e revision history r01uh0165ej0700 rev.7.00 page 1109 of 1113 sep 22, 2011 (7/8) edition description applied to: modification of 2.1 (1) table 6-1. port functions chapter 2 pin functions modification of table 4-4. port 0 alter nate-function pins chapter 4 port functions modification of table 6-1. operation st atus of each clock chapter 6 clock generator modification of 17.4 (1) uartc0 c ontrol register 0 (uc0ctl0) (2/2) chapter 17 asynchronous serial interface c (uartc) modification of 20. 3 (6) dma trigger factor regist ers 0 to 3 (dtfr0 to dtfr3) chapter 20 dma function (dma controller) modification of table 23-11. o perating status in subclock operation mode chapter 23 standby function modification of table 24-1. hardware status on reset pin input modification of table 24-2. hardware stat us during watchdog timer 2 reset operation modification of table 24-3. hardware status during reset operation by low-voltage detector modification of 24.5 cautions. chapter 24 reset function modification of 32.9 (1) basi c characteristics chapter 32 electrical specifications modification of 33.5 r egulator characteristics modification of 33.8.10 (1) vdd power-down timing modification of 33.8.10 (2) vdd power-up timing 5th modification of 33.9 (1) basic characteristics chapter 33 electrical specifications (target) ? addition of products pd70f3841gc-ueu-ax pd70f3842gc-ueu-ax pd70f3841f1-cah-a pd70f3842f1-cah-a throughout modification of table 1-1. v850es/jx3-l product list modification of 1.2 features addition of 1.4 ordering information chapter 1 introduction addition of figure 3-3. data memo ry map (physical addresses) ( pd70f3841, 70f3842) addition of figure 3-5. program memory map ( pd70f3841, 70f3842) addition of 3. 4. 3 (3) expanded internal ram (24 kb) chapter 3 cpu function modification of table 5-3. pin statuses when in ternal rom, internal ram, on-chip peripheral i/o, or expanded internal ram is accessed addition of figure 5-2. data memo ry map: physical addresses ( pd70f3841, 70f3842) chapter 5 bus control function modification of 6.5.2(4) pll lockup time specification register (plls) modification of 6.5.3 usage chapter 6 clock generator addition of note to 11. 3 (1) real-time counter control register 0 (rc1cc0) addition of note to 11. 3 (2) real-tim e counter control register 1 (rc1cc1) addition of note to 11. 3 (3) real-tim e counter control register 2 (rc1cc2) addition of note to 11. 3 (4) real-tim e counter control register 3 (rc1cc3) addition of note to 11. 3 (5) sub-count register (rc1subc) addition of note to 11. 3 (6) second count register (rc1sec) addition of note to 11. 3 (7) minute count register (rc1min) addition of note to 11. 3 (8) hour count register (rc1hour) 6th addition of note to 11. 3 (9) day count register (rc1day) chapter 11 real-time counter
v850es/jg3-l appendix e revision history r01uh0165ej0700 rev.7.00 page 1110 of 1113 sep 22, 2011 (8/8) edition description applied to: addition of note to 11. 3 (10) da y-of-week count register (rc1week) addition of note to 11. 3 (11) month count register (rc1month) addition of note to 11. 3 (12) year count register (rc1year) addition of note to 11. 3 (13) watch error correction register (rc1subu) addition of note to 11. 3 (14) al arm minute setting register (rc1alm) addition of note to 11. 3 (15) al arm hour setting register (rc1alh) addition of note to 11. 3 (16) alarm day-of-week setting register (rc1alw) modification of figure 11-10. watch error correction example chapter 11 real-time counter addition of 20.1 features ? transfer sources and destinations modification of figure 20-1 . block diagram of dmac modification of 20. 3 (1) dma source address registers 0 to 3 (dsa0 to dsa3) modification of 20. 3 (2) dma destination address registers 0 to 3 (dda0 to dda3) modification of table 20-3. relationship be tween transfer sources and destinations addition of remark to 20.6 transfer types modification of table 20-4. number of execution clocks during dma cycle modification of 20. 13 (6) memory boundary modification of 20. 13 (8) bus arbitration for cpu chapter 20 dma function (dma controller) modification of 21.2.2 (2) from intwdt2 signal chapter 21 interrupt servicing/excepti on processing function modification of 23.9 rtc backup mode ( pd70f3792, 70f3793, 70f3841, 70f3842 only) chapter 23 standby function modification of 32. 4. 1(1) main clock oscillator characteristics modification of 32. 4. 3 pll characteristics modification of 32.6.2 s upply current c haracteristics chapter 32 electrical specifications ( pd70f3737, 70f3738) modification of 33.3 operating conditions modification of 33. 4. 1 (1) main clock oscillator characteristics addition of 33. 4. 1 (1) (a) kyocera kinseki corporation: crystal resonator (ta = ? 10 to +70c) addition of 33. 4. 1 (1) (b) murata mfg. co. ltd.: ceramic resonator (ta = ? 20 to +80c) addition of 33. 4. 2 (a) seiko instruments inc.: crystal resonator (ta = ? 40 to +85c) addition of 33. 4. 2 (b) citizen miyota co., ltd.: crystal resonator (ta = ? 40 to +85c) modification of 33.4.3 pll characteristics modification of 33.6.2 suppl y current characteristics modification of 33.7.3 (1) (a) read/ write cycle (asynchronous to clkout) addition of remark to 33.7.4 power on/power off/reset timing chapter 33 electrical specifications ( pd70f3792, 70f3793) addition of chapter 34 electric al specifications (target) ( pd70f3841, 70f3842) chapter 34 electrical specifications ( pd70f3841, 70f3842) modification of table 36-1. surface mounting type soldering conditions chapter 36 recommended soldering conditions 6th modification of appendix b major differences between products appendix b major differences between products
v850es/jg3-l user?s manual: hardware publication date: rev.6.00 february 28, 2011 rev.7.00 september 22, 2011 published by: renesas electronics corporation
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